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        "unknown_cycles": 0,
        "terminator": "JSR @loc_1891",
        "targets": [
          6289
        ]
      },
      {
        "start": 5735,
        "end": 5739,
        "label": "loc_1667",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1670",
        "targets": [
          5744
        ]
      },
      {
        "start": 5741,
        "end": 5741,
        "label": "loc_166D",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_18E7",
        "targets": [
          6375
        ]
      },
      {
        "start": 5744,
        "end": 5748,
        "label": "loc_1670",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1679",
        "targets": [
          5753
        ]
      },
      {
        "start": 5750,
        "end": 5750,
        "label": "loc_1676",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_194A",
        "targets": [
          6474
        ]
      },
      {
        "start": 5753,
        "end": 5757,
        "label": "loc_1679",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1682",
        "targets": [
          5762
        ]
      },
      {
        "start": 5759,
        "end": 5759,
        "label": "loc_167F",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1979",
        "targets": [
          6521
        ]
      },
      {
        "start": 5762,
        "end": 5762,
        "label": "loc_1682",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #0, @H'F6F1",
        "targets": []
      },
      {
        "start": 5766,
        "end": 5770,
        "label": "loc_1686",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_16D4",
        "targets": [
          5844
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      },
      {
        "start": 5772,
        "end": 5776,
        "label": "loc_168C",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1695",
        "targets": [
          5781
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      },
      {
        "start": 5778,
        "end": 5778,
        "label": "loc_1692",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1B2D",
        "targets": [
          6957
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      },
      {
        "start": 5781,
        "end": 5785,
        "label": "loc_1695",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_169E",
        "targets": [
          5790
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      },
      {
        "start": 5787,
        "end": 5787,
        "label": "loc_169B",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1B44",
        "targets": [
          6980
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      },
      {
        "start": 5790,
        "end": 5794,
        "label": "loc_169E",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_16A7",
        "targets": [
          5799
        ]
      },
      {
        "start": 5796,
        "end": 5796,
        "label": "loc_16A4",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1B5B",
        "targets": [
          7003
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      },
      {
        "start": 5799,
        "end": 5803,
        "label": "loc_16A7",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_16B0",
        "targets": [
          5808
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      },
      {
        "start": 5805,
        "end": 5805,
        "label": "loc_16AD",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1BA0",
        "targets": [
          7072
        ]
      },
      {
        "start": 5808,
        "end": 5812,
        "label": "loc_16B0",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_16B9",
        "targets": [
          5817
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      },
      {
        "start": 5814,
        "end": 5814,
        "label": "loc_16B6",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1BB6",
        "targets": [
          7094
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      },
      {
        "start": 5817,
        "end": 5821,
        "label": "loc_16B9",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_16C2",
        "targets": [
          5826
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      },
      {
        "start": 5823,
        "end": 5823,
        "label": "loc_16BF",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1BCC",
        "targets": [
          7116
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      },
      {
        "start": 5826,
        "end": 5830,
        "label": "loc_16C2",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_16CB",
        "targets": [
          5835
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      },
      {
        "start": 5832,
        "end": 5832,
        "label": "loc_16C8",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1B72",
        "targets": [
          7026
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      },
      {
        "start": 5835,
        "end": 5839,
        "label": "loc_16CB",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_16D4",
        "targets": [
          5844
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      },
      {
        "start": 5841,
        "end": 5841,
        "label": "loc_16D1",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1B89",
        "targets": [
          7049
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      },
      {
        "start": 5844,
        "end": 5848,
        "label": "loc_16D4",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1704",
        "targets": [
          5892
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      },
      {
        "start": 5850,
        "end": 5866,
        "label": "loc_16DA",
        "instruction_count": 5,
        "cycles_min": 39,
        "cycles_max": 43,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_16EF",
        "targets": [
          5871
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      },
      {
        "start": 5868,
        "end": 5868,
        "label": "loc_16EC",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1BE2",
        "targets": [
          7138
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      },
      {
        "start": 5871,
        "end": 5875,
        "label": "loc_16EF",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_16F8",
        "targets": [
          5880
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      },
      {
        "start": 5877,
        "end": 5877,
        "label": "loc_16F5",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "JSR @loc_1BF8",
        "targets": [
          7160
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      },
      {
        "start": 5880,
        "end": 5888,
        "label": "loc_16F8",
        "instruction_count": 3,
        "cycles_min": 27,
        "cycles_max": 27,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #0, @H'F6F3",
        "targets": []
      },
      {
        "start": 5892,
        "end": 5892,
        "label": "loc_1704",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 5893,
        "end": 5898,
        "label": "loc_1705",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_1744",
        "targets": [
          5956
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      },
      {
        "start": 5900,
        "end": 5904,
        "label": "loc_170C",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1736",
        "targets": [
          5942
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      },
      {
        "start": 5906,
        "end": 5910,
        "label": "loc_1712",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1736",
        "targets": [
          5942
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      },
      {
        "start": 5912,
        "end": 5916,
        "label": "loc_1718",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1726",
        "targets": [
          5926
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      },
      {
        "start": 5918,
        "end": 5922,
        "label": "loc_171E",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R1, @H'F734",
        "targets": []
      },
      {
        "start": 5926,
        "end": 5940,
        "label": "loc_1726",
        "instruction_count": 4,
        "cycles_min": 41,
        "cycles_max": 41,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1744",
        "targets": [
          5956
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      },
      {
        "start": 5942,
        "end": 5953,
        "label": "loc_1736",
        "instruction_count": 4,
        "cycles_min": 31,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
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      },
      {
        "start": 5956,
        "end": 5964,
        "label": "loc_1744",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
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      {
        "start": 5965,
        "end": 5970,
        "label": "loc_174D",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_178C",
        "targets": [
          6028
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      },
      {
        "start": 5972,
        "end": 5976,
        "label": "loc_1754",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_178C",
        "targets": [
          6028
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      },
      {
        "start": 5978,
        "end": 5982,
        "label": "loc_175A",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_177E",
        "targets": [
          6014
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      },
      {
        "start": 5984,
        "end": 5988,
        "label": "loc_1760",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BNE loc_176E",
        "targets": [
          5998
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      },
      {
        "start": 5990,
        "end": 5994,
        "label": "loc_1766",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R1, @H'F734",
        "targets": []
      },
      {
        "start": 5998,
        "end": 6012,
        "label": "loc_176E",
        "instruction_count": 4,
        "cycles_min": 41,
        "cycles_max": 41,
        "unknown_cycles": 0,
        "terminator": "BRA loc_178C",
        "targets": [
          6028
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      },
      {
        "start": 6014,
        "end": 6025,
        "label": "loc_177E",
        "instruction_count": 4,
        "cycles_min": 31,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
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      },
      {
        "start": 6028,
        "end": 6036,
        "label": "loc_178C",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6037,
        "end": 6042,
        "label": "loc_1795",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_17C0",
        "targets": [
          6080
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      },
      {
        "start": 6044,
        "end": 6048,
        "label": "loc_179C",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_17A7",
        "targets": [
          6055
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      },
      {
        "start": 6050,
        "end": 6053,
        "label": "loc_17A2",
        "instruction_count": 2,
        "cycles_min": 21,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BRA loc_17C0",
        "targets": [
          6080
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      },
      {
        "start": 6055,
        "end": 6059,
        "label": "loc_17A7",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_17B2",
        "targets": [
          6066
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      },
      {
        "start": 6061,
        "end": 6064,
        "label": "loc_17AD",
        "instruction_count": 2,
        "cycles_min": 21,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BRA loc_17C0",
        "targets": [
          6080
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      },
      {
        "start": 6066,
        "end": 6077,
        "label": "loc_17B2",
        "instruction_count": 4,
        "cycles_min": 31,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
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      },
      {
        "start": 6080,
        "end": 6088,
        "label": "loc_17C0",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6089,
        "end": 6094,
        "label": "loc_17C9",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_17F2",
        "targets": [
          6130
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      },
      {
        "start": 6096,
        "end": 6100,
        "label": "loc_17D0",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_17F2",
        "targets": [
          6130
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      },
      {
        "start": 6102,
        "end": 6117,
        "label": "loc_17D6",
        "instruction_count": 5,
        "cycles_min": 26,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_17EF",
        "targets": [
          6127
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      },
      {
        "start": 6119,
        "end": 6123,
        "label": "loc_17E7",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_17EF",
        "targets": [
          6127
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      },
      {
        "start": 6125,
        "end": 6125,
        "label": "loc_17ED",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 6127,
        "end": 6127,
        "label": "loc_17EF",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
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      },
      {
        "start": 6130,
        "end": 6138,
        "label": "loc_17F2",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6139,
        "end": 6144,
        "label": "loc_17FB",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_1824",
        "targets": [
          6180
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      },
      {
        "start": 6146,
        "end": 6150,
        "label": "loc_1802",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1824",
        "targets": [
          6180
        ]
      },
      {
        "start": 6152,
        "end": 6167,
        "label": "loc_1808",
        "instruction_count": 5,
        "cycles_min": 26,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1821",
        "targets": [
          6177
        ]
      },
      {
        "start": 6169,
        "end": 6173,
        "label": "loc_1819",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1821",
        "targets": [
          6177
        ]
      },
      {
        "start": 6175,
        "end": 6175,
        "label": "loc_181F",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 6177,
        "end": 6177,
        "label": "loc_1821",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
        ]
      },
      {
        "start": 6180,
        "end": 6188,
        "label": "loc_1824",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6189,
        "end": 6193,
        "label": "loc_182D",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1865",
        "targets": [
          6245
        ]
      },
      {
        "start": 6195,
        "end": 6200,
        "label": "loc_1833",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_185C",
        "targets": [
          6236
        ]
      },
      {
        "start": 6202,
        "end": 6206,
        "label": "loc_183A",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_185C",
        "targets": [
          6236
        ]
      },
      {
        "start": 6208,
        "end": 6223,
        "label": "loc_1840",
        "instruction_count": 5,
        "cycles_min": 26,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1859",
        "targets": [
          6233
        ]
      },
      {
        "start": 6225,
        "end": 6229,
        "label": "loc_1851",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1859",
        "targets": [
          6233
        ]
      },
      {
        "start": 6231,
        "end": 6231,
        "label": "loc_1857",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 6233,
        "end": 6233,
        "label": "loc_1859",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
        ]
      },
      {
        "start": 6236,
        "end": 6244,
        "label": "loc_185C",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6245,
        "end": 6250,
        "label": "loc_1865",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_1888",
        "targets": [
          6280
        ]
      },
      {
        "start": 6252,
        "end": 6267,
        "label": "loc_186C",
        "instruction_count": 5,
        "cycles_min": 26,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1885",
        "targets": [
          6277
        ]
      },
      {
        "start": 6269,
        "end": 6273,
        "label": "loc_187D",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1885",
        "targets": [
          6277
        ]
      },
      {
        "start": 6275,
        "end": 6275,
        "label": "loc_1883",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 6277,
        "end": 6277,
        "label": "loc_1885",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
        ]
      },
      {
        "start": 6280,
        "end": 6288,
        "label": "loc_1888",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6289,
        "end": 6293,
        "label": "loc_1891",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_18BB",
        "targets": [
          6331
        ]
      },
      {
        "start": 6295,
        "end": 6300,
        "label": "loc_1897",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_18B2",
        "targets": [
          6322
        ]
      },
      {
        "start": 6302,
        "end": 6306,
        "label": "loc_189E",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_18B2",
        "targets": [
          6322
        ]
      },
      {
        "start": 6308,
        "end": 6319,
        "label": "loc_18A4",
        "instruction_count": 4,
        "cycles_min": 31,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
        ]
      },
      {
        "start": 6322,
        "end": 6330,
        "label": "loc_18B2",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6331,
        "end": 6336,
        "label": "loc_18BB",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_18DE",
        "targets": [
          6366
        ]
      },
      {
        "start": 6338,
        "end": 6353,
        "label": "loc_18C2",
        "instruction_count": 5,
        "cycles_min": 26,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_18DB",
        "targets": [
          6363
        ]
      },
      {
        "start": 6355,
        "end": 6359,
        "label": "loc_18D3",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_18DB",
        "targets": [
          6363
        ]
      },
      {
        "start": 6361,
        "end": 6361,
        "label": "loc_18D9",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 6363,
        "end": 6363,
        "label": "loc_18DB",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
        ]
      },
      {
        "start": 6366,
        "end": 6374,
        "label": "loc_18DE",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6375,
        "end": 6379,
        "label": "loc_18E7",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_191F",
        "targets": [
          6431
        ]
      },
      {
        "start": 6381,
        "end": 6386,
        "label": "loc_18ED",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_1916",
        "targets": [
          6422
        ]
      },
      {
        "start": 6388,
        "end": 6392,
        "label": "loc_18F4",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1916",
        "targets": [
          6422
        ]
      },
      {
        "start": 6394,
        "end": 6409,
        "label": "loc_18FA",
        "instruction_count": 5,
        "cycles_min": 26,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1913",
        "targets": [
          6419
        ]
      },
      {
        "start": 6411,
        "end": 6415,
        "label": "loc_190B",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1913",
        "targets": [
          6419
        ]
      },
      {
        "start": 6417,
        "end": 6417,
        "label": "loc_1911",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 6419,
        "end": 6419,
        "label": "loc_1913",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
        ]
      },
      {
        "start": 6422,
        "end": 6430,
        "label": "loc_1916",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6431,
        "end": 6436,
        "label": "loc_191F",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_1941",
        "targets": [
          6465
        ]
      },
      {
        "start": 6438,
        "end": 6453,
        "label": "loc_1926",
        "instruction_count": 5,
        "cycles_min": 26,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_193F",
        "targets": [
          6463
        ]
      },
      {
        "start": 6455,
        "end": 6459,
        "label": "loc_1937",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_193F",
        "targets": [
          6463
        ]
      },
      {
        "start": 6461,
        "end": 6461,
        "label": "loc_193D",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 6463,
        "end": 6463,
        "label": "loc_193F",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19A2",
        "targets": [
          6562
        ]
      },
      {
        "start": 6465,
        "end": 6473,
        "label": "loc_1941",
        "instruction_count": 3,
        "cycles_min": 25,
        "cycles_max": 25,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6474,
        "end": 6479,
        "label": "loc_194A",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BHI loc_1970",
        "targets": [
          6512
        ]
      },
      {
        "start": 6481,
        "end": 6493,
        "label": "loc_1951",
        "instruction_count": 4,
        "cycles_min": 21,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "BNE loc_195F",
        "targets": [
          6495
        ]
      },
      {
        "start": 6495,
        "end": 6502,
        "label": "loc_195F",
        "instruction_count": 3,
        "cycles_min": 13,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_196A",
        "targets": [
          6506
        ]
      },
      {
        "start": 6504,
        "end": 6504,
        "label": "loc_1968",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 6506,
        "end": 6508,
        "label": "loc_196A",
        "instruction_count": 2,
        "cycles_min": 22,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "BSET.B #7, @H'F76D",
        "targets": []
      },
      {
        "start": 6512,
        "end": 6520,
        "label": "loc_1970",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6521,
        "end": 6526,
        "label": "loc_1979",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BHI loc_1999",
        "targets": [
          6553
        ]
      },
      {
        "start": 6528,
        "end": 6547,
        "label": "loc_1980",
        "instruction_count": 6,
        "cycles_min": 52,
        "cycles_max": 57,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1997",
        "targets": [
          6551
        ]
      },
      {
        "start": 6549,
        "end": 6549,
        "label": "loc_1995",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 6551,
        "end": 6551,
        "label": "loc_1997",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_19DB",
        "targets": [
          6619
        ]
      },
      {
        "start": 6553,
        "end": 6561,
        "label": "loc_1999",
        "instruction_count": 3,
        "cycles_min": 25,
        "cycles_max": 25,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6562,
        "end": 6577,
        "label": "loc_19A2",
        "instruction_count": 6,
        "cycles_min": 23,
        "cycles_max": 28,
        "unknown_cycles": 0,
        "terminator": "BHI loc_19B6",
        "targets": [
          6582
        ]
      },
      {
        "start": 6579,
        "end": 6579,
        "label": "loc_19B3",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'FE00, R0",
        "targets": []
      },
      {
        "start": 6582,
        "end": 6589,
        "label": "loc_19B6",
        "instruction_count": 4,
        "cycles_min": 13,
        "cycles_max": 18,
        "unknown_cycles": 0,
        "terminator": "BLS loc_19D3",
        "targets": [
          6611
        ]
      },
      {
        "start": 6591,
        "end": 6594,
        "label": "loc_19BF",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BCC loc_19D3",
        "targets": [
          6611
        ]
      },
      {
        "start": 6596,
        "end": 6599,
        "label": "loc_19C4",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BCC loc_19CE",
        "targets": [
          6606
        ]
      },
      {
        "start": 6601,
        "end": 6604,
        "label": "loc_19C9",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BRA loc_19D7",
        "targets": [
          6615
        ]
      },
      {
        "start": 6606,
        "end": 6609,
        "label": "loc_19CE",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BRA loc_19D7",
        "targets": [
          6615
        ]
      },
      {
        "start": 6611,
        "end": 6611,
        "label": "loc_19D3",
        "instruction_count": 1,
        "cycles_min": 6,
        "cycles_max": 6,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B @(H'1A25,R4), R4",
        "targets": []
      },
      {
        "start": 6615,
        "end": 6617,
        "label": "loc_19D7",
        "instruction_count": 2,
        "cycles_min": 33,
        "cycles_max": 33,
        "unknown_cycles": 0,
        "terminator": "BRA loc_19E3",
        "targets": [
          6627
        ]
      },
      {
        "start": 6619,
        "end": 6625,
        "label": "loc_19DB",
        "instruction_count": 3,
        "cycles_min": 10,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "SHLL.W R3",
        "targets": []
      },
      {
        "start": 6627,
        "end": 6635,
        "label": "loc_19E3",
        "instruction_count": 4,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BCS loc_19F9",
        "targets": [
          6649
        ]
      },
      {
        "start": 6637,
        "end": 6642,
        "label": "loc_19ED",
        "instruction_count": 3,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BLS loc_1A03",
        "targets": [
          6659
        ]
      },
      {
        "start": 6644,
        "end": 6647,
        "label": "loc_19F4",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1A03",
        "targets": [
          6659
        ]
      },
      {
        "start": 6649,
        "end": 6654,
        "label": "loc_19F9",
        "instruction_count": 3,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BLS loc_1A03",
        "targets": [
          6659
        ]
      },
      {
        "start": 6656,
        "end": 6656,
        "label": "loc_1A00",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'FFFF, R1",
        "targets": []
      },
      {
        "start": 6659,
        "end": 6663,
        "label": "loc_1A03",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1A14",
        "targets": [
          6676
        ]
      },
      {
        "start": 6665,
        "end": 6673,
        "label": "loc_1A09",
        "instruction_count": 4,
        "cycles_min": 25,
        "cycles_max": 25,
        "unknown_cycles": 0,
        "terminator": "BSR loc_3E54",
        "targets": [
          15956
        ]
      },
      {
        "start": 6676,
        "end": 6676,
        "label": "loc_1A14",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6709,
        "end": 6721,
        "label": "loc_1A35",
        "instruction_count": 5,
        "cycles_min": 19,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1A7D",
        "targets": [
          6781
        ]
      },
      {
        "start": 6723,
        "end": 6723,
        "label": "loc_1A43",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_1A8D",
        "targets": [
          6797
        ]
      },
      {
        "start": 6725,
        "end": 6727,
        "label": "loc_1A45",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1A59",
        "targets": [
          6745
        ]
      },
      {
        "start": 6729,
        "end": 6729,
        "label": "loc_1A49",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, R2",
        "targets": []
      },
      {
        "start": 6731,
        "end": 6737,
        "label": "loc_1A4B",
        "instruction_count": 3,
        "cycles_min": 12,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1A69",
        "targets": [
          6761
        ]
      },
      {
        "start": 6739,
        "end": 6741,
        "label": "loc_1A53",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1A4B",
        "targets": [
          6731
        ]
      },
      {
        "start": 6743,
        "end": 6743,
        "label": "loc_1A57",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1A6B",
        "targets": [
          6763
        ]
      },
      {
        "start": 6745,
        "end": 6745,
        "label": "loc_1A59",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, R2",
        "targets": []
      },
      {
        "start": 6747,
        "end": 6753,
        "label": "loc_1A5B",
        "instruction_count": 3,
        "cycles_min": 12,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1A69",
        "targets": [
          6761
        ]
      },
      {
        "start": 6755,
        "end": 6757,
        "label": "loc_1A63",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1A5B",
        "targets": [
          6747
        ]
      },
      {
        "start": 6759,
        "end": 6759,
        "label": "loc_1A67",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1A6B",
        "targets": [
          6763
        ]
      },
      {
        "start": 6761,
        "end": 6761,
        "label": "loc_1A69",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R2, R0",
        "targets": []
      },
      {
        "start": 6763,
        "end": 6767,
        "label": "loc_1A6B",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1A7C",
        "targets": [
          6780
        ]
      },
      {
        "start": 6769,
        "end": 6777,
        "label": "loc_1A71",
        "instruction_count": 4,
        "cycles_min": 25,
        "cycles_max": 25,
        "unknown_cycles": 0,
        "terminator": "BSR loc_3E54",
        "targets": [
          15956
        ]
      },
      {
        "start": 6780,
        "end": 6780,
        "label": "loc_1A7C",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6781,
        "end": 6781,
        "label": "loc_1A7D",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #15, R0",
        "targets": []
      },
      {
        "start": 6783,
        "end": 6789,
        "label": "loc_1A7F",
        "instruction_count": 3,
        "cycles_min": 12,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1A8B",
        "targets": [
          6795
        ]
      },
      {
        "start": 6791,
        "end": 6793,
        "label": "loc_1A87",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1A7F",
        "targets": [
          6783
        ]
      },
      {
        "start": 6795,
        "end": 6795,
        "label": "loc_1A8B",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1A45",
        "targets": [
          6725
        ]
      },
      {
        "start": 6797,
        "end": 6797,
        "label": "loc_1A8D",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'000F, R1",
        "targets": []
      },
      {
        "start": 6800,
        "end": 6802,
        "label": "loc_1A90",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1A97",
        "targets": [
          6807
        ]
      },
      {
        "start": 6804,
        "end": 6804,
        "label": "loc_1A94",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "SCB/F R1, loc_1A90",
        "targets": [
          6800
        ]
      },
      {
        "start": 6807,
        "end": 6811,
        "label": "loc_1A97",
        "instruction_count": 3,
        "cycles_min": 19,
        "cycles_max": 19,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6812,
        "end": 6814,
        "label": "loc_1A9C",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1AD2",
        "targets": [
          6866
        ]
      },
      {
        "start": 6816,
        "end": 6829,
        "label": "loc_1AA0",
        "instruction_count": 6,
        "cycles_min": 21,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1ABC",
        "targets": [
          6844
        ]
      },
      {
        "start": 6831,
        "end": 6840,
        "label": "loc_1AAF",
        "instruction_count": 4,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1AAF",
        "targets": [
          6831
        ]
      },
      {
        "start": 6842,
        "end": 6842,
        "label": "loc_1ABA",
        "instruction_count": 1,
        "cycles_min": 7,
        "cycles_max": 7,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1AC7",
        "targets": [
          6855
        ]
      },
      {
        "start": 6844,
        "end": 6853,
        "label": "loc_1ABC",
        "instruction_count": 4,
        "cycles_min": 16,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1ABC",
        "targets": [
          6844
        ]
      },
      {
        "start": 6855,
        "end": 6864,
        "label": "loc_1AC7",
        "instruction_count": 4,
        "cycles_min": 19,
        "cycles_max": 19,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1AE0",
        "targets": [
          6880
        ]
      },
      {
        "start": 6866,
        "end": 6868,
        "label": "loc_1AD2",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1ADC",
        "targets": [
          6876
        ]
      },
      {
        "start": 6870,
        "end": 6874,
        "label": "loc_1AD6",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1AE0",
        "targets": [
          6880
        ]
      },
      {
        "start": 6876,
        "end": 6876,
        "label": "loc_1ADC",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "ADD:Q.B #-1, @H'F733",
        "targets": []
      },
      {
        "start": 6880,
        "end": 6883,
        "label": "loc_1AE0",
        "instruction_count": 2,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6884,
        "end": 6896,
        "label": "loc_1AE4",
        "instruction_count": 5,
        "cycles_min": 23,
        "cycles_max": 27,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1AFC",
        "targets": [
          6908
        ]
      },
      {
        "start": 6898,
        "end": 6902,
        "label": "loc_1AF2",
        "instruction_count": 3,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BLS loc_1B03",
        "targets": [
          6915
        ]
      },
      {
        "start": 6904,
        "end": 6906,
        "label": "loc_1AF8",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1B03",
        "targets": [
          6915
        ]
      },
      {
        "start": 6908,
        "end": 6911,
        "label": "loc_1AFC",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BCC loc_1B03",
        "targets": [
          6915
        ]
      },
      {
        "start": 6913,
        "end": 6913,
        "label": "loc_1B01",
        "instruction_count": 1,
        "cycles_min": 2,
        "cycles_max": 2,
        "unknown_cycles": 0,
        "terminator": "MOV:E.B #H'2E, R1",
        "targets": []
      },
      {
        "start": 6915,
        "end": 6922,
        "label": "loc_1B03",
        "instruction_count": 3,
        "cycles_min": 32,
        "cycles_max": 32,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6923,
        "end": 6929,
        "label": "loc_1B0B",
        "instruction_count": 3,
        "cycles_min": 12,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "BNE loc_1B1D",
        "targets": [
          6941
        ]
      },
      {
        "start": 6931,
        "end": 6935,
        "label": "loc_1B13",
        "instruction_count": 3,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BLS loc_1B25",
        "targets": [
          6949
        ]
      },
      {
        "start": 6937,
        "end": 6939,
        "label": "loc_1B19",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1B25",
        "targets": [
          6949
        ]
      },
      {
        "start": 6941,
        "end": 6945,
        "label": "loc_1B1D",
        "instruction_count": 3,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BCC loc_1B25",
        "targets": [
          6949
        ]
      },
      {
        "start": 6947,
        "end": 6947,
        "label": "loc_1B23",
        "instruction_count": 1,
        "cycles_min": 2,
        "cycles_max": 2,
        "unknown_cycles": 0,
        "terminator": "MOV:E.B #H'01, R0",
        "targets": []
      },
      {
        "start": 6949,
        "end": 6956,
        "label": "loc_1B25",
        "instruction_count": 3,
        "cycles_min": 32,
        "cycles_max": 32,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6957,
        "end": 6979,
        "label": "loc_1B2D",
        "instruction_count": 7,
        "cycles_min": 53,
        "cycles_max": 53,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 6980,
        "end": 7002,
        "label": "loc_1B44",
        "instruction_count": 7,
        "cycles_min": 57,
        "cycles_max": 57,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 7003,
        "end": 7025,
        "label": "loc_1B5B",
        "instruction_count": 7,
        "cycles_min": 53,
        "cycles_max": 53,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 7026,
        "end": 7048,
        "label": "loc_1B72",
        "instruction_count": 7,
        "cycles_min": 57,
        "cycles_max": 57,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 7049,
        "end": 7071,
        "label": "loc_1B89",
        "instruction_count": 7,
        "cycles_min": 53,
        "cycles_max": 53,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 7072,
        "end": 7093,
        "label": "loc_1BA0",
        "instruction_count": 7,
        "cycles_min": 56,
        "cycles_max": 56,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 7094,
        "end": 7115,
        "label": "loc_1BB6",
        "instruction_count": 7,
        "cycles_min": 56,
        "cycles_max": 56,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 7116,
        "end": 7137,
        "label": "loc_1BCC",
        "instruction_count": 7,
        "cycles_min": 56,
        "cycles_max": 56,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 7138,
        "end": 7159,
        "label": "loc_1BE2",
        "instruction_count": 7,
        "cycles_min": 56,
        "cycles_max": 56,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 7160,
        "end": 7181,
        "label": "loc_1BF8",
        "instruction_count": 7,
        "cycles_min": 56,
        "cycles_max": 56,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 7182,
        "end": 7184,
        "label": "loc_1C0E",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BCC loc_1C1C",
        "targets": [
          7196
        ]
      },
      {
        "start": 7186,
        "end": 7194,
        "label": "loc_1C12",
        "instruction_count": 4,
        "cycles_min": 46,
        "cycles_max": 46,
        "unknown_cycles": 0,
        "terminator": "LDM.W @SP+, {R4,R5}",
        "targets": []
      },
      {
        "start": 7196,
        "end": 7198,
        "label": "loc_1C1C",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_1C24",
        "targets": [
          7204
        ]
      },
      {
        "start": 7200,
        "end": 7202,
        "label": "loc_1C20",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BRA loc_1C0E",
        "targets": [
          7182
        ]
      },
      {
        "start": 7204,
        "end": 7204,
        "label": "loc_1C24",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 8487,
        "end": 8491,
        "label": "loc_2127",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BNE loc_2135",
        "targets": [
          8501
        ]
      },
      {
        "start": 8493,
        "end": 8497,
        "label": "loc_212D",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R1, @H'F734",
        "targets": []
      },
      {
        "start": 8501,
        "end": 8515,
        "label": "loc_2135",
        "instruction_count": 4,
        "cycles_min": 44,
        "cycles_max": 44,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 9808,
        "end": 9812,
        "label": "loc_2650",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_26BF",
        "targets": [
          9919
        ]
      },
      {
        "start": 9815,
        "end": 9827,
        "label": "loc_2657",
        "instruction_count": 5,
        "cycles_min": 21,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "BNE loc_266D",
        "targets": [
          9837
        ]
      },
      {
        "start": 9829,
        "end": 9831,
        "label": "loc_2665",
        "instruction_count": 2,
        "cycles_min": 7,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "BCC loc_2683",
        "targets": [
          9859
        ]
      },
      {
        "start": 9833,
        "end": 9835,
        "label": "loc_2669",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BRA loc_2683",
        "targets": [
          9859
        ]
      },
      {
        "start": 9837,
        "end": 9843,
        "label": "loc_266D",
        "instruction_count": 3,
        "cycles_min": 13,
        "cycles_max": 18,
        "unknown_cycles": 0,
        "terminator": "BNE loc_267D",
        "targets": [
          9853
        ]
      },
      {
        "start": 9845,
        "end": 9847,
        "label": "loc_2675",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BCC loc_2683",
        "targets": [
          9859
        ]
      },
      {
        "start": 9849,
        "end": 9851,
        "label": "loc_2679",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BRA loc_2683",
        "targets": [
          9859
        ]
      },
      {
        "start": 9853,
        "end": 9855,
        "label": "loc_267D",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BCC loc_2683",
        "targets": [
          9859
        ]
      },
      {
        "start": 9857,
        "end": 9857,
        "label": "loc_2681",
        "instruction_count": 1,
        "cycles_min": 2,
        "cycles_max": 2,
        "unknown_cycles": 0,
        "terminator": "MOV:E.B #H'16, R0",
        "targets": []
      },
      {
        "start": 9859,
        "end": 9871,
        "label": "loc_2683",
        "instruction_count": 6,
        "cycles_min": 21,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_26BF",
        "targets": [
          9919
        ]
      },
      {
        "start": 9873,
        "end": 9886,
        "label": "loc_2691",
        "instruction_count": 5,
        "cycles_min": 21,
        "cycles_max": 25,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_26A8",
        "targets": [
          9896
        ]
      },
      {
        "start": 9888,
        "end": 9892,
        "label": "loc_26A0",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_26A8",
        "targets": [
          9896
        ]
      },
      {
        "start": 9894,
        "end": 9894,
        "label": "loc_26A6",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "BSET.W #14, R3",
        "targets": []
      },
      {
        "start": 9896,
        "end": 9903,
        "label": "loc_26A8",
        "instruction_count": 3,
        "cycles_min": 24,
        "cycles_max": 29,
        "unknown_cycles": 0,
        "terminator": "BNE loc_26B9",
        "targets": [
          9913
        ]
      },
      {
        "start": 9905,
        "end": 9911,
        "label": "loc_26B1",
        "instruction_count": 2,
        "cycles_min": 17,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "BRA loc_26BF",
        "targets": [
          9919
        ]
      },
      {
        "start": 9913,
        "end": 9913,
        "label": "loc_26B9",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W #H'00C8, @H'F6F4",
        "targets": []
      },
      {
        "start": 9919,
        "end": 9919,
        "label": "loc_26BF",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 10246,
        "end": 10256,
        "label": "loc_2806",
        "instruction_count": 4,
        "cycles_min": 20,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BNE loc_2815",
        "targets": [
          10261
        ]
      },
      {
        "start": 10258,
        "end": 10258,
        "label": "loc_2812",
        "instruction_count": 1,
        "cycles_min": 7,
        "cycles_max": 7,
        "unknown_cycles": 0,
        "terminator": "BRA loc_2CA6",
        "targets": [
          11430
        ]
      },
      {
        "start": 10261,
        "end": 10293,
        "label": "loc_2815",
        "instruction_count": 13,
        "cycles_min": 58,
        "cycles_max": 63,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_289F",
        "targets": [
          10399
        ]
      },
      {
        "start": 10295,
        "end": 10305,
        "label": "loc_2837",
        "instruction_count": 4,
        "cycles_min": 16,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_2CAB",
        "targets": [
          11435
        ]
      },
      {
        "start": 10308,
        "end": 10318,
        "label": "loc_2844",
        "instruction_count": 4,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_2CAB",
        "targets": [
          11435
        ]
      },
      {
        "start": 10321,
        "end": 10331,
        "label": "loc_2851",
        "instruction_count": 4,
        "cycles_min": 16,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_2CAB",
        "targets": [
          11435
        ]
      },
      {
        "start": 10334,
        "end": 10344,
        "label": "loc_285E",
        "instruction_count": 4,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_2CAB",
        "targets": [
          11435
        ]
      },
      {
        "start": 10347,
        "end": 10357,
        "label": "loc_286B",
        "instruction_count": 4,
        "cycles_min": 16,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_2CAB",
        "targets": [
          11435
        ]
      },
      {
        "start": 10360,
        "end": 10370,
        "label": "loc_2878",
        "instruction_count": 4,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_2CAB",
        "targets": [
          11435
        ]
      },
      {
        "start": 10373,
        "end": 10383,
        "label": "loc_2885",
        "instruction_count": 4,
        "cycles_min": 16,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_2CAB",
        "targets": [
          11435
        ]
      },
      {
        "start": 10386,
        "end": 10396,
        "label": "loc_2892",
        "instruction_count": 4,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_2CAB",
        "targets": [
          11435
        ]
      },
      {
        "start": 10399,
        "end": 10403,
        "label": "loc_289F",
        "instruction_count": 2,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "JMP @R1",
        "targets": []
      },
      {
        "start": 11430,
        "end": 11434,
        "label": "loc_2CA6",
        "instruction_count": 2,
        "cycles_min": 21,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 11435,
        "end": 11446,
        "label": "loc_2CAB",
        "instruction_count": 5,
        "cycles_min": 63,
        "cycles_max": 63,
        "unknown_cycles": 0,
        "terminator": "BRA loc_289F",
        "targets": [
          10399
        ]
      },
      {
        "start": 14640,
        "end": 14640,
        "label": "loc_3930",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'0007, R0",
        "targets": []
      },
      {
        "start": 14643,
        "end": 14647,
        "label": "loc_3933",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3943",
        "targets": [
          14659
        ]
      },
      {
        "start": 14649,
        "end": 14657,
        "label": "loc_3939",
        "instruction_count": 3,
        "cycles_min": 24,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3947",
        "targets": [
          14663
        ]
      },
      {
        "start": 14659,
        "end": 14659,
        "label": "loc_3943",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "SHLL.B @(-H'0980,R0)",
        "targets": []
      },
      {
        "start": 14663,
        "end": 14668,
        "label": "loc_3947",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3954",
        "targets": [
          14676
        ]
      },
      {
        "start": 14670,
        "end": 14674,
        "label": "loc_394E",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_395F",
        "targets": [
          14687
        ]
      },
      {
        "start": 14676,
        "end": 14681,
        "label": "loc_3954",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BNE loc_395F",
        "targets": [
          14687
        ]
      },
      {
        "start": 14683,
        "end": 14683,
        "label": "loc_395B",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BCLR.B R0, @H'F688",
        "targets": []
      },
      {
        "start": 14687,
        "end": 14687,
        "label": "loc_395F",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "SCB/F R0, loc_3933",
        "targets": [
          14643
        ]
      },
      {
        "start": 14690,
        "end": 14699,
        "label": "loc_3962",
        "instruction_count": 3,
        "cycles_min": 19,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_397C",
        "targets": [
          14716
        ]
      },
      {
        "start": 14701,
        "end": 14706,
        "label": "loc_396D",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_397F",
        "targets": [
          14719
        ]
      },
      {
        "start": 14708,
        "end": 14713,
        "label": "loc_3974",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3983",
        "targets": [
          14723
        ]
      },
      {
        "start": 14715,
        "end": 14715,
        "label": "loc_397B",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 14716,
        "end": 14718,
        "label": "loc_397C",
        "instruction_count": 2,
        "cycles_min": 25,
        "cycles_max": 25,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 14719,
        "end": 14722,
        "label": "loc_397F",
        "instruction_count": 2,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 14723,
        "end": 14729,
        "label": "loc_3983",
        "instruction_count": 3,
        "cycles_min": 35,
        "cycles_max": 35,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 14730,
        "end": 14734,
        "label": "loc_398A",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3994",
        "targets": [
          14740
        ]
      },
      {
        "start": 14736,
        "end": 14736,
        "label": "loc_3990",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BSET.B #5, @ADCSR",
        "targets": []
      },
      {
        "start": 14740,
        "end": 14740,
        "label": "loc_3994",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 14741,
        "end": 14745,
        "label": "loc_3995",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3A2D",
        "targets": [
          14893
        ]
      },
      {
        "start": 14748,
        "end": 14757,
        "label": "loc_399C",
        "instruction_count": 3,
        "cycles_min": 18,
        "cycles_max": 23,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3A2D",
        "targets": [
          14893
        ]
      },
      {
        "start": 14760,
        "end": 14888,
        "label": "loc_39A8",
        "instruction_count": 34,
        "cycles_min": 227,
        "cycles_max": 227,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B #H'03, @H'F720",
        "targets": []
      },
      {
        "start": 14893,
        "end": 14893,
        "label": "loc_3A2D",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 14894,
        "end": 14898,
        "label": "loc_3A2E",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3AC6",
        "targets": [
          15046
        ]
      },
      {
        "start": 14901,
        "end": 14910,
        "label": "loc_3A35",
        "instruction_count": 3,
        "cycles_min": 19,
        "cycles_max": 23,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3AC6",
        "targets": [
          15046
        ]
      },
      {
        "start": 14913,
        "end": 15041,
        "label": "loc_3A41",
        "instruction_count": 34,
        "cycles_min": 197,
        "cycles_max": 197,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B #H'03, @H'F721",
        "targets": []
      },
      {
        "start": 15046,
        "end": 15046,
        "label": "loc_3AC6",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 15047,
        "end": 15053,
        "label": "vec_irq4_3AC7",
        "instruction_count": 3,
        "cycles_min": 14,
        "cycles_max": 19,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3C2D",
        "targets": [
          15405
        ]
      },
      {
        "start": 15056,
        "end": 15062,
        "label": "loc_3AD0",
        "instruction_count": 3,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3AE0",
        "targets": [
          15072
        ]
      },
      {
        "start": 15064,
        "end": 15066,
        "label": "loc_3AD8",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3B62",
        "targets": [
          15202
        ]
      },
      {
        "start": 15069,
        "end": 15069,
        "label": "loc_3ADD",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3C2D",
        "targets": [
          15405
        ]
      },
      {
        "start": 15072,
        "end": 15091,
        "label": "loc_3AE0",
        "instruction_count": 6,
        "cycles_min": 31,
        "cycles_max": 36,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3AFD",
        "targets": [
          15101
        ]
      },
      {
        "start": 15093,
        "end": 15097,
        "label": "loc_3AF5",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F69A",
        "targets": []
      },
      {
        "start": 15101,
        "end": 15109,
        "label": "loc_3AFD",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3B0F",
        "targets": [
          15119
        ]
      },
      {
        "start": 15111,
        "end": 15115,
        "label": "loc_3B07",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F698",
        "targets": []
      },
      {
        "start": 15119,
        "end": 15127,
        "label": "loc_3B0F",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3B21",
        "targets": [
          15137
        ]
      },
      {
        "start": 15129,
        "end": 15133,
        "label": "loc_3B19",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F696",
        "targets": []
      },
      {
        "start": 15137,
        "end": 15145,
        "label": "loc_3B21",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3B33",
        "targets": [
          15155
        ]
      },
      {
        "start": 15147,
        "end": 15151,
        "label": "loc_3B2B",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F694",
        "targets": []
      },
      {
        "start": 15155,
        "end": 15163,
        "label": "loc_3B33",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3B45",
        "targets": [
          15173
        ]
      },
      {
        "start": 15165,
        "end": 15169,
        "label": "loc_3B3D",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F692",
        "targets": []
      },
      {
        "start": 15173,
        "end": 15181,
        "label": "loc_3B45",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3B57",
        "targets": [
          15191
        ]
      },
      {
        "start": 15183,
        "end": 15187,
        "label": "loc_3B4F",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F690",
        "targets": []
      },
      {
        "start": 15191,
        "end": 15199,
        "label": "loc_3B57",
        "instruction_count": 3,
        "cycles_min": 22,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3C2D",
        "targets": [
          15405
        ]
      },
      {
        "start": 15202,
        "end": 15225,
        "label": "loc_3B62",
        "instruction_count": 7,
        "cycles_min": 39,
        "cycles_max": 44,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3B83",
        "targets": [
          15235
        ]
      },
      {
        "start": 15227,
        "end": 15231,
        "label": "loc_3B7B",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F69E",
        "targets": []
      },
      {
        "start": 15235,
        "end": 15243,
        "label": "loc_3B83",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3B95",
        "targets": [
          15253
        ]
      },
      {
        "start": 15245,
        "end": 15249,
        "label": "loc_3B8D",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F69C",
        "targets": []
      },
      {
        "start": 15253,
        "end": 15261,
        "label": "loc_3B95",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3BA7",
        "targets": [
          15271
        ]
      },
      {
        "start": 15263,
        "end": 15267,
        "label": "loc_3B9F",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D0",
        "targets": []
      },
      {
        "start": 15271,
        "end": 15279,
        "label": "loc_3BA7",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3BB9",
        "targets": [
          15289
        ]
      },
      {
        "start": 15281,
        "end": 15285,
        "label": "loc_3BB1",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D1",
        "targets": []
      },
      {
        "start": 15289,
        "end": 15297,
        "label": "loc_3BB9",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3BCB",
        "targets": [
          15307
        ]
      },
      {
        "start": 15299,
        "end": 15303,
        "label": "loc_3BC3",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D2",
        "targets": []
      },
      {
        "start": 15307,
        "end": 15315,
        "label": "loc_3BCB",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3BDD",
        "targets": [
          15325
        ]
      },
      {
        "start": 15317,
        "end": 15321,
        "label": "loc_3BD5",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D3",
        "targets": []
      },
      {
        "start": 15325,
        "end": 15333,
        "label": "loc_3BDD",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3BEF",
        "targets": [
          15343
        ]
      },
      {
        "start": 15335,
        "end": 15339,
        "label": "loc_3BE7",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D4",
        "targets": []
      },
      {
        "start": 15343,
        "end": 15351,
        "label": "loc_3BEF",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3C01",
        "targets": [
          15361
        ]
      },
      {
        "start": 15353,
        "end": 15357,
        "label": "loc_3BF9",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D5",
        "targets": []
      },
      {
        "start": 15361,
        "end": 15369,
        "label": "loc_3C01",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3C13",
        "targets": [
          15379
        ]
      },
      {
        "start": 15371,
        "end": 15375,
        "label": "loc_3C0B",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D6",
        "targets": []
      },
      {
        "start": 15379,
        "end": 15387,
        "label": "loc_3C13",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3C25",
        "targets": [
          15397
        ]
      },
      {
        "start": 15389,
        "end": 15393,
        "label": "loc_3C1D",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D7",
        "targets": []
      },
      {
        "start": 15397,
        "end": 15401,
        "label": "loc_3C25",
        "instruction_count": 2,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #1, @H'F720",
        "targets": []
      },
      {
        "start": 15405,
        "end": 15407,
        "label": "loc_3C2D",
        "instruction_count": 2,
        "cycles_min": 20,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "RTE",
        "targets": []
      },
      {
        "start": 15408,
        "end": 15414,
        "label": "vec_irq3_3C30",
        "instruction_count": 3,
        "cycles_min": 16,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3D96",
        "targets": [
          15766
        ]
      },
      {
        "start": 15417,
        "end": 15423,
        "label": "loc_3C39",
        "instruction_count": 3,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3C49",
        "targets": [
          15433
        ]
      },
      {
        "start": 15425,
        "end": 15427,
        "label": "loc_3C41",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3CCB",
        "targets": [
          15563
        ]
      },
      {
        "start": 15430,
        "end": 15430,
        "label": "loc_3C46",
        "instruction_count": 1,
        "cycles_min": 7,
        "cycles_max": 7,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3D96",
        "targets": [
          15766
        ]
      },
      {
        "start": 15433,
        "end": 15452,
        "label": "loc_3C49",
        "instruction_count": 6,
        "cycles_min": 33,
        "cycles_max": 37,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3C66",
        "targets": [
          15462
        ]
      },
      {
        "start": 15454,
        "end": 15458,
        "label": "loc_3C5E",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F6AA",
        "targets": []
      },
      {
        "start": 15462,
        "end": 15470,
        "label": "loc_3C66",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3C78",
        "targets": [
          15480
        ]
      },
      {
        "start": 15472,
        "end": 15476,
        "label": "loc_3C70",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F6A8",
        "targets": []
      },
      {
        "start": 15480,
        "end": 15488,
        "label": "loc_3C78",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3C8A",
        "targets": [
          15498
        ]
      },
      {
        "start": 15490,
        "end": 15494,
        "label": "loc_3C82",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F6A6",
        "targets": []
      },
      {
        "start": 15498,
        "end": 15506,
        "label": "loc_3C8A",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3C9C",
        "targets": [
          15516
        ]
      },
      {
        "start": 15508,
        "end": 15512,
        "label": "loc_3C94",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F6A4",
        "targets": []
      },
      {
        "start": 15516,
        "end": 15524,
        "label": "loc_3C9C",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3CAE",
        "targets": [
          15534
        ]
      },
      {
        "start": 15526,
        "end": 15530,
        "label": "loc_3CA6",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F6A2",
        "targets": []
      },
      {
        "start": 15534,
        "end": 15542,
        "label": "loc_3CAE",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3CC0",
        "targets": [
          15552
        ]
      },
      {
        "start": 15544,
        "end": 15548,
        "label": "loc_3CB8",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F6A0",
        "targets": []
      },
      {
        "start": 15552,
        "end": 15560,
        "label": "loc_3CC0",
        "instruction_count": 3,
        "cycles_min": 23,
        "cycles_max": 23,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3D96",
        "targets": [
          15766
        ]
      },
      {
        "start": 15563,
        "end": 15586,
        "label": "loc_3CCB",
        "instruction_count": 7,
        "cycles_min": 42,
        "cycles_max": 46,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3CEC",
        "targets": [
          15596
        ]
      },
      {
        "start": 15588,
        "end": 15592,
        "label": "loc_3CE4",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F6AE",
        "targets": []
      },
      {
        "start": 15596,
        "end": 15604,
        "label": "loc_3CEC",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3CFE",
        "targets": [
          15614
        ]
      },
      {
        "start": 15606,
        "end": 15610,
        "label": "loc_3CF6",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F6AC",
        "targets": []
      },
      {
        "start": 15614,
        "end": 15622,
        "label": "loc_3CFE",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3D10",
        "targets": [
          15632
        ]
      },
      {
        "start": 15624,
        "end": 15628,
        "label": "loc_3D08",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D8",
        "targets": []
      },
      {
        "start": 15632,
        "end": 15640,
        "label": "loc_3D10",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3D22",
        "targets": [
          15650
        ]
      },
      {
        "start": 15642,
        "end": 15646,
        "label": "loc_3D1A",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6D9",
        "targets": []
      },
      {
        "start": 15650,
        "end": 15658,
        "label": "loc_3D22",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3D34",
        "targets": [
          15668
        ]
      },
      {
        "start": 15660,
        "end": 15664,
        "label": "loc_3D2C",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6DA",
        "targets": []
      },
      {
        "start": 15668,
        "end": 15676,
        "label": "loc_3D34",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3D46",
        "targets": [
          15686
        ]
      },
      {
        "start": 15678,
        "end": 15682,
        "label": "loc_3D3E",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6DB",
        "targets": []
      },
      {
        "start": 15686,
        "end": 15694,
        "label": "loc_3D46",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3D58",
        "targets": [
          15704
        ]
      },
      {
        "start": 15696,
        "end": 15700,
        "label": "loc_3D50",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6DC",
        "targets": []
      },
      {
        "start": 15704,
        "end": 15712,
        "label": "loc_3D58",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3D6A",
        "targets": [
          15722
        ]
      },
      {
        "start": 15714,
        "end": 15718,
        "label": "loc_3D62",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6DD",
        "targets": []
      },
      {
        "start": 15722,
        "end": 15730,
        "label": "loc_3D6A",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3D7C",
        "targets": [
          15740
        ]
      },
      {
        "start": 15732,
        "end": 15736,
        "label": "loc_3D74",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6DE",
        "targets": []
      },
      {
        "start": 15740,
        "end": 15748,
        "label": "loc_3D7C",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3D8E",
        "targets": [
          15758
        ]
      },
      {
        "start": 15750,
        "end": 15754,
        "label": "loc_3D86",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F6DF",
        "targets": []
      },
      {
        "start": 15758,
        "end": 15762,
        "label": "loc_3D8E",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #1, @H'F721",
        "targets": []
      },
      {
        "start": 15766,
        "end": 15768,
        "label": "loc_3D96",
        "instruction_count": 2,
        "cycles_min": 18,
        "cycles_max": 18,
        "unknown_cycles": 0,
        "terminator": "RTE",
        "targets": []
      },
      {
        "start": 15769,
        "end": 15803,
        "label": "vec_ad_adi_3D99",
        "instruction_count": 12,
        "cycles_min": 112,
        "cycles_max": 117,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3E08",
        "targets": [
          15880
        ]
      },
      {
        "start": 15805,
        "end": 15818,
        "label": "loc_3DBD",
        "instruction_count": 4,
        "cycles_min": 21,
        "cycles_max": 25,
        "unknown_cycles": 0,
        "terminator": "BHI loc_3E08",
        "targets": [
          15880
        ]
      },
      {
        "start": 15820,
        "end": 15842,
        "label": "loc_3DCC",
        "instruction_count": 9,
        "cycles_min": 75,
        "cycles_max": 79,
        "unknown_cycles": 0,
        "terminator": "BCS loc_3DF0",
        "targets": [
          15856
        ]
      },
      {
        "start": 15844,
        "end": 15849,
        "label": "loc_3DE4",
        "instruction_count": 3,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BLS loc_3DFA",
        "targets": [
          15866
        ]
      },
      {
        "start": 15851,
        "end": 15854,
        "label": "loc_3DEB",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3DFA",
        "targets": [
          15866
        ]
      },
      {
        "start": 15856,
        "end": 15861,
        "label": "loc_3DF0",
        "instruction_count": 3,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BLS loc_3DFA",
        "targets": [
          15866
        ]
      },
      {
        "start": 15863,
        "end": 15863,
        "label": "loc_3DF7",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'FFFF, R1",
        "targets": []
      },
      {
        "start": 15866,
        "end": 15870,
        "label": "loc_3DFA",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3E08",
        "targets": [
          15880
        ]
      },
      {
        "start": 15872,
        "end": 15876,
        "label": "loc_3E00",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BSET.B #7, @H'F689",
        "targets": []
      },
      {
        "start": 15880,
        "end": 15904,
        "label": "loc_3E08",
        "instruction_count": 9,
        "cycles_min": 74,
        "cycles_max": 78,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3E28",
        "targets": [
          15912
        ]
      },
      {
        "start": 15906,
        "end": 15910,
        "label": "loc_3E22",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3E4D",
        "targets": [
          15949
        ]
      },
      {
        "start": 15912,
        "end": 15941,
        "label": "loc_3E28",
        "instruction_count": 11,
        "cycles_min": 98,
        "cycles_max": 103,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3E49",
        "targets": [
          15945
        ]
      },
      {
        "start": 15943,
        "end": 15943,
        "label": "loc_3E47",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "SHLR.W R0",
        "targets": []
      },
      {
        "start": 15945,
        "end": 15945,
        "label": "loc_3E49",
        "instruction_count": 1,
        "cycles_min": 6,
        "cycles_max": 6,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @H'F68C",
        "targets": []
      },
      {
        "start": 15949,
        "end": 15955,
        "label": "loc_3E4D",
        "instruction_count": 3,
        "cycles_min": 52,
        "cycles_max": 52,
        "unknown_cycles": 0,
        "terminator": "RTE",
        "targets": []
      },
      {
        "start": 15956,
        "end": 15958,
        "label": "loc_3E54",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3E9A",
        "targets": [
          16026
        ]
      },
      {
        "start": 15960,
        "end": 15974,
        "label": "loc_3E58",
        "instruction_count": 6,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "SHLL.W R1",
        "targets": []
      },
      {
        "start": 15976,
        "end": 15978,
        "label": "loc_3E68",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3E76",
        "targets": [
          15990
        ]
      },
      {
        "start": 15980,
        "end": 15984,
        "label": "loc_3E6C",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3E9A",
        "targets": [
          16026
        ]
      },
      {
        "start": 15986,
        "end": 15988,
        "label": "loc_3E72",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3E68",
        "targets": [
          15976
        ]
      },
      {
        "start": 15990,
        "end": 15998,
        "label": "loc_3E76",
        "instruction_count": 3,
        "cycles_min": 25,
        "cycles_max": 25,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #7, @H'F9B0",
        "targets": []
      },
      {
        "start": 16002,
        "end": 16015,
        "label": "loc_3E82",
        "instruction_count": 5,
        "cycles_min": 23,
        "cycles_max": 28,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3E9A",
        "targets": [
          16026
        ]
      },
      {
        "start": 16017,
        "end": 16024,
        "label": "loc_3E91",
        "instruction_count": 4,
        "cycles_min": 47,
        "cycles_max": 47,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3E82",
        "targets": [
          16002
        ]
      },
      {
        "start": 16026,
        "end": 16028,
        "label": "loc_3E9A",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3ECB",
        "targets": [
          16075
        ]
      },
      {
        "start": 16030,
        "end": 16044,
        "label": "loc_3E9E",
        "instruction_count": 6,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "SHLL.W R1",
        "targets": []
      },
      {
        "start": 16046,
        "end": 16048,
        "label": "loc_3EAE",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3EBF",
        "targets": [
          16063
        ]
      },
      {
        "start": 16050,
        "end": 16054,
        "label": "loc_3EB2",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3ECB",
        "targets": [
          16075
        ]
      },
      {
        "start": 16056,
        "end": 16061,
        "label": "loc_3EB8",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3EAE",
        "targets": [
          16046
        ]
      },
      {
        "start": 16063,
        "end": 16071,
        "label": "loc_3EBF",
        "instruction_count": 3,
        "cycles_min": 22,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #5, @H'F9B4",
        "targets": []
      },
      {
        "start": 16075,
        "end": 16075,
        "label": "loc_3ECB",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16076,
        "end": 16082,
        "label": "loc_3ECC",
        "instruction_count": 4,
        "cycles_min": 29,
        "cycles_max": 33,
        "unknown_cycles": 0,
        "terminator": "BLS loc_3ED9",
        "targets": [
          16089
        ]
      },
      {
        "start": 16084,
        "end": 16087,
        "label": "loc_3ED4",
        "instruction_count": 2,
        "cycles_min": 21,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3F25",
        "targets": [
          16165
        ]
      },
      {
        "start": 16089,
        "end": 16093,
        "label": "loc_3ED9",
        "instruction_count": 3,
        "cycles_min": 7,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3EE9",
        "targets": [
          16105
        ]
      },
      {
        "start": 16095,
        "end": 16097,
        "label": "loc_3EDF",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3EEE",
        "targets": [
          16110
        ]
      },
      {
        "start": 16099,
        "end": 16101,
        "label": "loc_3EE3",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3EF3",
        "targets": [
          16115
        ]
      },
      {
        "start": 16103,
        "end": 16103,
        "label": "loc_3EE7",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3EF8",
        "targets": [
          16120
        ]
      },
      {
        "start": 16105,
        "end": 16108,
        "label": "loc_3EE9",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3EFB",
        "targets": [
          16123
        ]
      },
      {
        "start": 16110,
        "end": 16113,
        "label": "loc_3EEE",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3EFB",
        "targets": [
          16123
        ]
      },
      {
        "start": 16115,
        "end": 16118,
        "label": "loc_3EF3",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3EFB",
        "targets": [
          16123
        ]
      },
      {
        "start": 16120,
        "end": 16120,
        "label": "loc_3EF8",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'00D0, R5",
        "targets": []
      },
      {
        "start": 16123,
        "end": 16130,
        "label": "loc_3EFB",
        "instruction_count": 3,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "CLR.W R1",
        "targets": []
      },
      {
        "start": 16132,
        "end": 16138,
        "label": "loc_3F04",
        "instruction_count": 3,
        "cycles_min": 16,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3F10",
        "targets": [
          16144
        ]
      },
      {
        "start": 16140,
        "end": 16142,
        "label": "loc_3F0C",
        "instruction_count": 2,
        "cycles_min": 19,
        "cycles_max": 19,
        "unknown_cycles": 0,
        "terminator": "BSR loc_3F28",
        "targets": [
          16168
        ]
      },
      {
        "start": 16144,
        "end": 16150,
        "label": "loc_3F10",
        "instruction_count": 4,
        "cycles_min": 13,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3F1A",
        "targets": [
          16154
        ]
      },
      {
        "start": 16152,
        "end": 16152,
        "label": "loc_3F18",
        "instruction_count": 1,
        "cycles_min": 7,
        "cycles_max": 7,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3F04",
        "targets": [
          16132
        ]
      },
      {
        "start": 16154,
        "end": 16163,
        "label": "loc_3F1A",
        "instruction_count": 3,
        "cycles_min": 28,
        "cycles_max": 28,
        "unknown_cycles": 0,
        "terminator": "BSR loc_3F40",
        "targets": [
          16192
        ]
      },
      {
        "start": 16165,
        "end": 16167,
        "label": "loc_3F25",
        "instruction_count": 2,
        "cycles_min": 39,
        "cycles_max": 39,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16168,
        "end": 16176,
        "label": "loc_3F28",
        "instruction_count": 4,
        "cycles_min": 15,
        "cycles_max": 19,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3F38",
        "targets": [
          16184
        ]
      },
      {
        "start": 16178,
        "end": 16182,
        "label": "loc_3F32",
        "instruction_count": 2,
        "cycles_min": 20,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BSR loc_3F40",
        "targets": [
          16192
        ]
      },
      {
        "start": 16184,
        "end": 16191,
        "label": "loc_3F38",
        "instruction_count": 4,
        "cycles_min": 32,
        "cycles_max": 32,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16192,
        "end": 16198,
        "label": "loc_3F40",
        "instruction_count": 3,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "ORC.W #H'0600, SR",
        "targets": []
      },
      {
        "start": 16202,
        "end": 16209,
        "label": "loc_3F4A",
        "instruction_count": 3,
        "cycles_min": 18,
        "cycles_max": 23,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3F4A",
        "targets": [
          16202
        ]
      },
      {
        "start": 16211,
        "end": 16213,
        "label": "loc_3F53",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3F6D",
        "targets": [
          16237
        ]
      },
      {
        "start": 16215,
        "end": 16217,
        "label": "loc_3F57",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3F62",
        "targets": [
          16226
        ]
      },
      {
        "start": 16219,
        "end": 16224,
        "label": "loc_3F5B",
        "instruction_count": 2,
        "cycles_min": 20,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3F72",
        "targets": [
          16242
        ]
      },
      {
        "start": 16226,
        "end": 16235,
        "label": "loc_3F62",
        "instruction_count": 3,
        "cycles_min": 29,
        "cycles_max": 29,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3F72",
        "targets": [
          16242
        ]
      },
      {
        "start": 16237,
        "end": 16237,
        "label": "loc_3F6D",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "MOVFPE.B @H'F201, R4",
        "targets": []
      },
      {
        "start": 16242,
        "end": 16244,
        "label": "loc_3F72",
        "instruction_count": 2,
        "cycles_min": 19,
        "cycles_max": 19,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16246,
        "end": 16249,
        "label": "loc_3F76",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 6,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'C350, R1",
        "targets": []
      },
      {
        "start": 16252,
        "end": 16256,
        "label": "loc_3F7C",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "SCB/F R0, loc_3F7C",
        "targets": [
          16252
        ]
      },
      {
        "start": 16259,
        "end": 16263,
        "label": "loc_3F83",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "SCB/F R1, loc_3F83",
        "targets": [
          16259
        ]
      },
      {
        "start": 16266,
        "end": 16266,
        "label": "loc_3F8A",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "CLR.W R0",
        "targets": []
      },
      {
        "start": 16268,
        "end": 16285,
        "label": "loc_3F8C",
        "instruction_count": 6,
        "cycles_min": 37,
        "cycles_max": 42,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3F8C",
        "targets": [
          16268
        ]
      },
      {
        "start": 16287,
        "end": 16302,
        "label": "loc_3F9F",
        "instruction_count": 6,
        "cycles_min": 81,
        "cycles_max": 81,
        "unknown_cycles": 0,
        "terminator": "BSR loc_434C",
        "targets": [
          17228
        ]
      },
      {
        "start": 16305,
        "end": 16337,
        "label": "loc_3FB1",
        "instruction_count": 11,
        "cycles_min": 133,
        "cycles_max": 133,
        "unknown_cycles": 0,
        "terminator": "BRA loc_3FB1",
        "targets": [
          16305
        ]
      },
      {
        "start": 16339,
        "end": 16343,
        "label": "loc_3FD3",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3FEE",
        "targets": [
          16366
        ]
      },
      {
        "start": 16345,
        "end": 16349,
        "label": "loc_3FD9",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_3FE5",
        "targets": [
          16357
        ]
      },
      {
        "start": 16351,
        "end": 16355,
        "label": "loc_3FDF",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3FEE",
        "targets": [
          16366
        ]
      },
      {
        "start": 16357,
        "end": 16361,
        "label": "loc_3FE5",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_3FEE",
        "targets": [
          16366
        ]
      },
      {
        "start": 16363,
        "end": 16363,
        "label": "loc_3FEB",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_BAF2",
        "targets": [
          47858
        ]
      },
      {
        "start": 16366,
        "end": 16366,
        "label": "loc_3FEE",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16367,
        "end": 16371,
        "label": "loc_3FEF",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_4007",
        "targets": [
          16391
        ]
      },
      {
        "start": 16373,
        "end": 16385,
        "label": "loc_3FF5",
        "instruction_count": 4,
        "cycles_min": 27,
        "cycles_max": 32,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_400B",
        "targets": [
          16395
        ]
      },
      {
        "start": 16387,
        "end": 16389,
        "label": "loc_4003",
        "instruction_count": 2,
        "cycles_min": 22,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "BRA loc_400B",
        "targets": [
          16395
        ]
      },
      {
        "start": 16391,
        "end": 16391,
        "label": "loc_4007",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BSET.B #7, @H'FAA5",
        "targets": []
      },
      {
        "start": 16395,
        "end": 16395,
        "label": "loc_400B",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16396,
        "end": 16453,
        "label": "loc_400C",
        "instruction_count": 16,
        "cycles_min": 156,
        "cycles_max": 156,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16454,
        "end": 16458,
        "label": "loc_4046",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_4058",
        "targets": [
          16472
        ]
      },
      {
        "start": 16460,
        "end": 16464,
        "label": "loc_404C",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_4059",
        "targets": [
          16473
        ]
      },
      {
        "start": 16466,
        "end": 16470,
        "label": "loc_4052",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_4059",
        "targets": [
          16473
        ]
      },
      {
        "start": 16472,
        "end": 16472,
        "label": "loc_4058",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16473,
        "end": 16483,
        "label": "loc_4059",
        "instruction_count": 4,
        "cycles_min": 18,
        "cycles_max": 23,
        "unknown_cycles": 0,
        "terminator": "BNE loc_4074",
        "targets": [
          16500
        ]
      },
      {
        "start": 16485,
        "end": 16496,
        "label": "loc_4065",
        "instruction_count": 4,
        "cycles_min": 31,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #7, @H'F9B0",
        "targets": []
      },
      {
        "start": 16500,
        "end": 16500,
        "label": "loc_4074",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16501,
        "end": 16501,
        "label": "loc_4075",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "CLR.W R0",
        "targets": []
      },
      {
        "start": 16503,
        "end": 16518,
        "label": "loc_4077",
        "instruction_count": 5,
        "cycles_min": 30,
        "cycles_max": 34,
        "unknown_cycles": 0,
        "terminator": "BCC loc_408C",
        "targets": [
          16524
        ]
      },
      {
        "start": 16520,
        "end": 16520,
        "label": "loc_4088",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "CLR.W @(-H'1400,R0)",
        "targets": []
      },
      {
        "start": 16524,
        "end": 16529,
        "label": "loc_408C",
        "instruction_count": 3,
        "cycles_min": 10,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BNE loc_4077",
        "targets": [
          16503
        ]
      },
      {
        "start": 16531,
        "end": 16533,
        "label": "loc_4093",
        "instruction_count": 2,
        "cycles_min": 27,
        "cycles_max": 27,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16534,
        "end": 16570,
        "label": "loc_4096",
        "instruction_count": 7,
        "cycles_min": 78,
        "cycles_max": 78,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16571,
        "end": 16571,
        "label": "loc_40BB",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'0040, R0",
        "targets": []
      },
      {
        "start": 16574,
        "end": 16606,
        "label": "loc_40BE",
        "instruction_count": 7,
        "cycles_min": 52,
        "cycles_max": 56,
        "unknown_cycles": 0,
        "terminator": "BNE loc_40BE",
        "targets": [
          16574
        ]
      },
      {
        "start": 16608,
        "end": 16632,
        "label": "loc_40E0",
        "instruction_count": 6,
        "cycles_min": 46,
        "cycles_max": 50,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_4103",
        "targets": [
          16643
        ]
      },
      {
        "start": 16634,
        "end": 16640,
        "label": "loc_40FA",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_41B0",
        "targets": [
          16816
        ]
      },
      {
        "start": 16643,
        "end": 16643,
        "label": "loc_4103",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'0100, R0",
        "targets": []
      },
      {
        "start": 16646,
        "end": 16770,
        "label": "loc_4106",
        "instruction_count": 38,
        "cycles_min": 311,
        "cycles_max": 315,
        "unknown_cycles": 0,
        "terminator": "BNE loc_4106",
        "targets": [
          16646
        ]
      },
      {
        "start": 16772,
        "end": 16772,
        "label": "loc_4184",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'000F, R0",
        "targets": []
      },
      {
        "start": 16775,
        "end": 16813,
        "label": "loc_4187",
        "instruction_count": 16,
        "cycles_min": 96,
        "cycles_max": 102,
        "unknown_cycles": 0,
        "terminator": "SCB/F R0, loc_4187",
        "targets": [
          16775
        ]
      },
      {
        "start": 16816,
        "end": 16816,
        "label": "loc_41B0",
        "instruction_count": 1,
        "cycles_min": 7,
        "cycles_max": 7,
        "unknown_cycles": 0,
        "terminator": "BRA loc_41D2",
        "targets": [
          16850
        ]
      },
      {
        "start": 16850,
        "end": 16850,
        "label": "loc_41D2",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'000F, R0",
        "targets": []
      },
      {
        "start": 16853,
        "end": 16915,
        "label": "loc_41D5",
        "instruction_count": 26,
        "cycles_min": 214,
        "cycles_max": 220,
        "unknown_cycles": 0,
        "terminator": "SCB/F R0, loc_41D5",
        "targets": [
          16853
        ]
      },
      {
        "start": 16918,
        "end": 16918,
        "label": "loc_4216",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 16919,
        "end": 17163,
        "label": "loc_4217",
        "instruction_count": 51,
        "cycles_min": 444,
        "cycles_max": 444,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 17164,
        "end": 17187,
        "label": "loc_430C",
        "instruction_count": 6,
        "cycles_min": 57,
        "cycles_max": 57,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 17188,
        "end": 17227,
        "label": "loc_4324",
        "instruction_count": 14,
        "cycles_min": 104,
        "cycles_max": 104,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 17228,
        "end": 17286,
        "label": "loc_434C",
        "instruction_count": 14,
        "cycles_min": 118,
        "cycles_max": 122,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_438E",
        "targets": [
          17294
        ]
      },
      {
        "start": 17288,
        "end": 17288,
        "label": "loc_4388",
        "instruction_count": 1,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W #H'A53F, @WDT_TCSR_R",
        "targets": []
      },
      {
        "start": 17294,
        "end": 17298,
        "label": "loc_438E",
        "instruction_count": 2,
        "cycles_min": 18,
        "cycles_max": 18,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 17299,
        "end": 17299,
        "label": "vec_nmi_4393",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "RTE",
        "targets": []
      },
      {
        "start": 17300,
        "end": 17305,
        "label": "loc_4394",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BHI loc_4422",
        "targets": [
          17442
        ]
      },
      {
        "start": 17308,
        "end": 17312,
        "label": "loc_439C",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_4422",
        "targets": [
          17442
        ]
      },
      {
        "start": 17315,
        "end": 17319,
        "label": "loc_43A3",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_4422",
        "targets": [
          17442
        ]
      },
      {
        "start": 17322,
        "end": 17332,
        "label": "loc_43AA",
        "instruction_count": 4,
        "cycles_min": 20,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BNE loc_43CF",
        "targets": [
          17359
        ]
      },
      {
        "start": 17334,
        "end": 17336,
        "label": "loc_43B6",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BNE loc_43DB",
        "targets": [
          17371
        ]
      },
      {
        "start": 17338,
        "end": 17340,
        "label": "loc_43BA",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BNE loc_43E7",
        "targets": [
          17383
        ]
      },
      {
        "start": 17342,
        "end": 17344,
        "label": "loc_43BE",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BNE loc_43F3",
        "targets": [
          17395
        ]
      },
      {
        "start": 17346,
        "end": 17348,
        "label": "loc_43C2",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BNE loc_43FF",
        "targets": [
          17407
        ]
      },
      {
        "start": 17350,
        "end": 17352,
        "label": "loc_43C6",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BNE loc_440D",
        "targets": [
          17421
        ]
      },
      {
        "start": 17354,
        "end": 17357,
        "label": "loc_43CA",
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        "terminator": "BEQ loc_43D9",
        "targets": [
          17369
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      },
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        "start": 17366,
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        "label": "loc_43D6",
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        "terminator": "BSR loc_1A35",
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        "start": 17369,
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        "label": "loc_43D9",
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        "targets": [
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      },
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        "start": 17378,
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        "terminator": "BSR loc_1A9C",
        "targets": [
          6812
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        "start": 17381,
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        "terminator": "BRA loc_4422",
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          17442
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      },
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        "start": 17390,
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        "terminator": "BSR loc_1AE4",
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          6884
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        "start": 17395,
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        "terminator": "BEQ loc_43FD",
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          6923
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      {
        "start": 17405,
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        "label": "loc_43FD",
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          17442
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        "targets": [
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          18682
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        "start": 17455,
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        "terminator": "BCC loc_4444",
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          17476
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        "targets": [
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        "terminator": "MOV:I.W #H'0001, R4",
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      {
        "start": 17494,
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        "label": "loc_4456",
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        "terminator": "BHI loc_44E5",
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          17637
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        "start": 17503,
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        "label": "loc_4466",
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        "terminator": "BEQ loc_44E5",
        "targets": [
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        "start": 17517,
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        "terminator": "BNE loc_4492",
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        "label": "loc_4479",
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        "terminator": "BNE loc_449E",
        "targets": [
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        "terminator": "BNE loc_44AA",
        "targets": [
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        "targets": [
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        "targets": [
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        "start": 17549,
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          17637
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        "start": 17554,
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        "targets": [
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        "label": "loc_4499",
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        "terminator": "BSR loc_1A35",
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        "start": 17564,
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        "terminator": "BRA loc_44E5",
        "targets": [
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        "start": 17566,
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        "terminator": "BEQ loc_44A8",
        "targets": [
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        "start": 17573,
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        "terminator": "BSR loc_1A9C",
        "targets": [
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        "label": "loc_44A8",
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        "targets": [
          17637
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        "terminator": "BEQ loc_44B4",
        "targets": [
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        "label": "loc_44B1",
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        "terminator": "BSR loc_1AE4",
        "targets": [
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        "label": "loc_44B4",
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        "terminator": "BRA loc_44E5",
        "targets": [
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        "label": "loc_44B6",
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        "terminator": "BEQ loc_44C0",
        "targets": [
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        "start": 17597,
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        "terminator": "BSR loc_1B0B",
        "targets": [
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        "start": 17600,
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        "label": "loc_44C0",
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        "targets": [
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        "targets": [
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        "start": 17616,
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        "terminator": "BEQ loc_44E3",
        "targets": [
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        "start": 17623,
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        "label": "loc_44D7",
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        "terminator": "BSR loc_48FA",
        "targets": [
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        "label": "loc_44E3",
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        "targets": [
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        "start": 17637,
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        "terminator": "RTS",
        "targets": []
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        "start": 17650,
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        "label": "loc_44F2",
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        "terminator": "BCC loc_4507",
        "targets": [
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        "start": 17658,
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        "label": "loc_44FA",
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        "terminator": "BLS loc_4511",
        "targets": [
          17681
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        "start": 17662,
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        "label": "loc_44FE",
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        "terminator": "BRA loc_4519",
        "targets": [
          17689
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        "start": 17671,
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        "label": "loc_4507",
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        "unknown_cycles": 0,
        "terminator": "BRA loc_4519",
        "targets": [
          17689
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        "start": 17681,
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        "label": "loc_4511",
        "instruction_count": 2,
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        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'0001, R4",
        "targets": []
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        "start": 17689,
        "end": 17689,
        "label": "loc_4519",
        "instruction_count": 1,
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        "terminator": "RTS",
        "targets": []
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      {
        "start": 17690,
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        "label": "loc_451A",
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        "unknown_cycles": 0,
        "terminator": "BHI loc_45A8",
        "targets": [
          17832
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      },
      {
        "start": 17698,
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        "label": "loc_4522",
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        "terminator": "BNE loc_45A8",
        "targets": [
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        "start": 17705,
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        "label": "loc_4529",
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        "terminator": "BEQ loc_45A8",
        "targets": [
          17832
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        "start": 17712,
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        "label": "loc_4530",
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        "terminator": "BNE loc_4555",
        "targets": [
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        "start": 17724,
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        "label": "loc_453C",
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        "unknown_cycles": 0,
        "terminator": "BNE loc_4561",
        "targets": [
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        "start": 17728,
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        "label": "loc_4540",
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        "unknown_cycles": 0,
        "terminator": "BNE loc_456D",
        "targets": [
          17773
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        "start": 17732,
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        "label": "loc_4544",
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        "terminator": "BNE loc_4579",
        "targets": [
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        "start": 17736,
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        "label": "loc_4548",
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        "terminator": "BNE loc_4585",
        "targets": [
          17797
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        "start": 17740,
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        "terminator": "BNE loc_4593",
        "targets": [
          17811
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        "start": 17744,
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        "label": "loc_4550",
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        "unknown_cycles": 0,
        "terminator": "BRA loc_45A8",
        "targets": [
          17832
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        "start": 17749,
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        "terminator": "BEQ loc_455F",
        "targets": [
          17759
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        "label": "loc_455C",
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        "terminator": "BSR loc_1A35",
        "targets": [
          6709
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        "start": 17759,
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        "label": "loc_455F",
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        "terminator": "BRA loc_45A8",
        "targets": [
          17832
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        "start": 17761,
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        "terminator": "BEQ loc_456B",
        "targets": [
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        "start": 17768,
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        "label": "loc_4568",
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        "terminator": "BSR loc_1A9C",
        "targets": [
          6812
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        "start": 17771,
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        "terminator": "BRA loc_45A8",
        "targets": [
          17832
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      },
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        "start": 17773,
        "end": 17778,
        "label": "loc_456D",
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        "terminator": "BEQ loc_4577",
        "targets": [
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      },
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        "start": 17780,
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        "label": "loc_4574",
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        "terminator": "BSR loc_1AE4",
        "targets": [
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      },
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        "start": 17783,
        "end": 17783,
        "label": "loc_4577",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_45A8",
        "targets": [
          17832
        ]
      },
      {
        "start": 17785,
        "end": 17790,
        "label": "loc_4579",
        "instruction_count": 3,
        "cycles_min": 20,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_4583",
        "targets": [
          17795
        ]
      },
      {
        "start": 17792,
        "end": 17792,
        "label": "loc_4580",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BSR loc_1B0B",
        "targets": [
          6923
        ]
      },
      {
        "start": 17795,
        "end": 17795,
        "label": "loc_4583",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_45A8",
        "targets": [
          17832
        ]
      },
      {
        "start": 17797,
        "end": 17809,
        "label": "loc_4585",
        "instruction_count": 4,
        "cycles_min": 37,
        "cycles_max": 37,
        "unknown_cycles": 0,
        "terminator": "BRA loc_45A8",
        "targets": [
          17832
        ]
      },
      {
        "start": 17811,
        "end": 17816,
        "label": "loc_4593",
        "instruction_count": 3,
        "cycles_min": 20,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_45A6",
        "targets": [
          17830
        ]
      },
      {
        "start": 17818,
        "end": 17827,
        "label": "loc_459A",
        "instruction_count": 3,
        "cycles_min": 29,
        "cycles_max": 29,
        "unknown_cycles": 0,
        "terminator": "BSR loc_48FA",
        "targets": [
          18682
        ]
      },
      {
        "start": 17830,
        "end": 17830,
        "label": "loc_45A6",
        "instruction_count": 1,
        "cycles_min": 7,
        "cycles_max": 7,
        "unknown_cycles": 0,
        "terminator": "BRA loc_45A8",
        "targets": [
          17832
        ]
      },
      {
        "start": 17832,
        "end": 17844,
        "label": "loc_45A8",
        "instruction_count": 4,
        "cycles_min": 35,
        "cycles_max": 35,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 17845,
        "end": 17851,
        "label": "loc_45B5",
        "instruction_count": 3,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BCC loc_45CA",
        "targets": [
          17866
        ]
      },
      {
        "start": 17853,
        "end": 17855,
        "label": "loc_45BD",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BLS loc_45D4",
        "targets": [
          17876
        ]
      },
      {
        "start": 17857,
        "end": 17864,
        "label": "loc_45C1",
        "instruction_count": 3,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_45DC",
        "targets": [
          17884
        ]
      },
      {
        "start": 17866,
        "end": 17874,
        "label": "loc_45CA",
        "instruction_count": 3,
        "cycles_min": 19,
        "cycles_max": 19,
        "unknown_cycles": 0,
        "terminator": "BRA loc_45DC",
        "targets": [
          17884
        ]
      },
      {
        "start": 17876,
        "end": 17881,
        "label": "loc_45D4",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'0001, R4",
        "targets": []
      },
      {
        "start": 17884,
        "end": 17884,
        "label": "loc_45DC",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 18671,
        "end": 18681,
        "label": "loc_48EF",
        "instruction_count": 4,
        "cycles_min": 39,
        "cycles_max": 39,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 18682,
        "end": 18686,
        "label": "loc_48FA",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_4929",
        "targets": [
          18729
        ]
      },
      {
        "start": 18688,
        "end": 18693,
        "label": "loc_4900",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_4929",
        "targets": [
          18729
        ]
      },
      {
        "start": 18695,
        "end": 18701,
        "label": "loc_4907",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_4929",
        "targets": [
          18729
        ]
      },
      {
        "start": 18703,
        "end": 18707,
        "label": "loc_490F",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_4929",
        "targets": [
          18729
        ]
      },
      {
        "start": 18709,
        "end": 18726,
        "label": "loc_4915",
        "instruction_count": 6,
        "cycles_min": 34,
        "cycles_max": 34,
        "unknown_cycles": 0,
        "terminator": "BSR loc_3E54",
        "targets": [
          15956
        ]
      },
      {
        "start": 18729,
        "end": 18733,
        "label": "loc_4929",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_493D",
        "targets": [
          18749
        ]
      },
      {
        "start": 18735,
        "end": 18747,
        "label": "loc_492F",
        "instruction_count": 5,
        "cycles_min": 31,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "JSR @R0",
        "targets": []
      },
      {
        "start": 18749,
        "end": 18749,
        "label": "loc_493D",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 25094,
        "end": 25101,
        "label": "loc_6206",
        "instruction_count": 3,
        "cycles_min": 10,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BLS loc_6216",
        "targets": [
          25110
        ]
      },
      {
        "start": 25103,
        "end": 25106,
        "label": "loc_620F",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BLS loc_6218",
        "targets": [
          25112
        ]
      },
      {
        "start": 25108,
        "end": 25108,
        "label": "loc_6214",
        "instruction_count": 1,
        "cycles_min": 7,
        "cycles_max": 7,
        "unknown_cycles": 0,
        "terminator": "BRA loc_6222",
        "targets": [
          25122
        ]
      },
      {
        "start": 25110,
        "end": 25110,
        "label": "loc_6216",
        "instruction_count": 1,
        "cycles_min": 7,
        "cycles_max": 7,
        "unknown_cycles": 0,
        "terminator": "BRA loc_622A",
        "targets": [
          25130
        ]
      },
      {
        "start": 25112,
        "end": 25120,
        "label": "loc_6218",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BRA loc_622A",
        "targets": [
          25130
        ]
      },
      {
        "start": 25122,
        "end": 25126,
        "label": "loc_6222",
        "instruction_count": 2,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "ADD:G.W #H'0200, R5",
        "targets": []
      },
      {
        "start": 25130,
        "end": 25130,
        "label": "loc_622A",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 25131,
        "end": 25142,
        "label": "loc_622B",
        "instruction_count": 6,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_6244",
        "targets": [
          25156
        ]
      },
      {
        "start": 25144,
        "end": 25146,
        "label": "loc_6238",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_624D",
        "targets": [
          25165
        ]
      },
      {
        "start": 25148,
        "end": 25150,
        "label": "loc_623C",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_6256",
        "targets": [
          25174
        ]
      },
      {
        "start": 25152,
        "end": 25154,
        "label": "loc_6240",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_625F",
        "targets": [
          25183
        ]
      },
      {
        "start": 25156,
        "end": 25158,
        "label": "loc_6244",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BHI loc_625F",
        "targets": [
          25183
        ]
      },
      {
        "start": 25160,
        "end": 25163,
        "label": "loc_6248",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BRA loc_6264",
        "targets": [
          25188
        ]
      },
      {
        "start": 25165,
        "end": 25167,
        "label": "loc_624D",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BHI loc_625F",
        "targets": [
          25183
        ]
      },
      {
        "start": 25169,
        "end": 25172,
        "label": "loc_6251",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BRA loc_6264",
        "targets": [
          25188
        ]
      },
      {
        "start": 25174,
        "end": 25176,
        "label": "loc_6256",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BHI loc_625F",
        "targets": [
          25183
        ]
      },
      {
        "start": 25178,
        "end": 25181,
        "label": "loc_625A",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BRA loc_6264",
        "targets": [
          25188
        ]
      },
      {
        "start": 25183,
        "end": 25185,
        "label": "loc_625F",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 6,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'01FF, R5",
        "targets": []
      },
      {
        "start": 25188,
        "end": 25190,
        "label": "loc_6264",
        "instruction_count": 2,
        "cycles_min": 15,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 47654,
        "end": 47658,
        "label": "loc_BA26",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BA26",
        "targets": [
          47654
        ]
      },
      {
        "start": 47660,
        "end": 47716,
        "label": "loc_BA2C",
        "instruction_count": 15,
        "cycles_min": 104,
        "cycles_max": 104,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B R0, @H'F85D",
        "targets": []
      },
      {
        "start": 47720,
        "end": 47724,
        "label": "loc_BA68",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BA68",
        "targets": [
          47720
        ]
      },
      {
        "start": 47726,
        "end": 47747,
        "label": "loc_BA6E",
        "instruction_count": 6,
        "cycles_min": 52,
        "cycles_max": 52,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 47748,
        "end": 47752,
        "label": "vec_sci1_txi_BA84",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BAA9",
        "targets": [
          47785
        ]
      },
      {
        "start": 47754,
        "end": 47758,
        "label": "loc_BA8A",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BAA9",
        "targets": [
          47785
        ]
      },
      {
        "start": 47760,
        "end": 47764,
        "label": "loc_BA90",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BAA9",
        "targets": [
          47785
        ]
      },
      {
        "start": 47766,
        "end": 47783,
        "label": "loc_BA96",
        "instruction_count": 5,
        "cycles_min": 44,
        "cycles_max": 44,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BAF1",
        "targets": [
          47857
        ]
      },
      {
        "start": 47785,
        "end": 47816,
        "label": "loc_BAA9",
        "instruction_count": 10,
        "cycles_min": 57,
        "cycles_max": 61,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BAF1",
        "targets": [
          47857
        ]
      },
      {
        "start": 47818,
        "end": 47826,
        "label": "loc_BACA",
        "instruction_count": 3,
        "cycles_min": 19,
        "cycles_max": 23,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BAE8",
        "targets": [
          47848
        ]
      },
      {
        "start": 47828,
        "end": 47832,
        "label": "loc_BAD4",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BAE1",
        "targets": [
          47841
        ]
      },
      {
        "start": 47834,
        "end": 47839,
        "label": "loc_BADA",
        "instruction_count": 2,
        "cycles_min": 17,
        "cycles_max": 17,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BAED",
        "targets": [
          47853
        ]
      },
      {
        "start": 47841,
        "end": 47846,
        "label": "loc_BAE1",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BAED",
        "targets": [
          47853
        ]
      },
      {
        "start": 47848,
        "end": 47848,
        "label": "loc_BAE8",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B #H'F0, @H'F9C0",
        "targets": []
      },
      {
        "start": 47853,
        "end": 47853,
        "label": "loc_BAED",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "CLR.B @H'F9C1",
        "targets": []
      },
      {
        "start": 47857,
        "end": 47857,
        "label": "loc_BAF1",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "RTE",
        "targets": []
      },
      {
        "start": 47858,
        "end": 47868,
        "label": "loc_BAF2",
        "instruction_count": 4,
        "cycles_min": 20,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BB00",
        "targets": [
          47872
        ]
      },
      {
        "start": 47870,
        "end": 47870,
        "label": "loc_BAFE",
        "instruction_count": 1,
        "cycles_min": 7,
        "cycles_max": 7,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BB56",
        "targets": [
          47958
        ]
      },
      {
        "start": 47872,
        "end": 47953,
        "label": "loc_BB00",
        "instruction_count": 27,
        "cycles_min": 150,
        "cycles_max": 150,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B #H'80, @H'FAA3",
        "targets": []
      },
      {
        "start": 47958,
        "end": 47958,
        "label": "loc_BB56",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 47959,
        "end": 47971,
        "label": "vec_sci1_eri_BB57",
        "instruction_count": 4,
        "cycles_min": 32,
        "cycles_max": 32,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #3, @SCI1_SSR",
        "targets": []
      },
      {
        "start": 47975,
        "end": 47989,
        "label": "vec_sci1_rxi_BB67",
        "instruction_count": 5,
        "cycles_min": 35,
        "cycles_max": 40,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BB7D",
        "targets": [
          47997
        ]
      },
      {
        "start": 47991,
        "end": 47995,
        "label": "loc_BB77",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BB8A",
        "targets": [
          48010
        ]
      },
      {
        "start": 47997,
        "end": 48002,
        "label": "loc_BB7D",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BLS loc_BB8A",
        "targets": [
          48010
        ]
      },
      {
        "start": 48004,
        "end": 48008,
        "label": "loc_BB84",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BBA3",
        "targets": [
          48035
        ]
      },
      {
        "start": 48010,
        "end": 48028,
        "label": "loc_BB8A",
        "instruction_count": 7,
        "cycles_min": 33,
        "cycles_max": 37,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BBA3",
        "targets": [
          48035
        ]
      },
      {
        "start": 48030,
        "end": 48030,
        "label": "loc_BB9E",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B #H'14, @H'F9C5",
        "targets": []
      },
      {
        "start": 48035,
        "end": 48042,
        "label": "loc_BBA3",
        "instruction_count": 3,
        "cycles_min": 36,
        "cycles_max": 36,
        "unknown_cycles": 0,
        "terminator": "RTE",
        "targets": []
      },
      {
        "start": 48043,
        "end": 48048,
        "label": "loc_BBAB",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BE6F",
        "targets": [
          48751
        ]
      },
      {
        "start": 48051,
        "end": 48083,
        "label": "loc_BBB3",
        "instruction_count": 9,
        "cycles_min": 53,
        "cycles_max": 58,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BE29",
        "targets": [
          48681
        ]
      },
      {
        "start": 48086,
        "end": 48112,
        "label": "loc_BBD6",
        "instruction_count": 8,
        "cycles_min": 47,
        "cycles_max": 51,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BE29",
        "targets": [
          48681
        ]
      },
      {
        "start": 48115,
        "end": 48147,
        "label": "loc_BBF3",
        "instruction_count": 11,
        "cycles_min": 62,
        "cycles_max": 67,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BC3A",
        "targets": [
          48186
        ]
      },
      {
        "start": 48149,
        "end": 48157,
        "label": "loc_BC15",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BD0B",
        "targets": [
          48395
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      },
      {
        "start": 48160,
        "end": 48162,
        "label": "loc_BC20",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BC69",
        "targets": [
          48233
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      },
      {
        "start": 48164,
        "end": 48166,
        "label": "loc_BC24",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BCD7",
        "targets": [
          48343
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      },
      {
        "start": 48169,
        "end": 48171,
        "label": "loc_BC29",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BD04",
        "targets": [
          48388
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      },
      {
        "start": 48174,
        "end": 48176,
        "label": "loc_BC2E",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BE05",
        "targets": [
          48645
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      },
      {
        "start": 48179,
        "end": 48183,
        "label": "loc_BC33",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48186,
        "end": 48188,
        "label": "loc_BC3A",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BC5C",
        "targets": [
          48220
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      },
      {
        "start": 48190,
        "end": 48194,
        "label": "loc_BC3E",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BE27",
        "targets": [
          48679
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      },
      {
        "start": 48197,
        "end": 48199,
        "label": "loc_BC45",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BD0E",
        "targets": [
          48398
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      },
      {
        "start": 48202,
        "end": 48204,
        "label": "loc_BC4A",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BD80",
        "targets": [
          48512
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      },
      {
        "start": 48207,
        "end": 48209,
        "label": "loc_BC4F",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDDB",
        "targets": [
          48603
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      },
      {
        "start": 48212,
        "end": 48214,
        "label": "loc_BC54",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BE05",
        "targets": [
          48645
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      },
      {
        "start": 48217,
        "end": 48217,
        "label": "loc_BC59",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48220,
        "end": 48224,
        "label": "loc_BC5C",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48227,
        "end": 48231,
        "label": "loc_BC63",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BC15",
        "targets": [
          48149
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      },
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        "start": 48233,
        "end": 48235,
        "label": "loc_BC69",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BC8B",
        "targets": [
          48267
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      },
      {
        "start": 48237,
        "end": 48265,
        "label": "loc_BC6D",
        "instruction_count": 9,
        "cycles_min": 62,
        "cycles_max": 62,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BCB0",
        "targets": [
          48304
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      },
      {
        "start": 48267,
        "end": 48295,
        "label": "loc_BC8B",
        "instruction_count": 9,
        "cycles_min": 47,
        "cycles_max": 52,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BCAD",
        "targets": [
          48301
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      },
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        "start": 48297,
        "end": 48297,
        "label": "loc_BCA9",
        "instruction_count": 1,
        "cycles_min": 6,
        "cycles_max": 6,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W R0, @(-H'0C00,R1)",
        "targets": []
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      {
        "start": 48301,
        "end": 48301,
        "label": "loc_BCAD",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_BE70",
        "targets": [
          48752
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      },
      {
        "start": 48304,
        "end": 48340,
        "label": "loc_BCB0",
        "instruction_count": 10,
        "cycles_min": 75,
        "cycles_max": 75,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48343,
        "end": 48385,
        "label": "loc_BCD7",
        "instruction_count": 12,
        "cycles_min": 90,
        "cycles_max": 90,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48388,
        "end": 48392,
        "label": "loc_BD04",
        "instruction_count": 2,
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        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
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        "start": 48395,
        "end": 48395,
        "label": "loc_BD0B",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48398,
        "end": 48400,
        "label": "loc_BD0E",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BD2B",
        "targets": [
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      },
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        "start": 48402,
        "end": 48425,
        "label": "loc_BD12",
        "instruction_count": 8,
        "cycles_min": 56,
        "cycles_max": 56,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BD67",
        "targets": [
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      },
      {
        "start": 48427,
        "end": 48451,
        "label": "loc_BD2B",
        "instruction_count": 8,
        "cycles_min": 41,
        "cycles_max": 46,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BD64",
        "targets": [
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      },
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        "start": 48453,
        "end": 48461,
        "label": "loc_BD45",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 20,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BD64",
        "targets": [
          48484
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      },
      {
        "start": 48463,
        "end": 48482,
        "label": "loc_BD4F",
        "instruction_count": 8,
        "cycles_min": 65,
        "cycles_max": 65,
        "unknown_cycles": 0,
        "terminator": "LDM.W @SP+, {R0,R4,R5}",
        "targets": []
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      {
        "start": 48484,
        "end": 48484,
        "label": "loc_BD64",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BSR loc_BE70",
        "targets": [
          48752
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      },
      {
        "start": 48487,
        "end": 48491,
        "label": "loc_BD67",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BD75",
        "targets": [
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      },
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        "start": 48493,
        "end": 48497,
        "label": "loc_BD6D",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #7, @H'F9B5",
        "targets": []
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      {
        "start": 48501,
        "end": 48509,
        "label": "loc_BD75",
        "instruction_count": 3,
        "cycles_min": 24,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
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        "start": 48512,
        "end": 48515,
        "label": "loc_BD80",
        "instruction_count": 2,
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        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDBF",
        "targets": [
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      },
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        "start": 48517,
        "end": 48520,
        "label": "loc_BD85",
        "instruction_count": 2,
        "cycles_min": 6,
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        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDBF",
        "targets": [
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      },
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        "start": 48522,
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        "label": "loc_BD8A",
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        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDBF",
        "targets": [
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      },
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        "start": 48527,
        "end": 48530,
        "label": "loc_BD8F",
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        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDBF",
        "targets": [
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      },
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        "start": 48532,
        "end": 48536,
        "label": "loc_BD94",
        "instruction_count": 2,
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        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDC2",
        "targets": [
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      },
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        "start": 48538,
        "end": 48541,
        "label": "loc_BD9A",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDB5",
        "targets": [
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      },
      {
        "start": 48543,
        "end": 48546,
        "label": "loc_BD9F",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDB5",
        "targets": [
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      },
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        "start": 48548,
        "end": 48551,
        "label": "loc_BDA4",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDB5",
        "targets": [
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      },
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        "start": 48553,
        "end": 48556,
        "label": "loc_BDA9",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 10,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDB5",
        "targets": [
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      },
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        "start": 48558,
        "end": 48561,
        "label": "loc_BDAE",
        "instruction_count": 2,
        "cycles_min": 6,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDB5",
        "targets": [
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      },
      {
        "start": 48563,
        "end": 48563,
        "label": "loc_BDB3",
        "instruction_count": 1,
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        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BDC2",
        "targets": [
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      },
      {
        "start": 48565,
        "end": 48573,
        "label": "loc_BDB5",
        "instruction_count": 3,
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        "unknown_cycles": 0,
        "terminator": "BRA loc_BDC2",
        "targets": [
          48578
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      },
      {
        "start": 48575,
        "end": 48575,
        "label": "loc_BDBF",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_BE70",
        "targets": [
          48752
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      },
      {
        "start": 48578,
        "end": 48582,
        "label": "loc_BDC2",
        "instruction_count": 2,
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        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDD0",
        "targets": [
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      },
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        "start": 48584,
        "end": 48588,
        "label": "loc_BDC8",
        "instruction_count": 2,
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        "cycles_max": 18,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #7, @H'F9B5",
        "targets": []
      },
      {
        "start": 48592,
        "end": 48600,
        "label": "loc_BDD0",
        "instruction_count": 3,
        "cycles_min": 25,
        "cycles_max": 25,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48603,
        "end": 48625,
        "label": "loc_BDDB",
        "instruction_count": 7,
        "cycles_min": 38,
        "cycles_max": 43,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BDFB",
        "targets": [
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      },
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        "start": 48627,
        "end": 48631,
        "label": "loc_BDF3",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #7, @H'F9B5",
        "targets": []
      },
      {
        "start": 48635,
        "end": 48643,
        "label": "loc_BDFB",
        "instruction_count": 3,
        "cycles_min": 24,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48645,
        "end": 48677,
        "label": "loc_BE05",
        "instruction_count": 9,
        "cycles_min": 66,
        "cycles_max": 66,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48679,
        "end": 48679,
        "label": "loc_BE27",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48681,
        "end": 48689,
        "label": "loc_BE29",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BE6D",
        "targets": [
          48749
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      },
      {
        "start": 48691,
        "end": 48700,
        "label": "loc_BE33",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 21,
        "unknown_cycles": 0,
        "terminator": "BCS loc_BE4D",
        "targets": [
          48717
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      },
      {
        "start": 48702,
        "end": 48715,
        "label": "loc_BE3E",
        "instruction_count": 4,
        "cycles_min": 33,
        "cycles_max": 33,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6D",
        "targets": [
          48749
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      },
      {
        "start": 48717,
        "end": 48746,
        "label": "loc_BE4D",
        "instruction_count": 8,
        "cycles_min": 64,
        "cycles_max": 64,
        "unknown_cycles": 0,
        "terminator": "BSR loc_BA26",
        "targets": [
          47654
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      },
      {
        "start": 48749,
        "end": 48749,
        "label": "loc_BE6D",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE6F",
        "targets": [
          48751
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      },
      {
        "start": 48751,
        "end": 48751,
        "label": "loc_BE6F",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 48752,
        "end": 48766,
        "label": "loc_BE70",
        "instruction_count": 6,
        "cycles_min": 26,
        "cycles_max": 26,
        "unknown_cycles": 0,
        "terminator": "SHLL.W R1",
        "targets": []
      },
      {
        "start": 48768,
        "end": 48770,
        "label": "loc_BE80",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BE91",
        "targets": [
          48785
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      },
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        "start": 48772,
        "end": 48776,
        "label": "loc_BE84",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BE9D",
        "targets": [
          48797
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      },
      {
        "start": 48778,
        "end": 48783,
        "label": "loc_BE8A",
        "instruction_count": 3,
        "cycles_min": 15,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BE80",
        "targets": [
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      },
      {
        "start": 48785,
        "end": 48793,
        "label": "loc_BE91",
        "instruction_count": 3,
        "cycles_min": 22,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #5, @H'F9B4",
        "targets": []
      },
      {
        "start": 48797,
        "end": 48797,
        "label": "loc_BE9D",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 48798,
        "end": 48813,
        "label": "loc_BE9E",
        "instruction_count": 5,
        "cycles_min": 25,
        "cycles_max": 30,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BEB5",
        "targets": [
          48821
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      },
      {
        "start": 48815,
        "end": 48819,
        "label": "loc_BEAF",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BEE8",
        "targets": [
          48872
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      },
      {
        "start": 48821,
        "end": 48825,
        "label": "loc_BEB5",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BEE8",
        "targets": [
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      },
      {
        "start": 48827,
        "end": 48831,
        "label": "loc_BEBB",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BEE4",
        "targets": [
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      },
      {
        "start": 48833,
        "end": 48847,
        "label": "loc_BEC1",
        "instruction_count": 4,
        "cycles_min": 26,
        "cycles_max": 31,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BEE8",
        "targets": [
          48872
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      },
      {
        "start": 48849,
        "end": 48856,
        "label": "loc_BED1",
        "instruction_count": 3,
        "cycles_min": 29,
        "cycles_max": 29,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BEE8",
        "targets": [
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      },
      {
        "start": 48868,
        "end": 48868,
        "label": "loc_BEE4",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "CLR.B @H'F9C5",
        "targets": []
      },
      {
        "start": 48872,
        "end": 48872,
        "label": "loc_BEE8",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 48874,
        "end": 48882,
        "label": "vec_frt1_ocia_BEEA",
        "instruction_count": 3,
        "cycles_min": 19,
        "cycles_max": 23,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BEF8",
        "targets": [
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      },
      {
        "start": 48884,
        "end": 48884,
        "label": "loc_BEF4",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "ADD:Q.B #-1, @H'F9C0",
        "targets": []
      },
      {
        "start": 48888,
        "end": 48892,
        "label": "loc_BEF8",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF02",
        "targets": [
          48898
        ]
      },
      {
        "start": 48894,
        "end": 48894,
        "label": "loc_BEFE",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "ADD:Q.B #-1, @H'F9C1",
        "targets": []
      },
      {
        "start": 48898,
        "end": 48902,
        "label": "loc_BF02",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF0C",
        "targets": [
          48908
        ]
      },
      {
        "start": 48904,
        "end": 48904,
        "label": "loc_BF08",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "ADD:Q.W #-1, @H'F9C6",
        "targets": []
      },
      {
        "start": 48908,
        "end": 48912,
        "label": "loc_BF0C",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF22",
        "targets": [
          48930
        ]
      },
      {
        "start": 48914,
        "end": 48918,
        "label": "loc_BF12",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BF1E",
        "targets": [
          48926
        ]
      },
      {
        "start": 48920,
        "end": 48924,
        "label": "loc_BF18",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BF22",
        "targets": [
          48930
        ]
      },
      {
        "start": 48926,
        "end": 48926,
        "label": "loc_BF1E",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "ADD:Q.W #-1, @H'F6F4",
        "targets": []
      },
      {
        "start": 48930,
        "end": 48930,
        "label": "loc_BF22",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTE",
        "targets": []
      },
      {
        "start": 48931,
        "end": 48939,
        "label": "vec_frt2_ocia_BF23",
        "instruction_count": 3,
        "cycles_min": 17,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF31",
        "targets": [
          48945
        ]
      },
      {
        "start": 48941,
        "end": 48941,
        "label": "loc_BF2D",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "ADD:Q.B #-1, @H'F9C4",
        "targets": []
      },
      {
        "start": 48945,
        "end": 48949,
        "label": "loc_BF31",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF3B",
        "targets": [
          48955
        ]
      },
      {
        "start": 48951,
        "end": 48951,
        "label": "loc_BF37",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "ADD:Q.B #-1, @H'F9C5",
        "targets": []
      },
      {
        "start": 48955,
        "end": 48959,
        "label": "loc_BF3B",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF47",
        "targets": [
          48967
        ]
      },
      {
        "start": 48961,
        "end": 48965,
        "label": "loc_BF41",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BF50",
        "targets": [
          48976
        ]
      },
      {
        "start": 48967,
        "end": 48972,
        "label": "loc_BF47",
        "instruction_count": 2,
        "cycles_min": 18,
        "cycles_max": 18,
        "unknown_cycles": 0,
        "terminator": "NOT.B @H'F723",
        "targets": []
      },
      {
        "start": 48976,
        "end": 48980,
        "label": "loc_BF50",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF6D",
        "targets": [
          49005
        ]
      },
      {
        "start": 48982,
        "end": 48986,
        "label": "loc_BF56",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF62",
        "targets": [
          48994
        ]
      },
      {
        "start": 48988,
        "end": 48992,
        "label": "loc_BF5C",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BF6D",
        "targets": [
          49005
        ]
      },
      {
        "start": 48994,
        "end": 49003,
        "label": "loc_BF62",
        "instruction_count": 4,
        "cycles_min": 76,
        "cycles_max": 76,
        "unknown_cycles": 0,
        "terminator": "LDM.W @SP+, {R0,R1,R2,R3,R4,R5}",
        "targets": []
      },
      {
        "start": 49005,
        "end": 49009,
        "label": "loc_BF6D",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF77",
        "targets": [
          49015
        ]
      },
      {
        "start": 49011,
        "end": 49011,
        "label": "loc_BF73",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "ADD:Q.B #-1, @H'F76C",
        "targets": []
      },
      {
        "start": 49015,
        "end": 49019,
        "label": "loc_BF77",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BF81",
        "targets": [
          49025
        ]
      },
      {
        "start": 49021,
        "end": 49021,
        "label": "loc_BF7D",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "ADD:Q.B #-1, @H'F840",
        "targets": []
      },
      {
        "start": 49025,
        "end": 49029,
        "label": "loc_BF81",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BFA3",
        "targets": [
          49059
        ]
      },
      {
        "start": 49031,
        "end": 49035,
        "label": "loc_BF87",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BFA3",
        "targets": [
          49059
        ]
      },
      {
        "start": 49037,
        "end": 49041,
        "label": "loc_BF8D",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BFA3",
        "targets": [
          49059
        ]
      },
      {
        "start": 49043,
        "end": 49055,
        "label": "loc_BF93",
        "instruction_count": 4,
        "cycles_min": 32,
        "cycles_max": 32,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #4, @H'F711",
        "targets": []
      },
      {
        "start": 49059,
        "end": 49063,
        "label": "loc_BFA3",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BFB3",
        "targets": [
          49075
        ]
      },
      {
        "start": 49065,
        "end": 49069,
        "label": "loc_BFA9",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BFB3",
        "targets": [
          49075
        ]
      },
      {
        "start": 49071,
        "end": 49071,
        "label": "loc_BFAF",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #7, @H'F731",
        "targets": []
      },
      {
        "start": 49075,
        "end": 49079,
        "label": "loc_BFB3",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BFC3",
        "targets": [
          49091
        ]
      },
      {
        "start": 49081,
        "end": 49085,
        "label": "loc_BFB9",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BFC3",
        "targets": [
          49091
        ]
      },
      {
        "start": 49087,
        "end": 49087,
        "label": "loc_BFBF",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #7, @H'F731",
        "targets": []
      },
      {
        "start": 49091,
        "end": 49091,
        "label": "loc_BFC3",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "RTE",
        "targets": []
      },
      {
        "start": 49092,
        "end": 49111,
        "label": "vec_interval_timer_BFC4",
        "instruction_count": 5,
        "cycles_min": 37,
        "cycles_max": 42,
        "unknown_cycles": 0,
        "terminator": "BNE loc_BFDF",
        "targets": [
          49119
        ]
      },
      {
        "start": 49113,
        "end": 49113,
        "label": "loc_BFD9",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "MOV:G.W #H'A57F, @WDT_TCSR_R",
        "targets": []
      },
      {
        "start": 49119,
        "end": 49119,
        "label": "loc_BFDF",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "RTE",
        "targets": []
      },
      {
        "start": 49120,
        "end": 49120,
        "label": "loc_BFE0",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "MOV:G.B #H'0A, @H'F840",
        "targets": []
      },
      {
        "start": 49125,
        "end": 49133,
        "label": "loc_BFE5",
        "instruction_count": 5,
        "cycles_min": 37,
        "cycles_max": 42,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BFFD",
        "targets": [
          49149
        ]
      },
      {
        "start": 49135,
        "end": 49139,
        "label": "loc_BFEF",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_BFF9",
        "targets": [
          49145
        ]
      },
      {
        "start": 49141,
        "end": 49143,
        "label": "loc_BFF5",
        "instruction_count": 2,
        "cycles_min": 11,
        "cycles_max": 11,
        "unknown_cycles": 0,
        "terminator": "BRA loc_BFE5",
        "targets": [
          49125
        ]
      },
      {
        "start": 49145,
        "end": 49145,
        "label": "loc_BFF9",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BSET.B #7, @H'F841",
        "targets": []
      },
      {
        "start": 49149,
        "end": 49149,
        "label": "loc_BFFD",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 49150,
        "end": 49161,
        "label": "loc_BFFE",
        "instruction_count": 4,
        "cycles_min": 32,
        "cycles_max": 37,
        "unknown_cycles": 0,
        "terminator": "BNE loc_C00F",
        "targets": [
          49167
        ]
      },
      {
        "start": 49163,
        "end": 49163,
        "label": "loc_C00B",
        "instruction_count": 1,
        "cycles_min": 8,
        "cycles_max": 8,
        "unknown_cycles": 0,
        "terminator": "BSET.B #6, @H'F841",
        "targets": []
      },
      {
        "start": 49167,
        "end": 49167,
        "label": "loc_C00F",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 49168,
        "end": 49168,
        "label": "loc_C010",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "BSR loc_C06A",
        "targets": [
          49258
        ]
      },
      {
        "start": 49170,
        "end": 49174,
        "label": "loc_C012",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C038",
        "targets": [
          49208
        ]
      },
      {
        "start": 49176,
        "end": 49183,
        "label": "loc_C018",
        "instruction_count": 4,
        "cycles_min": 32,
        "cycles_max": 37,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C012",
        "targets": [
          49170
        ]
      },
      {
        "start": 49185,
        "end": 49189,
        "label": "loc_C021",
        "instruction_count": 3,
        "cycles_min": 19,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C012",
        "targets": [
          49170
        ]
      },
      {
        "start": 49191,
        "end": 49197,
        "label": "loc_C027",
        "instruction_count": 4,
        "cycles_min": 23,
        "cycles_max": 28,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C012",
        "targets": [
          49170
        ]
      },
      {
        "start": 49199,
        "end": 49203,
        "label": "loc_C02F",
        "instruction_count": 3,
        "cycles_min": 19,
        "cycles_max": 24,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C012",
        "targets": [
          49170
        ]
      },
      {
        "start": 49205,
        "end": 49205,
        "label": "loc_C035",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_C142",
        "targets": [
          49474
        ]
      },
      {
        "start": 49208,
        "end": 49208,
        "label": "loc_C038",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 49209,
        "end": 49209,
        "label": "loc_C039",
        "instruction_count": 1,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BSR loc_C06A",
        "targets": [
          49258
        ]
      },
      {
        "start": 49211,
        "end": 49215,
        "label": "loc_C03B",
        "instruction_count": 2,
        "cycles_min": 9,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C069",
        "targets": [
          49257
        ]
      },
      {
        "start": 49217,
        "end": 49224,
        "label": "loc_C041",
        "instruction_count": 4,
        "cycles_min": 32,
        "cycles_max": 36,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C03B",
        "targets": [
          49211
        ]
      },
      {
        "start": 49226,
        "end": 49230,
        "label": "loc_C04A",
        "instruction_count": 3,
        "cycles_min": 18,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C03B",
        "targets": [
          49211
        ]
      },
      {
        "start": 49232,
        "end": 49241,
        "label": "loc_C050",
        "instruction_count": 5,
        "cycles_min": 34,
        "cycles_max": 39,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C03B",
        "targets": [
          49211
        ]
      },
      {
        "start": 49243,
        "end": 49254,
        "label": "loc_C05B",
        "instruction_count": 5,
        "cycles_min": 57,
        "cycles_max": 57,
        "unknown_cycles": 0,
        "terminator": "BSR loc_C142",
        "targets": [
          49474
        ]
      },
      {
        "start": 49257,
        "end": 49257,
        "label": "loc_C069",
        "instruction_count": 1,
        "cycles_min": 13,
        "cycles_max": 13,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 49258,
        "end": 49265,
        "label": "loc_C06A",
        "instruction_count": 3,
        "cycles_min": 10,
        "cycles_max": 15,
        "unknown_cycles": 0,
        "terminator": "BCC loc_C07E",
        "targets": [
          49278
        ]
      },
      {
        "start": 49267,
        "end": 49276,
        "label": "loc_C073",
        "instruction_count": 5,
        "cycles_min": 18,
        "cycles_max": 18,
        "unknown_cycles": 0,
        "terminator": "BRA loc_C08A",
        "targets": [
          49290
        ]
      },
      {
        "start": 49278,
        "end": 49287,
        "label": "loc_C07E",
        "instruction_count": 5,
        "cycles_min": 14,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "terminator": "OR.B #H'E0, R3",
        "targets": []
      },
      {
        "start": 49290,
        "end": 49290,
        "label": "loc_C08A",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
      },
      {
        "start": 49291,
        "end": 49291,
        "label": "loc_C08B",
        "instruction_count": 1,
        "cycles_min": 3,
        "cycles_max": 3,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'0007, R1",
        "targets": []
      },
      {
        "start": 49294,
        "end": 49296,
        "label": "loc_C08E",
        "instruction_count": 2,
        "cycles_min": 5,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BCC loc_C098",
        "targets": [
          49304
        ]
      },
      {
        "start": 49298,
        "end": 49302,
        "label": "loc_C092",
        "instruction_count": 2,
        "cycles_min": 16,
        "cycles_max": 16,
        "unknown_cycles": 0,
        "terminator": "BRA loc_C09C",
        "targets": [
          49308
        ]
      },
      {
        "start": 49304,
        "end": 49304,
        "label": "loc_C098",
        "instruction_count": 1,
        "cycles_min": 9,
        "cycles_max": 9,
        "unknown_cycles": 0,
        "terminator": "BCLR.B #7, @P9DR",
        "targets": []
      },
      {
        "start": 49308,
        "end": 49324,
        "label": "loc_C09C",
        "instruction_count": 5,
        "cycles_min": 39,
        "cycles_max": 44,
        "unknown_cycles": 0,
        "terminator": "SCB/F R1, loc_C08E",
        "targets": [
          49294
        ]
      },
      {
        "start": 49327,
        "end": 49344,
        "label": "loc_C0AF",
        "instruction_count": 5,
        "cycles_min": 37,
        "cycles_max": 41,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C0CF",
        "targets": [
          49359
        ]
      },
      {
        "start": 49346,
        "end": 49357,
        "label": "loc_C0C2",
        "instruction_count": 4,
        "cycles_min": 28,
        "cycles_max": 28,
        "unknown_cycles": 0,
        "terminator": "BRA loc_C0DA",
        "targets": [
          49370
        ]
      },
      {
        "start": 49359,
        "end": 49368,
        "label": "loc_C0CF",
        "instruction_count": 3,
        "cycles_min": 19,
        "cycles_max": 19,
        "unknown_cycles": 0,
        "terminator": "MOV:E.B #H'01, R0",
        "targets": []
      },
      {
        "start": 49370,
        "end": 49370,
        "label": "loc_C0DA",
        "instruction_count": 1,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "RTS",
        "targets": []
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      {
        "start": 49371,
        "end": 49376,
        "label": "loc_C0DB",
        "instruction_count": 2,
        "cycles_min": 12,
        "cycles_max": 12,
        "unknown_cycles": 0,
        "terminator": "MOV:I.W #H'0007, R1",
        "targets": []
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        "start": 49379,
        "end": 49391,
        "label": "loc_C0E3",
        "instruction_count": 4,
        "cycles_min": 25,
        "cycles_max": 30,
        "unknown_cycles": 0,
        "terminator": "BEQ loc_C0F5",
        "targets": [
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        "start": 49393,
        "end": 49395,
        "label": "loc_C0F1",
        "instruction_count": 2,
        "cycles_min": 10,
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        "unknown_cycles": 0,
        "terminator": "BRA loc_C0F7",
        "targets": [
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        "start": 49397,
        "end": 49397,
        "label": "loc_C0F5",
        "instruction_count": 1,
        "cycles_min": 2,
        "cycles_max": 2,
        "unknown_cycles": 0,
        "terminator": "BCLR.B R1, R5",
        "targets": []
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      {
        "start": 49399,
        "end": 49411,
        "label": "loc_C0F7",
        "instruction_count": 4,
        "cycles_min": 27,
        "cycles_max": 33,
        "unknown_cycles": 0,
        "terminator": "SCB/F R1, loc_C0E3",
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        "start": 49414,
        "end": 49419,
        "label": "loc_C106",
        "instruction_count": 2,
        "cycles_min": 22,
        "cycles_max": 22,
        "unknown_cycles": 0,
        "terminator": "RTS",
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        "start": 49420,
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        "label": "loc_C10C",
        "instruction_count": 6,
        "cycles_min": 57,
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        "unknown_cycles": 0,
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        "start": 49441,
        "end": 49473,
        "label": "loc_C121",
        "instruction_count": 9,
        "cycles_min": 77,
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        "unknown_cycles": 0,
        "terminator": "RTS",
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        "start": 49474,
        "end": 49506,
        "label": "loc_C142",
        "instruction_count": 9,
        "cycles_min": 84,
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        "unknown_cycles": 0,
        "terminator": "RTS",
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        "label": "loc_1A4B",
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        "back_edge_text": "BEQ loc_1A4B",
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        "end": 6757,
        "label": "loc_1A5B",
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        "back_edge_text": "BEQ loc_1A5B",
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        "cycles_min": 18,
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        "kind": "delay_loop_candidate"
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        "cycles_min": 23,
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        "end": 6795,
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        "back_edge_text": "BRA loc_1A45",
        "instruction_count": 31,
        "cycles_min": 147,
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        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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        "end": 6804,
        "label": "loc_1A90",
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        "back_edge_text": "SCB/F R1, loc_1A90",
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        "cycles_min": 9,
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        "label": "loc_1AAF",
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        "back_edge_text": "BEQ loc_1AAF",
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        "cycles_min": 17,
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        "kind": "delay_loop_candidate"
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        "start": 6844,
        "end": 6853,
        "label": "loc_1ABC",
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        "cycles_min": 16,
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        "kind": "delay_loop_candidate"
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        "start": 7182,
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        "back_edge_text": "BRA loc_1C0E",
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        "cycles_min": 67,
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        "unknown_cycles": 0,
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        "end": 11446,
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        "back_edge_text": "BRA loc_289F",
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        "cycles_min": 97,
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        "kind": "loop_with_call"
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        "start": 14643,
        "end": 14687,
        "label": "loc_3933",
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        "back_edge_text": "SCB/F R0, loc_3933",
        "instruction_count": 14,
        "cycles_min": 87,
        "cycles_max": 107,
        "unknown_cycles": 0,
        "has_call": false,
        "kind": "counter_delay_loop"
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        "back_edge_text": "BRA loc_3E68",
        "instruction_count": 6,
        "cycles_min": 26,
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        "label": "loc_3E82",
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        "back_edge_text": "BRA loc_3E82",
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        "cycles_min": 70,
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        "unknown_cycles": 0,
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        "kind": "loop_with_call"
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        "label": "loc_3EAE",
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        "back_edge_text": "BRA loc_3EAE",
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        "back_edge_text": "BRA loc_3F04",
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        "start": 16202,
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        "back_edge_text": "BNE loc_3F4A",
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        "start": 16252,
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        "label": "loc_3F7C",
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        "back_edge_text": "SCB/F R0, loc_3F7C",
        "instruction_count": 2,
        "cycles_min": 12,
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        "start": 16259,
        "end": 16263,
        "label": "loc_3F83",
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        "back_edge_text": "SCB/F R1, loc_3F83",
        "instruction_count": 2,
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        "kind": "counter_delay_loop"
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        "back_edge_text": "BSR loc_2806",
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        "label": "loc_3930",
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        "back_edge_text": "BSR loc_3930",
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        "back_edge_text": "BSR loc_15E0",
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        "kind": "loop_with_call"
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        "back_edge_text": "BRA loc_3FB1",
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        "cycles_min": 133,
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        "has_call": true,
        "kind": "loop_with_call"
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        "label": "loc_4077",
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        "cycles_min": 49,
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        "start": 16574,
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        "label": "loc_40BE",
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        "back_edge_text": "BNE loc_40BE",
        "instruction_count": 7,
        "cycles_min": 52,
        "cycles_max": 56,
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        "kind": "delay_loop_candidate"
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        "start": 16646,
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        "back_edge_text": "BNE loc_4106",
        "instruction_count": 38,
        "cycles_min": 311,
        "cycles_max": 315,
        "unknown_cycles": 0,
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        "kind": "loop_with_call"
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      {
        "start": 16775,
        "end": 16813,
        "label": "loc_4187",
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        "back_edge_text": "SCB/F R0, loc_4187",
        "instruction_count": 16,
        "cycles_min": 96,
        "cycles_max": 102,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "counter_loop"
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      {
        "start": 16853,
        "end": 16915,
        "label": "loc_41D5",
        "back_edge": 16915,
        "back_edge_text": "SCB/F R0, loc_41D5",
        "instruction_count": 26,
        "cycles_min": 214,
        "cycles_max": 220,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "counter_loop"
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        "start": 16076,
        "end": 17094,
        "label": "loc_3ECC",
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        "back_edge_text": "BSR loc_3ECC",
        "instruction_count": 305,
        "cycles_min": 2362,
        "cycles_max": 2508,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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        "start": 16076,
        "end": 17148,
        "label": "loc_3ECC",
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        "back_edge_text": "BSR loc_3ECC",
        "instruction_count": 315,
        "cycles_min": 2450,
        "cycles_max": 2596,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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        "start": 16076,
        "end": 17154,
        "label": "loc_3ECC",
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        "back_edge_text": "BSR loc_3ECC",
        "instruction_count": 317,
        "cycles_min": 2466,
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        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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        "start": 16076,
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        "label": "loc_3ECC",
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        "back_edge_text": "BSR loc_3ECC",
        "instruction_count": 319,
        "cycles_min": 2482,
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        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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        "start": 16076,
        "end": 17194,
        "label": "loc_3ECC",
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        "back_edge_text": "BSR loc_3ECC",
        "instruction_count": 329,
        "cycles_min": 2571,
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        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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        "start": 16076,
        "end": 17203,
        "label": "loc_3ECC",
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        "back_edge_text": "BSR loc_3ECC",
        "instruction_count": 332,
        "cycles_min": 2591,
        "cycles_max": 2737,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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      {
        "start": 16076,
        "end": 17212,
        "label": "loc_3ECC",
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        "back_edge_text": "BSR loc_3ECC",
        "instruction_count": 335,
        "cycles_min": 2610,
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        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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      {
        "start": 16076,
        "end": 17221,
        "label": "loc_3ECC",
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        "back_edge_text": "BSR loc_3ECC",
        "instruction_count": 338,
        "cycles_min": 2630,
        "cycles_max": 2776,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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        "start": 4302,
        "end": 17224,
        "label": "loc_10CE",
        "back_edge": 17224,
        "back_edge_text": "BSR loc_10CE",
        "instruction_count": 1629,
        "cycles_min": 10922,
        "cycles_max": 11937,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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        "start": 6562,
        "end": 17354,
        "label": "loc_19A2",
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        "back_edge_text": "BSR loc_19A2",
        "instruction_count": 1147,
        "cycles_min": 7631,
        "cycles_max": 8356,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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      {
        "start": 6709,
        "end": 17366,
        "label": "loc_1A35",
        "back_edge": 17366,
        "back_edge_text": "BSR loc_1A35",
        "instruction_count": 1107,
        "cycles_min": 7458,
        "cycles_max": 8150,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6812,
        "end": 17378,
        "label": "loc_1A9C",
        "back_edge": 17378,
        "back_edge_text": "BSR loc_1A9C",
        "instruction_count": 1068,
        "cycles_min": 7288,
        "cycles_max": 7935,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6884,
        "end": 17390,
        "label": "loc_1AE4",
        "back_edge": 17390,
        "back_edge_text": "BSR loc_1AE4",
        "instruction_count": 1045,
        "cycles_min": 7186,
        "cycles_max": 7815,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6923,
        "end": 17402,
        "label": "loc_1B0B",
        "back_edge": 17402,
        "back_edge_text": "BSR loc_1B0B",
        "instruction_count": 1034,
        "cycles_min": 7146,
        "cycles_max": 7766,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6562,
        "end": 17549,
        "label": "loc_19A2",
        "back_edge": 17549,
        "back_edge_text": "BSR loc_19A2",
        "instruction_count": 1218,
        "cycles_min": 8096,
        "cycles_max": 8894,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
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      {
        "start": 6709,
        "end": 17561,
        "label": "loc_1A35",
        "back_edge": 17561,
        "back_edge_text": "BSR loc_1A35",
        "instruction_count": 1178,
        "cycles_min": 7922,
        "cycles_max": 8688,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6812,
        "end": 17573,
        "label": "loc_1A9C",
        "back_edge": 17573,
        "back_edge_text": "BSR loc_1A9C",
        "instruction_count": 1139,
        "cycles_min": 7751,
        "cycles_max": 8473,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6884,
        "end": 17585,
        "label": "loc_1AE4",
        "back_edge": 17585,
        "back_edge_text": "BSR loc_1AE4",
        "instruction_count": 1116,
        "cycles_min": 7648,
        "cycles_max": 8353,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6923,
        "end": 17597,
        "label": "loc_1B0B",
        "back_edge": 17597,
        "back_edge_text": "BSR loc_1B0B",
        "instruction_count": 1105,
        "cycles_min": 7607,
        "cycles_max": 8304,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6562,
        "end": 17744,
        "label": "loc_19A2",
        "back_edge": 17744,
        "back_edge_text": "BSR loc_19A2",
        "instruction_count": 1289,
        "cycles_min": 8560,
        "cycles_max": 9429,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6709,
        "end": 17756,
        "label": "loc_1A35",
        "back_edge": 17756,
        "back_edge_text": "BSR loc_1A35",
        "instruction_count": 1249,
        "cycles_min": 8387,
        "cycles_max": 9223,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6812,
        "end": 17768,
        "label": "loc_1A9C",
        "back_edge": 17768,
        "back_edge_text": "BSR loc_1A9C",
        "instruction_count": 1210,
        "cycles_min": 8217,
        "cycles_max": 9008,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6884,
        "end": 17780,
        "label": "loc_1AE4",
        "back_edge": 17780,
        "back_edge_text": "BSR loc_1AE4",
        "instruction_count": 1187,
        "cycles_min": 8115,
        "cycles_max": 8888,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 6923,
        "end": 17792,
        "label": "loc_1B0B",
        "back_edge": 17792,
        "back_edge_text": "BSR loc_1B0B",
        "instruction_count": 1176,
        "cycles_min": 8075,
        "cycles_max": 8839,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 15956,
        "end": 18726,
        "label": "loc_3E54",
        "back_edge": 18726,
        "back_edge_text": "BSR loc_3E54",
        "instruction_count": 634,
        "cycles_min": 4572,
        "cycles_max": 4982,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 47654,
        "end": 47658,
        "label": "loc_BA26",
        "back_edge": 47658,
        "back_edge_text": "BNE loc_BA26",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "has_call": false,
        "kind": "delay_loop_candidate"
      },
      {
        "start": 47720,
        "end": 47724,
        "label": "loc_BA68",
        "back_edge": 47724,
        "back_edge_text": "BEQ loc_BA68",
        "instruction_count": 2,
        "cycles_min": 10,
        "cycles_max": 14,
        "unknown_cycles": 0,
        "has_call": false,
        "kind": "delay_loop_candidate"
      },
      {
        "start": 25094,
        "end": 47886,
        "label": "loc_6206",
        "back_edge": 47886,
        "back_edge_text": "BSR loc_6206",
        "instruction_count": 110,
        "cycles_min": 630,
        "cycles_max": 704,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 47654,
        "end": 47939,
        "label": "loc_BA26",
        "back_edge": 47939,
        "back_edge_text": "BSR loc_BA26",
        "instruction_count": 87,
        "cycles_min": 548,
        "cycles_max": 584,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 25131,
        "end": 48129,
        "label": "loc_622B",
        "back_edge": 48129,
        "back_edge_text": "BSR loc_622B",
        "instruction_count": 169,
        "cycles_min": 1021,
        "cycles_max": 1112,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 48149,
        "end": 48231,
        "label": "loc_BC15",
        "back_edge": 48231,
        "back_edge_text": "BRA loc_BC15",
        "instruction_count": 30,
        "cycles_min": 124,
        "cycles_max": 176,
        "unknown_cycles": 0,
        "has_call": false,
        "kind": "unconditional_loop"
      },
      {
        "start": 47654,
        "end": 48333,
        "label": "loc_BA26",
        "back_edge": 48333,
        "back_edge_text": "BSR loc_BA26",
        "instruction_count": 207,
        "cycles_min": 1264,
        "cycles_max": 1393,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 47654,
        "end": 48378,
        "label": "loc_BA26",
        "back_edge": 48378,
        "back_edge_text": "BSR loc_BA26",
        "instruction_count": 219,
        "cycles_min": 1354,
        "cycles_max": 1483,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 47654,
        "end": 48674,
        "label": "loc_BA26",
        "back_edge": 48674,
        "back_edge_text": "BSR loc_BA26",
        "instruction_count": 313,
        "cycles_min": 1938,
        "cycles_max": 2140,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 47654,
        "end": 48746,
        "label": "loc_BA26",
        "back_edge": 48746,
        "back_edge_text": "BSR loc_BA26",
        "instruction_count": 333,
        "cycles_min": 2085,
        "cycles_max": 2296,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 48768,
        "end": 48783,
        "label": "loc_BE80",
        "back_edge": 48783,
        "back_edge_text": "BRA loc_BE80",
        "instruction_count": 7,
        "cycles_min": 30,
        "cycles_max": 38,
        "unknown_cycles": 0,
        "has_call": false,
        "kind": "unconditional_loop"
      },
      {
        "start": 47654,
        "end": 48853,
        "label": "loc_BA26",
        "back_edge": 48853,
        "back_edge_text": "BSR loc_BA26",
        "instruction_count": 369,
        "cycles_min": 2304,
        "cycles_max": 2543,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 18671,
        "end": 49000,
        "label": "loc_48EF",
        "back_edge": 49000,
        "back_edge_text": "BSR loc_48EF",
        "instruction_count": 479,
        "cycles_min": 2952,
        "cycles_max": 3296,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 49125,
        "end": 49143,
        "label": "loc_BFE5",
        "back_edge": 49143,
        "back_edge_text": "BRA loc_BFE5",
        "instruction_count": 9,
        "cycles_min": 57,
        "cycles_max": 67,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 49170,
        "end": 49183,
        "label": "loc_C012",
        "back_edge": 49183,
        "back_edge_text": "BEQ loc_C012",
        "instruction_count": 6,
        "cycles_min": 42,
        "cycles_max": 51,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 49170,
        "end": 49189,
        "label": "loc_C012",
        "back_edge": 49189,
        "back_edge_text": "BEQ loc_C012",
        "instruction_count": 9,
        "cycles_min": 61,
        "cycles_max": 75,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 49170,
        "end": 49197,
        "label": "loc_C012",
        "back_edge": 49197,
        "back_edge_text": "BEQ loc_C012",
        "instruction_count": 13,
        "cycles_min": 84,
        "cycles_max": 103,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 49170,
        "end": 49203,
        "label": "loc_C012",
        "back_edge": 49203,
        "back_edge_text": "BEQ loc_C012",
        "instruction_count": 16,
        "cycles_min": 103,
        "cycles_max": 127,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 49211,
        "end": 49224,
        "label": "loc_C03B",
        "back_edge": 49224,
        "back_edge_text": "BEQ loc_C03B",
        "instruction_count": 6,
        "cycles_min": 41,
        "cycles_max": 50,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 49211,
        "end": 49230,
        "label": "loc_C03B",
        "back_edge": 49230,
        "back_edge_text": "BEQ loc_C03B",
        "instruction_count": 9,
        "cycles_min": 59,
        "cycles_max": 72,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 49211,
        "end": 49241,
        "label": "loc_C03B",
        "back_edge": 49241,
        "back_edge_text": "BEQ loc_C03B",
        "instruction_count": 14,
        "cycles_min": 93,
        "cycles_max": 111,
        "unknown_cycles": 0,
        "has_call": true,
        "kind": "loop_with_call"
      },
      {
        "start": 49294,
        "end": 49324,
        "label": "loc_C08E",
        "back_edge": 49324,
        "back_edge_text": "SCB/F R1, loc_C08E",
        "instruction_count": 10,
        "cycles_min": 69,
        "cycles_max": 78,
        "unknown_cycles": 0,
        "has_call": false,
        "kind": "counter_delay_loop"
      },
      {
        "start": 49379,
        "end": 49411,
        "label": "loc_C0E3",
        "back_edge": 49411,
        "back_edge_text": "SCB/F R1, loc_C0E3",
        "instruction_count": 11,
        "cycles_min": 64,
        "cycles_max": 75,
        "unknown_cycles": 0,
        "has_call": false,
        "kind": "counter_delay_loop"
      }
    ]
  },
  "sci": {
    "clock_hz": null,
    "formulas": {
      "async": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
      "sync": "B = clock_hz / (8 * 2^(2n) * (N + 1))"
    },
    "manual_references": [
      "Manual/0900766b802125d0.md:15837 SMR selects SCI mode and CKS1/CKS0 internal clock source",
      "Manual/0900766b802125d0.md:16027 SCR.CKE1 selects internal or external clock source",
      "Manual/0900766b802125d0.md:16177 BRR and SMR.CKS determine the baud-rate generator",
      "Manual/0900766b802125d0.md:16303 asynchronous BRR formula",
      "Manual/0900766b802125d0.md:16379 synchronous BRR formula",
      "Manual/0900766b802125d0.md:16410 SCI clock source selection tables"
    ],
    "channels": {
      "SCI1": {
        "writes": [
          {
            "address": 4245,
            "instruction": "MOV:G.B #H'24, @SCI1_SMR",
            "channel": "SCI1",
            "register": "SMR",
            "register_address": 65240,
            "operation": "MOV:G",
            "value": 36,
            "value_hex": "H'24"
          },
          {
            "address": 4250,
            "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "MOV:G",
            "value": 60,
            "value_hex": "H'3C"
          },
          {
            "address": 4255,
            "instruction": "MOV:G.B #H'07, @SCI1_BRR",
            "channel": "SCI1",
            "register": "BRR",
            "register_address": 65241,
            "operation": "MOV:G",
            "value": 7,
            "value_hex": "H'07"
          },
          {
            "address": 17258,
            "instruction": "BSET.B #6, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "BSET",
            "value": 124,
            "value_hex": "H'7C"
          },
          {
            "address": 47743,
            "instruction": "BSET.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "BSET",
            "value": 252,
            "value_hex": "H'FC"
          },
          {
            "address": 47774,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "BCLR",
            "value": 124,
            "value_hex": "H'7C"
          },
          {
            "address": 47818,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "BCLR",
            "value": 124,
            "value_hex": "H'7C"
          }
        ],
        "configurations": [
          {
            "channel": "SCI1",
            "mode": "async",
            "mode_summary": "async 8-bit even parity 1 stop",
            "smr": 36,
            "smr_hex": "H'24",
            "brr": 7,
            "brr_hex": "H'07",
            "scr": 60,
            "scr_hex": "H'3C",
            "cks_n": 0,
            "cks_divisor": 1,
            "denominator": 512,
            "clock_source": "internal",
            "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
            "baud_bps": null,
            "confidence": "partial",
            "reason": "clock_hz_missing",
            "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz",
            "address": 4255,
            "instruction": "MOV:G.B #H'07, @SCI1_BRR"
          }
        ]
      },
      "SCI2": {
        "writes": [
          {
            "address": 4260,
            "instruction": "MOV:G.B #H'24, @SCI2_SMR",
            "channel": "SCI2",
            "register": "SMR",
            "register_address": 65264,
            "operation": "MOV:G",
            "value": 36,
            "value_hex": "H'24"
          },
          {
            "address": 4265,
            "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
            "channel": "SCI2",
            "register": "SCR",
            "register_address": 65266,
            "operation": "MOV:G",
            "value": 12,
            "value_hex": "H'0C"
          },
          {
            "address": 4270,
            "instruction": "MOV:G.B #H'07, @SCI2_BRR",
            "channel": "SCI2",
            "register": "BRR",
            "register_address": 65265,
            "operation": "MOV:G",
            "value": 7,
            "value_hex": "H'07"
          }
        ],
        "configurations": [
          {
            "channel": "SCI2",
            "mode": "async",
            "mode_summary": "async 8-bit even parity 1 stop",
            "smr": 36,
            "smr_hex": "H'24",
            "brr": 7,
            "brr_hex": "H'07",
            "scr": 12,
            "scr_hex": "H'0C",
            "cks_n": 0,
            "cks_divisor": 1,
            "denominator": 512,
            "clock_source": "internal",
            "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
            "baud_bps": null,
            "confidence": "partial",
            "reason": "clock_hz_missing",
            "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz",
            "address": 4270,
            "instruction": "MOV:G.B #H'07, @SCI2_BRR"
          }
        ]
      }
    }
  },
  "sci_protocol": {
    "manual_references": [
      "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
      "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
      "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
      "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
      "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
      "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
      "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
      "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
      "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
      "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
      "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
      "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
      "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
    ],
    "channels": {
      "SCI1": {
        "events": [
          {
            "address": 4250,
            "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
            "action": "disable_tx_interrupt",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "register_address_hex": "H'FEDA",
            "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 7,
            "bit_name": "TIE",
            "enabled": false,
            "interrupt_source": "TXI",
            "value": 60
          },
          {
            "address": 4250,
            "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
            "action": "disable_rx_eri_interrupts",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "register_address_hex": "H'FEDA",
            "comment": "disable SCI1 receive and receive-error interrupts (RIE)",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 6,
            "bit_name": "RIE",
            "enabled": false,
            "interrupt_source": "RXI and ERI",
            "value": 60
          },
          {
            "address": 4250,
            "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
            "action": "enable_transmitter",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "register_address_hex": "H'FEDA",
            "comment": "enable SCI1 transmitter (TE)",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 5,
            "bit_name": "TE",
            "enabled": true,
            "interrupt_source": "TXD output",
            "value": 60
          },
          {
            "address": 4250,
            "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
            "action": "enable_receiver",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "register_address_hex": "H'FEDA",
            "comment": "enable SCI1 receiver (RE)",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 4,
            "bit_name": "RE",
            "enabled": true,
            "interrupt_source": "RXD input",
            "value": 60
          },
          {
            "address": 17258,
            "instruction": "BSET.B #6, @SCI1_SCR",
            "action": "enable_rx_eri_interrupts",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "register_address_hex": "H'FEDA",
            "comment": "enable SCI1 receive and receive-error interrupts (RIE)",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 6,
            "bit_name": "RIE",
            "enabled": true,
            "interrupt_source": "RXI and ERI"
          },
          {
            "address": 47720,
            "instruction": "BTST.B #7, @SCI1_SSR",
            "action": "wait_for_tdre",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "register_address_hex": "H'FEDC",
            "comment": "wait for SCI1 transmit data register empty (TDRE=1)",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 7,
            "flag": "TDRE",
            "branch_address": 47724,
            "branch_target": 47720
          },
          {
            "address": 47724,
            "instruction": "BEQ loc_BA68",
            "action": "tdre_wait_branch",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "register_address_hex": "H'FEDC",
            "comment": "repeat SCI1 transmit-empty wait while TDRE=0",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 7,
            "flag": "TDRE",
            "test_address": 47720,
            "branch_target": 47720
          },
          {
            "address": 47730,
            "instruction": "MOV:G.B R0, @SCI1_TDR",
            "action": "write_tdr",
            "channel": "SCI1",
            "register": "TDR",
            "register_address": 65243,
            "register_address_hex": "H'FEDB",
            "comment": "write RS232/SCI byte to SCI1 TDR for transmission",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ]
          },
          {
            "address": 47739,
            "instruction": "BCLR.B #7, @SCI1_SSR",
            "action": "clear_tdre",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "register_address_hex": "H'FEDC",
            "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 7,
            "flag": "TDRE",
            "description": "transmit data register empty"
          },
          {
            "address": 47743,
            "instruction": "BSET.B #7, @SCI1_SCR",
            "action": "enable_tx_interrupt",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "register_address_hex": "H'FEDA",
            "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 7,
            "bit_name": "TIE",
            "enabled": true,
            "interrupt_source": "TXI"
          },
          {
            "address": 47774,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "action": "disable_tx_interrupt",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "register_address_hex": "H'FEDA",
            "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 7,
            "bit_name": "TIE",
            "enabled": false,
            "interrupt_source": "TXI"
          },
          {
            "address": 47797,
            "instruction": "MOV:G.B R0, @SCI1_TDR",
            "action": "write_tdr",
            "channel": "SCI1",
            "register": "TDR",
            "register_address": 65243,
            "register_address_hex": "H'FEDB",
            "comment": "write RS232/SCI byte to SCI1 TDR for transmission",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ]
          },
          {
            "address": 47803,
            "instruction": "BCLR.B #7, @SCI1_SSR",
            "action": "clear_tdre",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "register_address_hex": "H'FEDC",
            "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 7,
            "flag": "TDRE",
            "description": "transmit data register empty"
          },
          {
            "address": 47818,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "action": "disable_tx_interrupt",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "register_address_hex": "H'FEDA",
            "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 7,
            "bit_name": "TIE",
            "enabled": false,
            "interrupt_source": "TXI"
          },
          {
            "address": 47963,
            "instruction": "BCLR.B #5, @SCI1_SSR",
            "action": "clear_orer",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "register_address_hex": "H'FEDC",
            "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 5,
            "flag": "ORER",
            "description": "overrun error"
          },
          {
            "address": 47967,
            "instruction": "BCLR.B #4, @SCI1_SSR",
            "action": "clear_fer",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "register_address_hex": "H'FEDC",
            "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 4,
            "flag": "FER",
            "description": "framing error"
          },
          {
            "address": 47971,
            "instruction": "BCLR.B #3, @SCI1_SSR",
            "action": "clear_per",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "register_address_hex": "H'FEDC",
            "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 3,
            "flag": "PER",
            "description": "parity error"
          },
          {
            "address": 47977,
            "instruction": "BCLR.B #6, @SCI1_SSR",
            "action": "clear_rdrf",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "register_address_hex": "H'FEDC",
            "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 6,
            "flag": "RDRF",
            "description": "receive-data-full"
          },
          {
            "address": 47981,
            "instruction": "MOV:G.B @SCI1_RDR, R0",
            "action": "read_rdr",
            "channel": "SCI1",
            "register": "RDR",
            "register_address": 65245,
            "register_address_hex": "H'FEDD",
            "comment": "read SCI1 received byte from RDR",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ]
          }
        ]
      },
      "SCI2": {
        "events": [
          {
            "address": 4265,
            "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
            "action": "disable_tx_interrupt",
            "channel": "SCI2",
            "register": "SCR",
            "register_address": 65266,
            "register_address_hex": "H'FEF2",
            "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 7,
            "bit_name": "TIE",
            "enabled": false,
            "interrupt_source": "TXI",
            "value": 12
          },
          {
            "address": 4265,
            "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
            "action": "disable_rx_eri_interrupts",
            "channel": "SCI2",
            "register": "SCR",
            "register_address": 65266,
            "register_address_hex": "H'FEF2",
            "comment": "disable SCI2 receive and receive-error interrupts (RIE)",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 6,
            "bit_name": "RIE",
            "enabled": false,
            "interrupt_source": "RXI and ERI",
            "value": 12
          },
          {
            "address": 4265,
            "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
            "action": "disable_transmitter",
            "channel": "SCI2",
            "register": "SCR",
            "register_address": 65266,
            "register_address_hex": "H'FEF2",
            "comment": "disable SCI2 transmitter (TE)",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 5,
            "bit_name": "TE",
            "enabled": false,
            "interrupt_source": "TXD output",
            "value": 12
          },
          {
            "address": 4265,
            "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
            "action": "disable_receiver",
            "channel": "SCI2",
            "register": "SCR",
            "register_address": 65266,
            "register_address_hex": "H'FEF2",
            "comment": "disable SCI2 receiver (RE)",
            "manual": [
              "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
              "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
              "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
              "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
              "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
              "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
              "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
              "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
              "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
              "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
              "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
              "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
              "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
            ],
            "bit": 4,
            "bit_name": "RE",
            "enabled": false,
            "interrupt_source": "RXD input",
            "value": 12
          }
        ]
      }
    },
    "events": [
      {
        "address": 4250,
        "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
        "action": "disable_tx_interrupt",
        "channel": "SCI1",
        "register": "SCR",
        "register_address": 65242,
        "register_address_hex": "H'FEDA",
        "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 7,
        "bit_name": "TIE",
        "enabled": false,
        "interrupt_source": "TXI",
        "value": 60
      },
      {
        "address": 4250,
        "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
        "action": "disable_rx_eri_interrupts",
        "channel": "SCI1",
        "register": "SCR",
        "register_address": 65242,
        "register_address_hex": "H'FEDA",
        "comment": "disable SCI1 receive and receive-error interrupts (RIE)",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 6,
        "bit_name": "RIE",
        "enabled": false,
        "interrupt_source": "RXI and ERI",
        "value": 60
      },
      {
        "address": 4250,
        "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
        "action": "enable_transmitter",
        "channel": "SCI1",
        "register": "SCR",
        "register_address": 65242,
        "register_address_hex": "H'FEDA",
        "comment": "enable SCI1 transmitter (TE)",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 5,
        "bit_name": "TE",
        "enabled": true,
        "interrupt_source": "TXD output",
        "value": 60
      },
      {
        "address": 4250,
        "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
        "action": "enable_receiver",
        "channel": "SCI1",
        "register": "SCR",
        "register_address": 65242,
        "register_address_hex": "H'FEDA",
        "comment": "enable SCI1 receiver (RE)",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 4,
        "bit_name": "RE",
        "enabled": true,
        "interrupt_source": "RXD input",
        "value": 60
      },
      {
        "address": 4265,
        "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
        "action": "disable_tx_interrupt",
        "channel": "SCI2",
        "register": "SCR",
        "register_address": 65266,
        "register_address_hex": "H'FEF2",
        "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 7,
        "bit_name": "TIE",
        "enabled": false,
        "interrupt_source": "TXI",
        "value": 12
      },
      {
        "address": 4265,
        "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
        "action": "disable_rx_eri_interrupts",
        "channel": "SCI2",
        "register": "SCR",
        "register_address": 65266,
        "register_address_hex": "H'FEF2",
        "comment": "disable SCI2 receive and receive-error interrupts (RIE)",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 6,
        "bit_name": "RIE",
        "enabled": false,
        "interrupt_source": "RXI and ERI",
        "value": 12
      },
      {
        "address": 4265,
        "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
        "action": "disable_transmitter",
        "channel": "SCI2",
        "register": "SCR",
        "register_address": 65266,
        "register_address_hex": "H'FEF2",
        "comment": "disable SCI2 transmitter (TE)",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 5,
        "bit_name": "TE",
        "enabled": false,
        "interrupt_source": "TXD output",
        "value": 12
      },
      {
        "address": 4265,
        "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
        "action": "disable_receiver",
        "channel": "SCI2",
        "register": "SCR",
        "register_address": 65266,
        "register_address_hex": "H'FEF2",
        "comment": "disable SCI2 receiver (RE)",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 4,
        "bit_name": "RE",
        "enabled": false,
        "interrupt_source": "RXD input",
        "value": 12
      },
      {
        "address": 17258,
        "instruction": "BSET.B #6, @SCI1_SCR",
        "action": "enable_rx_eri_interrupts",
        "channel": "SCI1",
        "register": "SCR",
        "register_address": 65242,
        "register_address_hex": "H'FEDA",
        "comment": "enable SCI1 receive and receive-error interrupts (RIE)",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 6,
        "bit_name": "RIE",
        "enabled": true,
        "interrupt_source": "RXI and ERI"
      },
      {
        "address": 47720,
        "instruction": "BTST.B #7, @SCI1_SSR",
        "action": "wait_for_tdre",
        "channel": "SCI1",
        "register": "SSR",
        "register_address": 65244,
        "register_address_hex": "H'FEDC",
        "comment": "wait for SCI1 transmit data register empty (TDRE=1)",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 7,
        "flag": "TDRE",
        "branch_address": 47724,
        "branch_target": 47720
      },
      {
        "address": 47724,
        "instruction": "BEQ loc_BA68",
        "action": "tdre_wait_branch",
        "channel": "SCI1",
        "register": "SSR",
        "register_address": 65244,
        "register_address_hex": "H'FEDC",
        "comment": "repeat SCI1 transmit-empty wait while TDRE=0",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 7,
        "flag": "TDRE",
        "test_address": 47720,
        "branch_target": 47720
      },
      {
        "address": 47730,
        "instruction": "MOV:G.B R0, @SCI1_TDR",
        "action": "write_tdr",
        "channel": "SCI1",
        "register": "TDR",
        "register_address": 65243,
        "register_address_hex": "H'FEDB",
        "comment": "write RS232/SCI byte to SCI1 TDR for transmission",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ]
      },
      {
        "address": 47739,
        "instruction": "BCLR.B #7, @SCI1_SSR",
        "action": "clear_tdre",
        "channel": "SCI1",
        "register": "SSR",
        "register_address": 65244,
        "register_address_hex": "H'FEDC",
        "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 7,
        "flag": "TDRE",
        "description": "transmit data register empty"
      },
      {
        "address": 47743,
        "instruction": "BSET.B #7, @SCI1_SCR",
        "action": "enable_tx_interrupt",
        "channel": "SCI1",
        "register": "SCR",
        "register_address": 65242,
        "register_address_hex": "H'FEDA",
        "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 7,
        "bit_name": "TIE",
        "enabled": true,
        "interrupt_source": "TXI"
      },
      {
        "address": 47774,
        "instruction": "BCLR.B #7, @SCI1_SCR",
        "action": "disable_tx_interrupt",
        "channel": "SCI1",
        "register": "SCR",
        "register_address": 65242,
        "register_address_hex": "H'FEDA",
        "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 7,
        "bit_name": "TIE",
        "enabled": false,
        "interrupt_source": "TXI"
      },
      {
        "address": 47797,
        "instruction": "MOV:G.B R0, @SCI1_TDR",
        "action": "write_tdr",
        "channel": "SCI1",
        "register": "TDR",
        "register_address": 65243,
        "register_address_hex": "H'FEDB",
        "comment": "write RS232/SCI byte to SCI1 TDR for transmission",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ]
      },
      {
        "address": 47803,
        "instruction": "BCLR.B #7, @SCI1_SSR",
        "action": "clear_tdre",
        "channel": "SCI1",
        "register": "SSR",
        "register_address": 65244,
        "register_address_hex": "H'FEDC",
        "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 7,
        "flag": "TDRE",
        "description": "transmit data register empty"
      },
      {
        "address": 47818,
        "instruction": "BCLR.B #7, @SCI1_SCR",
        "action": "disable_tx_interrupt",
        "channel": "SCI1",
        "register": "SCR",
        "register_address": 65242,
        "register_address_hex": "H'FEDA",
        "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 7,
        "bit_name": "TIE",
        "enabled": false,
        "interrupt_source": "TXI"
      },
      {
        "address": 47963,
        "instruction": "BCLR.B #5, @SCI1_SSR",
        "action": "clear_orer",
        "channel": "SCI1",
        "register": "SSR",
        "register_address": 65244,
        "register_address_hex": "H'FEDC",
        "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 5,
        "flag": "ORER",
        "description": "overrun error"
      },
      {
        "address": 47967,
        "instruction": "BCLR.B #4, @SCI1_SSR",
        "action": "clear_fer",
        "channel": "SCI1",
        "register": "SSR",
        "register_address": 65244,
        "register_address_hex": "H'FEDC",
        "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 4,
        "flag": "FER",
        "description": "framing error"
      },
      {
        "address": 47971,
        "instruction": "BCLR.B #3, @SCI1_SSR",
        "action": "clear_per",
        "channel": "SCI1",
        "register": "SSR",
        "register_address": 65244,
        "register_address_hex": "H'FEDC",
        "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 3,
        "flag": "PER",
        "description": "parity error"
      },
      {
        "address": 47977,
        "instruction": "BCLR.B #6, @SCI1_SSR",
        "action": "clear_rdrf",
        "channel": "SCI1",
        "register": "SSR",
        "register_address": 65244,
        "register_address_hex": "H'FEDC",
        "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ],
        "bit": 6,
        "flag": "RDRF",
        "description": "receive-data-full"
      },
      {
        "address": 47981,
        "instruction": "MOV:G.B @SCI1_RDR, R0",
        "action": "read_rdr",
        "channel": "SCI1",
        "register": "RDR",
        "register_address": 65245,
        "register_address_hex": "H'FEDD",
        "comment": "read SCI1 received byte from RDR",
        "manual": [
          "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
          "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
          "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
          "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
          "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
          "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
          "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
          "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
          "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
          "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
          "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
          "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
          "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
        ]
      }
    ]
  },
  "serial_reconstruction": {
    "kind": "serial_reconstruction",
    "candidates": [
      {
        "id": "sci1_tx_frame_f858_len6_candidate",
        "kind": "candidate_sci1_tx_frame",
        "channel": "SCI1",
        "frame_length": 6,
        "buffer_start": 63576,
        "buffer_start_hex": "H'F858",
        "buffer_end": 63581,
        "buffer_end_hex": "H'F85D",
        "checksum_address": 63581,
        "checksum_address_hex": "H'F85D",
        "tx_index_address": 63938,
        "tx_index_address_hex": "H'F9C2",
        "tdr_address": 65243,
        "tdr_address_hex": "H'FEDB",
        "checksum_seed": 90,
        "checksum_seed_hex": "H'005A",
        "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4",
        "roles": [
          {
            "name": "tx_frame",
            "address": 63576,
            "address_hex": "H'F858",
            "end_address": 63581,
            "end_address_hex": "H'F85D",
            "summary": "evidence-supported candidate SCI1 TX frame buffer"
          },
          {
            "name": "tx_checksum",
            "address": 63581,
            "address_hex": "H'F85D",
            "checksum_seed": 90,
            "checksum_seed_hex": "H'005A",
            "summary": "evidence-supported candidate SCI1 TX XOR checksum byte"
          },
          {
            "name": "tx_index",
            "address": 63938,
            "address_hex": "H'F9C2",
            "summary": "evidence-supported candidate SCI1 TX frame index"
          }
        ],
        "tx_path": {
          "kind": "interrupt_driven_txi",
          "initial_tdr_write_address": 47730,
          "initial_tdr_write_address_hex": "H'BA72",
          "txi_indexed_tdr_write_address": 47797,
          "txi_indexed_tdr_write_address_hex": "H'BAB5",
          "summary": "initial byte is written from the TX frame buffer, then subsequent bytes are sent by the TXI path when TDRE is reasserted",
          "tdre_caveat": "TDRE reassertion is hardware/emulator timing context; static evidence is the indexed TXI send path."
        },
        "confidence": "high",
        "confidence_score": 0.95,
        "confidence_reason": "all required independent evidence groups were observed",
        "required_evidence_count": 9,
        "observed_evidence_count": 9,
        "missing_evidence": [],
        "evidence_addresses": {
          "tx_buffer_region": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "tx_checksum_seed": [
            47694
          ],
          "checksum_byte": [
            47716
          ],
          "xor_checksum_chain": [
            47696,
            47700,
            47704,
            47708,
            47712,
            47716
          ],
          "initial_send_from_buffer_start": [
            47726,
            47730
          ],
          "tx_index_initialized_to_one": [
            47734
          ],
          "tx_isr_indexed_send": [
            47787,
            47793,
            47797
          ],
          "tx_index_increment": [
            47807
          ],
          "tx_index_compare_frame_length": [
            47811
          ]
        },
        "evidence_addresses_hex": {
          "tx_buffer_region": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "tx_checksum_seed": [
            "H'BA4E"
          ],
          "checksum_byte": [
            "H'BA64"
          ],
          "xor_checksum_chain": [
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64"
          ],
          "initial_send_from_buffer_start": [
            "H'BA6E",
            "H'BA72"
          ],
          "tx_index_initialized_to_one": [
            "H'BA76"
          ],
          "tx_isr_indexed_send": [
            "H'BAAB",
            "H'BAB1",
            "H'BAB5"
          ],
          "tx_index_increment": [
            "H'BABF"
          ],
          "tx_index_compare_frame_length": [
            "H'BAC3"
          ]
        },
        "evidence": [
          {
            "kind": "tx_buffer_region",
            "summary": "TX buffer-region references cluster around H'F858-H'F85D",
            "addresses": [
              47674,
              47682,
              47690,
              47696,
              47700,
              47704,
              47708,
              47712,
              47716,
              47726,
              48645,
              48653,
              48661
            ],
            "addresses_hex": [
              "H'BA3A",
              "H'BA42",
              "H'BA4A",
              "H'BA50",
              "H'BA54",
              "H'BA58",
              "H'BA5C",
              "H'BA60",
              "H'BA64",
              "H'BA6E",
              "H'BE05",
              "H'BE0D",
              "H'BE15"
            ],
            "instructions": [
              "MOV:G.W R0, @H'F858",
              "MOV:G.W R0, @H'F85A",
              "MOV:G.B R0, @H'F85C",
              "XOR.B @H'F858, R0",
              "XOR.B @H'F859, R0",
              "XOR.B @H'F85A, R0",
              "XOR.B @H'F85B, R0",
              "XOR.B @H'F85C, R0",
              "MOV:G.B R0, @H'F85D",
              "MOV:G.B @H'F858, R0",
              "MOV:G.W @H'F858, R0",
              "MOV:G.W @H'F85A, R0",
              "MOV:G.W @H'F85C, R0"
            ],
            "distinct_buffer_addresses": [
              63576,
              63577,
              63578,
              63579,
              63580,
              63581
            ],
            "distinct_buffer_addresses_hex": [
              "H'F858",
              "H'F859",
              "H'F85A",
              "H'F85B",
              "H'F85C",
              "H'F85D"
            ]
          },
          {
            "kind": "tx_checksum_seed",
            "summary": "candidate TX checksum starts from seed H'005A",
            "addresses": [
              47694
            ],
            "addresses_hex": [
              "H'BA4E"
            ],
            "instructions": [
              "MOV:E.B #H'5A, R0"
            ]
          },
          {
            "kind": "checksum_byte",
            "summary": "candidate checksum byte write targets H'F85D",
            "addresses": [
              47716
            ],
            "addresses_hex": [
              "H'BA64"
            ],
            "instructions": [
              "MOV:G.B R0, @H'F85D"
            ]
          },
          {
            "kind": "xor_checksum_chain",
            "summary": "XOR chain appears to feed the H'F85D checksum byte",
            "addresses": [
              47696,
              47700,
              47704,
              47708,
              47712,
              47716
            ],
            "addresses_hex": [
              "H'BA50",
              "H'BA54",
              "H'BA58",
              "H'BA5C",
              "H'BA60",
              "H'BA64"
            ],
            "instructions": [
              "XOR.B @H'F858, R0",
              "XOR.B @H'F859, R0",
              "XOR.B @H'F85A, R0",
              "XOR.B @H'F85B, R0",
              "XOR.B @H'F85C, R0",
              "MOV:G.B R0, @H'F85D"
            ]
          },
          {
            "kind": "initial_send_from_buffer_start",
            "summary": "initial SCI1 TDR send is supported by a read from H'F858",
            "addresses": [
              47726,
              47730
            ],
            "addresses_hex": [
              "H'BA6E",
              "H'BA72"
            ],
            "instructions": [
              "MOV:G.B @H'F858, R0",
              "MOV:G.B R0, @SCI1_TDR"
            ]
          },
          {
            "kind": "tx_index_initialized_to_one",
            "summary": "write evidence supports TX index H'F9C2 being initialized to 1",
            "addresses": [
              47734
            ],
            "addresses_hex": [
              "H'BA76"
            ],
            "instructions": [
              "MOV:G.B #H'01, @H'F9C2"
            ]
          },
          {
            "kind": "tx_isr_indexed_send",
            "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer",
            "addresses": [
              47787,
              47793,
              47797
            ],
            "addresses_hex": [
              "H'BAAB",
              "H'BAB1",
              "H'BAB5"
            ],
            "instructions": [
              "MOV:G.B @H'F9C2, R0",
              "MOV:G.B @(-H'07A8,R0), R0",
              "MOV:G.B R0, @SCI1_TDR"
            ]
          },
          {
            "kind": "tx_index_increment",
            "summary": "candidate TX ISR increments TX index H'F9C2",
            "addresses": [
              47807
            ],
            "addresses_hex": [
              "H'BABF"
            ],
            "instructions": [
              "ADD:Q.B #1, @H'F9C2"
            ]
          },
          {
            "kind": "tx_index_compare_frame_length",
            "summary": "candidate TX ISR compares TX index to frame length 6",
            "addresses": [
              47811
            ],
            "addresses_hex": [
              "H'BAC3"
            ],
            "instructions": [
              "CMP:G.B #H'06, @H'F9C2"
            ]
          }
        ],
        "short_comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A",
        "comment": "candidate/evidence-supported SCI1 6-byte TX frame hypothesis using buffer H'F858-H'F85D with checksum byte H'F85D seeded by H'005A"
      },
      {
        "id": "sci1_rx_frame_f868_len6_candidate",
        "kind": "candidate_sci1_rx_frame",
        "channel": "SCI1",
        "frame_length": 6,
        "capture_buffer_start": 63592,
        "capture_buffer_start_hex": "H'F868",
        "capture_buffer_end": 63597,
        "capture_buffer_end_hex": "H'F86D",
        "validation_buffer_start": 63584,
        "validation_buffer_start_hex": "H'F860",
        "validation_buffer_end": 63589,
        "validation_buffer_end_hex": "H'F865",
        "checksum_address": 63589,
        "checksum_address_hex": "H'F865",
        "rx_index_address": 63939,
        "rx_index_address_hex": "H'F9C3",
        "rdr_address": 65245,
        "rdr_address_hex": "H'FEDD",
        "interbyte_timeout_address": 63937,
        "interbyte_timeout_address_hex": "H'F9C1",
        "complete_timer_address": 63941,
        "complete_timer_address_hex": "H'F9C5",
        "checksum_seed": 90,
        "checksum_seed_hex": "H'005A",
        "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4",
        "confidence": "high",
        "confidence_score": 0.9,
        "confidence_reason": "RX count, copy, and checksum-validation evidence were observed; no explicit header/sync byte was identified",
        "caveat": "candidate frame means six consecutive bytes within the observed RX timing/state machine, not a proven delimited packet",
        "required_evidence_count": 9,
        "observed_evidence_count": 9,
        "optional_evidence_count": 2,
        "missing_evidence": [],
        "evidence_addresses": {
          "rx_rdr_read": [
            47981
          ],
          "rx_indexed_store": [
            48016
          ],
          "rx_index_increment_store": [
            48020,
            48022
          ],
          "rx_isr_compare_frame_length": [
            48026
          ],
          "rx_complete_timer": [
            48030
          ],
          "rx_processor_requires_six_bytes": [
            48043
          ],
          "rx_copy_capture_to_frame_buffer": [
            48051,
            48059,
            48067,
            48055,
            48063,
            48071
          ],
          "rx_checksum_seed": [
            48086
          ],
          "rx_xor_checksum_validation": [
            48086,
            48088,
            48092,
            48096,
            48100,
            48104,
            48108
          ],
          "rx_rdrf_clear_before_rdr_read": [
            47977,
            47981
          ],
          "rx_eri_falls_through_to_rxi": [
            47959,
            47963,
            47967,
            47971,
            47977,
            47981
          ]
        },
        "evidence_addresses_hex": {
          "rx_rdr_read": [
            "H'BB6D"
          ],
          "rx_indexed_store": [
            "H'BB90"
          ],
          "rx_index_increment_store": [
            "H'BB94",
            "H'BB96"
          ],
          "rx_isr_compare_frame_length": [
            "H'BB9A"
          ],
          "rx_complete_timer": [
            "H'BB9E"
          ],
          "rx_processor_requires_six_bytes": [
            "H'BBAB"
          ],
          "rx_copy_capture_to_frame_buffer": [
            "H'BBB3",
            "H'BBBB",
            "H'BBC3",
            "H'BBB7",
            "H'BBBF",
            "H'BBC7"
          ],
          "rx_checksum_seed": [
            "H'BBD6"
          ],
          "rx_xor_checksum_validation": [
            "H'BBD6",
            "H'BBD8",
            "H'BBDC",
            "H'BBE0",
            "H'BBE4",
            "H'BBE8",
            "H'BBEC"
          ],
          "rx_rdrf_clear_before_rdr_read": [
            "H'BB69",
            "H'BB6D"
          ],
          "rx_eri_falls_through_to_rxi": [
            "H'BB57",
            "H'BB5B",
            "H'BB5F",
            "H'BB63",
            "H'BB69",
            "H'BB6D"
          ]
        },
        "evidence": [
          {
            "kind": "rx_rdr_read",
            "summary": "SCI1 RX ISR reads a byte from SCI1_RDR",
            "addresses": [
              47981
            ],
            "addresses_hex": [
              "H'BB6D"
            ],
            "instructions": [
              "MOV:G.B @SCI1_RDR, R0"
            ]
          },
          {
            "kind": "rx_indexed_store",
            "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D",
            "addresses": [
              48016
            ],
            "addresses_hex": [
              "H'BB90"
            ],
            "instructions": [
              "MOV:G.B R0, @(-H'0798,R1)"
            ]
          },
          {
            "kind": "rx_index_increment_store",
            "summary": "RX byte count/index is incremented and stored at H'F9C3",
            "addresses": [
              48020,
              48022
            ],
            "addresses_hex": [
              "H'BB94",
              "H'BB96"
            ],
            "instructions": [
              "ADD:Q.B #1, R1",
              "MOV:G.B R1, @H'F9C3"
            ]
          },
          {
            "kind": "rx_isr_compare_frame_length",
            "summary": "RX ISR compares incremented count to candidate frame length 6",
            "addresses": [
              48026
            ],
            "addresses_hex": [
              "H'BB9A"
            ],
            "instructions": [
              "CMP:E #H'06, R1"
            ]
          },
          {
            "kind": "rx_complete_timer",
            "summary": "RX ISR sets H'F9C5 after count reaches 6",
            "addresses": [
              48030
            ],
            "addresses_hex": [
              "H'BB9E"
            ],
            "instructions": [
              "MOV:G.B #H'14, @H'F9C5"
            ]
          },
          {
            "kind": "rx_processor_requires_six_bytes",
            "summary": "RX processing path requires H'F9C3 to equal 6",
            "addresses": [
              48043
            ],
            "addresses_hex": [
              "H'BBAB"
            ],
            "instructions": [
              "CMP:G.B #H'06, @H'F9C3"
            ]
          },
          {
            "kind": "rx_copy_capture_to_frame_buffer",
            "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865",
            "addresses": [
              48051,
              48059,
              48067,
              48055,
              48063,
              48071
            ],
            "addresses_hex": [
              "H'BBB3",
              "H'BBBB",
              "H'BBC3",
              "H'BBB7",
              "H'BBBF",
              "H'BBC7"
            ],
            "instructions": [
              "MOV:G.W @H'F868, R0",
              "MOV:G.W @H'F86A, R0",
              "MOV:G.W @H'F86C, R0",
              "MOV:G.W R0, @H'F860",
              "MOV:G.W R0, @H'F862",
              "MOV:G.W R0, @H'F864"
            ]
          },
          {
            "kind": "rx_checksum_seed",
            "summary": "candidate RX checksum validation starts from seed H'005A",
            "addresses": [
              48086
            ],
            "addresses_hex": [
              "H'BBD6"
            ],
            "instructions": [
              "MOV:E.B #H'5A, R0"
            ]
          },
          {
            "kind": "rx_xor_checksum_validation",
            "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865",
            "addresses": [
              48086,
              48088,
              48092,
              48096,
              48100,
              48104,
              48108
            ],
            "addresses_hex": [
              "H'BBD6",
              "H'BBD8",
              "H'BBDC",
              "H'BBE0",
              "H'BBE4",
              "H'BBE8",
              "H'BBEC"
            ],
            "instructions": [
              "MOV:E.B #H'5A, R0",
              "XOR.B @H'F860, R0",
              "XOR.B @H'F861, R0",
              "XOR.B @H'F862, R0",
              "XOR.B @H'F863, R0",
              "XOR.B @H'F864, R0",
              "CMP:G.B @H'F865, R0"
            ]
          },
          {
            "kind": "rx_rdrf_clear_before_rdr_read",
            "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence",
            "addresses": [
              47977,
              47981
            ],
            "addresses_hex": [
              "H'BB69",
              "H'BB6D"
            ],
            "instructions": [
              "BCLR.B #6, @SCI1_SSR",
              "MOV:G.B @SCI1_RDR, R0"
            ],
            "manual_references": [
              "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF",
              "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence"
            ]
          },
          {
            "kind": "rx_eri_falls_through_to_rxi",
            "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path",
            "addresses": [
              47959,
              47963,
              47967,
              47971,
              47977,
              47981
            ],
            "addresses_hex": [
              "H'BB57",
              "H'BB5B",
              "H'BB5F",
              "H'BB63",
              "H'BB69",
              "H'BB6D"
            ],
            "instructions": [
              "BSET.B #7, @H'FAA4",
              "BCLR.B #5, @SCI1_SSR",
              "BCLR.B #4, @SCI1_SSR",
              "BCLR.B #3, @SCI1_SSR",
              "BCLR.B #6, @SCI1_SSR",
              "MOV:G.B @SCI1_RDR, R0"
            ],
            "manual_references": [
              "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not",
              "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER"
            ]
          }
        ],
        "rx_error_handling": {
          "kind": "sci1_rx_error_handling_candidate",
          "error_latch_address": 64164,
          "error_latch_address_hex": "H'FAA4",
          "error_latch_bit": 7,
          "fallthrough_to_rx_byte_path": true,
          "rdrf_clear_before_rdr_read": true,
          "summary": "SCI1 ERI appears to mark a physical receive error and continue into the RXI byte-capture path; the RXI path clears RDRF before reading RDR in the ROM order.",
          "manual_caveat": "Manual text distinguishes ORER from FER/PER data transfer into RDR and describes the normal RDR-read then RDRF-clear ordering; this output preserves the observed ROM order.",
          "evidence_addresses": [
            47959,
            47963,
            47967,
            47971,
            47977,
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB57",
            "H'BB5B",
            "H'BB5F",
            "H'BB63",
            "H'BB69",
            "H'BB6D"
          ],
          "confidence": "candidate-medium"
        },
        "short_comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A",
        "comment": "candidate/evidence-supported SCI1 6-byte RX frame hypothesis using capture buffer H'F868-H'F86D; checksum byte H'F865 is validated against XOR seeded by H'005A"
      }
    ],
    "ram_roles": [
      {
        "kind": "candidate_ram_role",
        "name": "post_tx_report_delay",
        "address": 63936,
        "address_hex": "H'F9C0",
        "width_bits": 8,
        "confidence": "candidate/evidence-supported",
        "summary": "post_tx_report_delay at H'F9C0 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it",
        "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol",
        "evidence": [
          {
            "kind": "frt1_ocia_periodic_tick_isr",
            "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
            "addresses": [
              48874
            ],
            "addresses_hex": [
              "H'BEEA"
            ],
            "instructions": [
              "BCLR.B #5, @FRT1_TCSR"
            ],
            "vector_address": 98,
            "vector_address_hex": "H'0062",
            "isr_address": 48874,
            "isr_address_hex": "H'BEEA"
          },
          {
            "kind": "post_tx_report_delay_tick_decrement",
            "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
            "addresses": [
              48878,
              48884
            ],
            "addresses_hex": [
              "H'BEEE",
              "H'BEF4"
            ],
            "instructions": [
              "TST.B @H'F9C0",
              "ADD:Q.B #-1, @H'F9C0"
            ],
            "role_name": "post_tx_report_delay",
            "ram_address": 63936,
            "ram_address_hex": "H'F9C0",
            "width_bits": 8,
            "isr_address": 48874,
            "isr_address_hex": "H'BEEA"
          }
        ],
        "evidence_addresses": {
          "frt1_ocia_periodic_tick_isr": [
            48874
          ],
          "post_tx_report_delay_tick_decrement": [
            48878,
            48884
          ]
        },
        "evidence_addresses_hex": {
          "frt1_ocia_periodic_tick_isr": [
            "H'BEEA"
          ],
          "post_tx_report_delay_tick_decrement": [
            "H'BEEE",
            "H'BEF4"
          ]
        }
      },
      {
        "kind": "candidate_ram_role",
        "name": "secondary_tx_report_delay",
        "address": 63937,
        "address_hex": "H'F9C1",
        "width_bits": 8,
        "confidence": "candidate/evidence-supported",
        "summary": "secondary_tx_report_delay at H'F9C1 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it",
        "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol",
        "evidence": [
          {
            "kind": "frt1_ocia_periodic_tick_isr",
            "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
            "addresses": [
              48874
            ],
            "addresses_hex": [
              "H'BEEA"
            ],
            "instructions": [
              "BCLR.B #5, @FRT1_TCSR"
            ],
            "vector_address": 98,
            "vector_address_hex": "H'0062",
            "isr_address": 48874,
            "isr_address_hex": "H'BEEA"
          },
          {
            "kind": "secondary_tx_report_delay_tick_decrement",
            "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
            "addresses": [
              48888,
              48894
            ],
            "addresses_hex": [
              "H'BEF8",
              "H'BEFE"
            ],
            "instructions": [
              "TST.B @H'F9C1",
              "ADD:Q.B #-1, @H'F9C1"
            ],
            "role_name": "secondary_tx_report_delay",
            "ram_address": 63937,
            "ram_address_hex": "H'F9C1",
            "width_bits": 8,
            "isr_address": 48874,
            "isr_address_hex": "H'BEEA"
          }
        ],
        "evidence_addresses": {
          "frt1_ocia_periodic_tick_isr": [
            48874
          ],
          "secondary_tx_report_delay_tick_decrement": [
            48888,
            48894
          ]
        },
        "evidence_addresses_hex": {
          "frt1_ocia_periodic_tick_isr": [
            "H'BEEA"
          ],
          "secondary_tx_report_delay_tick_decrement": [
            "H'BEF8",
            "H'BEFE"
          ]
        }
      },
      {
        "kind": "candidate_ram_role",
        "name": "periodic_report_countdown",
        "address": 63942,
        "address_hex": "H'F9C6",
        "width_bits": 16,
        "confidence": "candidate/evidence-supported",
        "summary": "periodic_report_countdown at H'F9C6 is a candidate/evidence-supported RAM timer role; FRT1 OCIA tick ISR H'BEEA decrements it",
        "caveat": "role name is evidence-supported from static references plus emulator-guided timer behavior, not a proved firmware symbol",
        "evidence": [
          {
            "kind": "frt1_ocia_periodic_tick_isr",
            "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
            "addresses": [
              48874
            ],
            "addresses_hex": [
              "H'BEEA"
            ],
            "instructions": [
              "BCLR.B #5, @FRT1_TCSR"
            ],
            "vector_address": 98,
            "vector_address_hex": "H'0062",
            "isr_address": 48874,
            "isr_address_hex": "H'BEEA"
          },
          {
            "kind": "periodic_report_countdown_tick_decrement",
            "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR",
            "addresses": [
              48898,
              48904
            ],
            "addresses_hex": [
              "H'BF02",
              "H'BF08"
            ],
            "instructions": [
              "TST.W @H'F9C6",
              "ADD:Q.W #-1, @H'F9C6"
            ],
            "role_name": "periodic_report_countdown",
            "ram_address": 63942,
            "ram_address_hex": "H'F9C6",
            "width_bits": 16,
            "isr_address": 48874,
            "isr_address_hex": "H'BEEA"
          }
        ],
        "evidence_addresses": {
          "frt1_ocia_periodic_tick_isr": [
            48874
          ],
          "periodic_report_countdown_tick_decrement": [
            48898,
            48904
          ]
        },
        "evidence_addresses_hex": {
          "frt1_ocia_periodic_tick_isr": [
            "H'BEEA"
          ],
          "periodic_report_countdown_tick_decrement": [
            "H'BF02",
            "H'BF08"
          ]
        }
      }
    ],
    "evidence": [
      {
        "kind": "tx_buffer_region",
        "summary": "TX buffer-region references cluster around H'F858-H'F85D",
        "addresses": [
          47674,
          47682,
          47690,
          47696,
          47700,
          47704,
          47708,
          47712,
          47716,
          47726,
          48645,
          48653,
          48661
        ],
        "addresses_hex": [
          "H'BA3A",
          "H'BA42",
          "H'BA4A",
          "H'BA50",
          "H'BA54",
          "H'BA58",
          "H'BA5C",
          "H'BA60",
          "H'BA64",
          "H'BA6E",
          "H'BE05",
          "H'BE0D",
          "H'BE15"
        ],
        "instructions": [
          "MOV:G.W R0, @H'F858",
          "MOV:G.W R0, @H'F85A",
          "MOV:G.B R0, @H'F85C",
          "XOR.B @H'F858, R0",
          "XOR.B @H'F859, R0",
          "XOR.B @H'F85A, R0",
          "XOR.B @H'F85B, R0",
          "XOR.B @H'F85C, R0",
          "MOV:G.B R0, @H'F85D",
          "MOV:G.B @H'F858, R0",
          "MOV:G.W @H'F858, R0",
          "MOV:G.W @H'F85A, R0",
          "MOV:G.W @H'F85C, R0"
        ],
        "distinct_buffer_addresses": [
          63576,
          63577,
          63578,
          63579,
          63580,
          63581
        ],
        "distinct_buffer_addresses_hex": [
          "H'F858",
          "H'F859",
          "H'F85A",
          "H'F85B",
          "H'F85C",
          "H'F85D"
        ]
      },
      {
        "kind": "tx_checksum_seed",
        "summary": "candidate TX checksum starts from seed H'005A",
        "addresses": [
          47694
        ],
        "addresses_hex": [
          "H'BA4E"
        ],
        "instructions": [
          "MOV:E.B #H'5A, R0"
        ]
      },
      {
        "kind": "checksum_byte",
        "summary": "candidate checksum byte write targets H'F85D",
        "addresses": [
          47716
        ],
        "addresses_hex": [
          "H'BA64"
        ],
        "instructions": [
          "MOV:G.B R0, @H'F85D"
        ]
      },
      {
        "kind": "xor_checksum_chain",
        "summary": "XOR chain appears to feed the H'F85D checksum byte",
        "addresses": [
          47696,
          47700,
          47704,
          47708,
          47712,
          47716
        ],
        "addresses_hex": [
          "H'BA50",
          "H'BA54",
          "H'BA58",
          "H'BA5C",
          "H'BA60",
          "H'BA64"
        ],
        "instructions": [
          "XOR.B @H'F858, R0",
          "XOR.B @H'F859, R0",
          "XOR.B @H'F85A, R0",
          "XOR.B @H'F85B, R0",
          "XOR.B @H'F85C, R0",
          "MOV:G.B R0, @H'F85D"
        ]
      },
      {
        "kind": "initial_send_from_buffer_start",
        "summary": "initial SCI1 TDR send is supported by a read from H'F858",
        "addresses": [
          47726,
          47730
        ],
        "addresses_hex": [
          "H'BA6E",
          "H'BA72"
        ],
        "instructions": [
          "MOV:G.B @H'F858, R0",
          "MOV:G.B R0, @SCI1_TDR"
        ]
      },
      {
        "kind": "tx_index_initialized_to_one",
        "summary": "write evidence supports TX index H'F9C2 being initialized to 1",
        "addresses": [
          47734
        ],
        "addresses_hex": [
          "H'BA76"
        ],
        "instructions": [
          "MOV:G.B #H'01, @H'F9C2"
        ]
      },
      {
        "kind": "tx_isr_indexed_send",
        "summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer",
        "addresses": [
          47787,
          47793,
          47797
        ],
        "addresses_hex": [
          "H'BAAB",
          "H'BAB1",
          "H'BAB5"
        ],
        "instructions": [
          "MOV:G.B @H'F9C2, R0",
          "MOV:G.B @(-H'07A8,R0), R0",
          "MOV:G.B R0, @SCI1_TDR"
        ]
      },
      {
        "kind": "tx_index_increment",
        "summary": "candidate TX ISR increments TX index H'F9C2",
        "addresses": [
          47807
        ],
        "addresses_hex": [
          "H'BABF"
        ],
        "instructions": [
          "ADD:Q.B #1, @H'F9C2"
        ]
      },
      {
        "kind": "tx_index_compare_frame_length",
        "summary": "candidate TX ISR compares TX index to frame length 6",
        "addresses": [
          47811
        ],
        "addresses_hex": [
          "H'BAC3"
        ],
        "instructions": [
          "CMP:G.B #H'06, @H'F9C2"
        ]
      },
      {
        "kind": "rx_rdr_read",
        "summary": "SCI1 RX ISR reads a byte from SCI1_RDR",
        "addresses": [
          47981
        ],
        "addresses_hex": [
          "H'BB6D"
        ],
        "instructions": [
          "MOV:G.B @SCI1_RDR, R0"
        ]
      },
      {
        "kind": "rx_rdrf_clear_before_rdr_read",
        "summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence",
        "addresses": [
          47977,
          47981
        ],
        "addresses_hex": [
          "H'BB69",
          "H'BB6D"
        ],
        "instructions": [
          "BCLR.B #6, @SCI1_SSR",
          "MOV:G.B @SCI1_RDR, R0"
        ],
        "manual_references": [
          "Manual/0900766b802125d0.md:16652 RDRF clear sequence reads RDR before clearing RDRF",
          "Manual/0900766b802125d0.md:16926 canonical receive flag clear sequence"
        ]
      },
      {
        "kind": "rx_eri_falls_through_to_rxi",
        "summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path",
        "addresses": [
          47959,
          47963,
          47967,
          47971,
          47977,
          47981
        ],
        "addresses_hex": [
          "H'BB57",
          "H'BB5B",
          "H'BB5F",
          "H'BB63",
          "H'BB69",
          "H'BB6D"
        ],
        "instructions": [
          "BSET.B #7, @H'FAA4",
          "BCLR.B #5, @SCI1_SSR",
          "BCLR.B #4, @SCI1_SSR",
          "BCLR.B #3, @SCI1_SSR",
          "BCLR.B #6, @SCI1_SSR",
          "MOV:G.B @SCI1_RDR, R0"
        ],
        "manual_references": [
          "Manual/0900766b802125d0.md:16703 FER/PER transfer errored data to RDR; ORER does not",
          "Manual/0900766b802125d0.md:16936 ERI is requested on ORER, FER, or PER"
        ]
      },
      {
        "kind": "rx_indexed_store",
        "summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D",
        "addresses": [
          48016
        ],
        "addresses_hex": [
          "H'BB90"
        ],
        "instructions": [
          "MOV:G.B R0, @(-H'0798,R1)"
        ]
      },
      {
        "kind": "rx_index_increment_store",
        "summary": "RX byte count/index is incremented and stored at H'F9C3",
        "addresses": [
          48020,
          48022
        ],
        "addresses_hex": [
          "H'BB94",
          "H'BB96"
        ],
        "instructions": [
          "ADD:Q.B #1, R1",
          "MOV:G.B R1, @H'F9C3"
        ]
      },
      {
        "kind": "rx_isr_compare_frame_length",
        "summary": "RX ISR compares incremented count to candidate frame length 6",
        "addresses": [
          48026
        ],
        "addresses_hex": [
          "H'BB9A"
        ],
        "instructions": [
          "CMP:E #H'06, R1"
        ]
      },
      {
        "kind": "rx_complete_timer",
        "summary": "RX ISR sets H'F9C5 after count reaches 6",
        "addresses": [
          48030
        ],
        "addresses_hex": [
          "H'BB9E"
        ],
        "instructions": [
          "MOV:G.B #H'14, @H'F9C5"
        ]
      },
      {
        "kind": "rx_processor_requires_six_bytes",
        "summary": "RX processing path requires H'F9C3 to equal 6",
        "addresses": [
          48043
        ],
        "addresses_hex": [
          "H'BBAB"
        ],
        "instructions": [
          "CMP:G.B #H'06, @H'F9C3"
        ]
      },
      {
        "kind": "rx_copy_capture_to_frame_buffer",
        "summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865",
        "addresses": [
          48051,
          48059,
          48067,
          48055,
          48063,
          48071
        ],
        "addresses_hex": [
          "H'BBB3",
          "H'BBBB",
          "H'BBC3",
          "H'BBB7",
          "H'BBBF",
          "H'BBC7"
        ],
        "instructions": [
          "MOV:G.W @H'F868, R0",
          "MOV:G.W @H'F86A, R0",
          "MOV:G.W @H'F86C, R0",
          "MOV:G.W R0, @H'F860",
          "MOV:G.W R0, @H'F862",
          "MOV:G.W R0, @H'F864"
        ]
      },
      {
        "kind": "rx_checksum_seed",
        "summary": "candidate RX checksum validation starts from seed H'005A",
        "addresses": [
          48086
        ],
        "addresses_hex": [
          "H'BBD6"
        ],
        "instructions": [
          "MOV:E.B #H'5A, R0"
        ]
      },
      {
        "kind": "rx_xor_checksum_validation",
        "summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865",
        "addresses": [
          48086,
          48088,
          48092,
          48096,
          48100,
          48104,
          48108
        ],
        "addresses_hex": [
          "H'BBD6",
          "H'BBD8",
          "H'BBDC",
          "H'BBE0",
          "H'BBE4",
          "H'BBE8",
          "H'BBEC"
        ],
        "instructions": [
          "MOV:E.B #H'5A, R0",
          "XOR.B @H'F860, R0",
          "XOR.B @H'F861, R0",
          "XOR.B @H'F862, R0",
          "XOR.B @H'F863, R0",
          "XOR.B @H'F864, R0",
          "CMP:G.B @H'F865, R0"
        ]
      },
      {
        "kind": "frt1_ocia_periodic_tick_isr",
        "summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
        "addresses": [
          48874
        ],
        "addresses_hex": [
          "H'BEEA"
        ],
        "instructions": [
          "BCLR.B #5, @FRT1_TCSR"
        ],
        "vector_address": 98,
        "vector_address_hex": "H'0062",
        "isr_address": 48874,
        "isr_address_hex": "H'BEEA"
      },
      {
        "kind": "post_tx_report_delay_tick_decrement",
        "summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
        "addresses": [
          48878,
          48884
        ],
        "addresses_hex": [
          "H'BEEE",
          "H'BEF4"
        ],
        "instructions": [
          "TST.B @H'F9C0",
          "ADD:Q.B #-1, @H'F9C0"
        ],
        "role_name": "post_tx_report_delay",
        "ram_address": 63936,
        "ram_address_hex": "H'F9C0",
        "width_bits": 8,
        "isr_address": 48874,
        "isr_address_hex": "H'BEEA"
      },
      {
        "kind": "secondary_tx_report_delay_tick_decrement",
        "summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
        "addresses": [
          48888,
          48894
        ],
        "addresses_hex": [
          "H'BEF8",
          "H'BEFE"
        ],
        "instructions": [
          "TST.B @H'F9C1",
          "ADD:Q.B #-1, @H'F9C1"
        ],
        "role_name": "secondary_tx_report_delay",
        "ram_address": 63937,
        "ram_address_hex": "H'F9C1",
        "width_bits": 8,
        "isr_address": 48874,
        "isr_address_hex": "H'BEEA"
      },
      {
        "kind": "periodic_report_countdown_tick_decrement",
        "summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR",
        "addresses": [
          48898,
          48904
        ],
        "addresses_hex": [
          "H'BF02",
          "H'BF08"
        ],
        "instructions": [
          "TST.W @H'F9C6",
          "ADD:Q.W #-1, @H'F9C6"
        ],
        "role_name": "periodic_report_countdown",
        "ram_address": 63942,
        "ram_address_hex": "H'F9C6",
        "width_bits": 16,
        "isr_address": 48874,
        "isr_address_hex": "H'BEEA"
      }
    ],
    "required_evidence": {
      "tx": [
        "tx_buffer_region",
        "tx_checksum_seed",
        "checksum_byte",
        "xor_checksum_chain",
        "initial_send_from_buffer_start",
        "tx_index_initialized_to_one",
        "tx_isr_indexed_send",
        "tx_index_increment",
        "tx_index_compare_frame_length"
      ],
      "rx": [
        "rx_rdr_read",
        "rx_indexed_store",
        "rx_index_increment_store",
        "rx_isr_compare_frame_length",
        "rx_complete_timer",
        "rx_processor_requires_six_bytes",
        "rx_copy_capture_to_frame_buffer",
        "rx_checksum_seed",
        "rx_xor_checksum_validation"
      ]
    }
  },
  "board_profile": {
    "board": "sony_rcp_tx7",
    "name": "Sony RCP-TX7",
    "summary": "Board trace ties the H8/536 SCI1 pins to a MAX202 RS232 transceiver.",
    "manual_references": [
      "Manual/0900766b802125d0.md:2417 FP-80 H8/536 pin 66 is P95/TXD",
      "Manual/0900766b802125d0.md:2418 FP-80 H8/536 pin 67 is P96/RXD",
      "Manual/0900766b802125d0.md:11192 Port 9 carries SCI1 and SCI2 serial signals",
      "Manual/0900766b802125d0.md:11201 P96 is RXD1 input",
      "Manual/0900766b802125d0.md:11202 P95 is TXD1 output",
      "Manual/0900766b802125d0.md:15725 SCI1 RXD input pin",
      "Manual/0900766b802125d0.md:15726 SCI1 TXD output pin",
      "Manual/0900766b802125d0.md:15750 SCI register table starts with SCI1 RDR/TDR/SMR/SCR/SSR/BRR",
      "Manual/0900766b802125d0.md:15758 SCI register table lists SCI2 RDR/TDR/SMR/SCR/SSR/BRR",
      "Manual/0900766b802125d0.md:15794 RDR receive data register",
      "Manual/0900766b802125d0.md:15823 TDR transmit data register",
      "Manual/0900766b802125d0.md:15969 SCR enables and disables SCI functions",
      "Manual/0900766b802125d0.md:16009 SCR.TE makes the TXD pin output",
      "Manual/0900766b802125d0.md:16029 SCR.RE makes the RXD pin input",
      "Manual/0900766b802125d0.md:16090 SSR contains transmit/receive status flags",
      "Manual/0900766b802125d0.md:10560 SYSCR2 controls port 9 pin functions",
      "Manual/0900766b802125d0.md:10631 SYSCR2.P9SCI2E controls the SCI2 functions of P92-P94"
    ],
    "traces": [
      {
        "channel": "SCI1",
        "signal": "TXD",
        "h8_pin": 66,
        "h8_pin_name": "P95/TXD",
        "h8_function": "TXD1",
        "max202_pin": 11,
        "evidence": "MAX202 pin 11 traces to H8 pin 66"
      },
      {
        "channel": "SCI1",
        "signal": "RXD",
        "h8_pin": 67,
        "h8_pin_name": "P96/RXD",
        "h8_function": "RXD1",
        "max202_pin": 12,
        "evidence": "MAX202 pin 12 traces to H8 pin 67"
      }
    ],
    "channels": {
      "SCI1": {
        "traced_to_max202": true,
        "path": "RS232/MAX202",
        "pins": [
          {
            "channel": "SCI1",
            "signal": "TXD",
            "h8_pin": 66,
            "h8_pin_name": "P95/TXD",
            "h8_function": "TXD1",
            "max202_pin": 11,
            "evidence": "MAX202 pin 11 traces to H8 pin 66"
          },
          {
            "channel": "SCI1",
            "signal": "RXD",
            "h8_pin": 67,
            "h8_pin_name": "P96/RXD",
            "h8_function": "RXD1",
            "max202_pin": 12,
            "evidence": "MAX202 pin 12 traces to H8 pin 67"
          }
        ],
        "scr": {
          "value": 124,
          "value_hex": "H'7C",
          "tie": false,
          "rie": true,
          "tx_enabled": true,
          "rx_enabled": true
        },
        "accesses": [
          {
            "address": 4245,
            "instruction": "MOV:G.B #H'24, @SCI1_SMR",
            "channel": "SCI1",
            "register": "SMR",
            "register_address": 65240,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)",
            "value": 36,
            "value_hex": "H'24"
          },
          {
            "address": 4250,
            "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 60,
            "value_hex": "H'3C",
            "scr": {
              "value": 60,
              "value_hex": "H'3C",
              "tie": false,
              "rie": false,
              "tx_enabled": true,
              "rx_enabled": true
            }
          },
          {
            "address": 4255,
            "instruction": "MOV:G.B #H'07, @SCI1_BRR",
            "channel": "SCI1",
            "register": "BRR",
            "register_address": 65241,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)",
            "value": 7,
            "value_hex": "H'07"
          },
          {
            "address": 17258,
            "instruction": "BSET.B #6, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 124,
            "value_hex": "H'7C",
            "scr": {
              "value": 124,
              "value_hex": "H'7C",
              "tie": false,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          },
          {
            "address": 47720,
            "instruction": "BTST.B #7, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "read",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          },
          {
            "address": 47730,
            "instruction": "MOV:G.B R0, @SCI1_TDR",
            "channel": "SCI1",
            "register": "TDR",
            "register_address": 65243,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
          },
          {
            "address": 47739,
            "instruction": "BCLR.B #7, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          },
          {
            "address": 47743,
            "instruction": "BSET.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 252,
            "value_hex": "H'FC",
            "scr": {
              "value": 252,
              "value_hex": "H'FC",
              "tie": true,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          },
          {
            "address": 47774,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 124,
            "value_hex": "H'7C",
            "scr": {
              "value": 124,
              "value_hex": "H'7C",
              "tie": false,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          },
          {
            "address": 47797,
            "instruction": "MOV:G.B R0, @SCI1_TDR",
            "channel": "SCI1",
            "register": "TDR",
            "register_address": 65243,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
          },
          {
            "address": 47803,
            "instruction": "BCLR.B #7, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          },
          {
            "address": 47818,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 124,
            "value_hex": "H'7C",
            "scr": {
              "value": 124,
              "value_hex": "H'7C",
              "tie": false,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          },
          {
            "address": 47963,
            "instruction": "BCLR.B #5, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          },
          {
            "address": 47967,
            "instruction": "BCLR.B #4, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          },
          {
            "address": 47971,
            "instruction": "BCLR.B #3, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          },
          {
            "address": 47977,
            "instruction": "BCLR.B #6, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          },
          {
            "address": 47981,
            "instruction": "MOV:G.B @SCI1_RDR, R0",
            "channel": "SCI1",
            "register": "RDR",
            "register_address": 65245,
            "access": "read",
            "traced_to_max202": true,
            "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD"
          }
        ]
      },
      "SCI2": {
        "traced_to_max202": false,
        "path": null,
        "note": "Sony RCP-TX7 MAX202 board traces are on SCI1 P95/P96, not SCI2 P92/P93.",
        "p9sci2e": false,
        "scr": {
          "value": 12,
          "value_hex": "H'0C",
          "tie": false,
          "rie": false,
          "tx_enabled": false,
          "rx_enabled": false
        },
        "accesses": [
          {
            "address": 4260,
            "instruction": "MOV:G.B #H'24, @SCI2_SMR",
            "channel": "SCI2",
            "register": "SMR",
            "register_address": 65264,
            "access": "write",
            "traced_to_max202": false,
            "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96",
            "value": 36,
            "value_hex": "H'24",
            "p9sci2e": false
          },
          {
            "address": 4265,
            "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
            "channel": "SCI2",
            "register": "SCR",
            "register_address": 65266,
            "access": "write",
            "traced_to_max202": false,
            "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96",
            "value": 12,
            "value_hex": "H'0C",
            "scr": {
              "value": 12,
              "value_hex": "H'0C",
              "tie": false,
              "rie": false,
              "tx_enabled": false,
              "rx_enabled": false
            },
            "p9sci2e": false
          },
          {
            "address": 4270,
            "instruction": "MOV:G.B #H'07, @SCI2_BRR",
            "channel": "SCI2",
            "register": "BRR",
            "register_address": 65265,
            "access": "write",
            "traced_to_max202": false,
            "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96",
            "value": 7,
            "value_hex": "H'07",
            "p9sci2e": false
          }
        ]
      }
    },
    "instructions": {
      "4148": {
        "accesses": [
          {
            "address": 4148,
            "instruction": "MOV:G.B #H'84, @SYSCR2",
            "register": "SYSCR2",
            "register_address": 65277,
            "access": "write",
            "p9sci2e": false,
            "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96",
            "value": 132,
            "value_hex": "H'84"
          }
        ],
        "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96"
      },
      "4245": {
        "accesses": [
          {
            "address": 4245,
            "instruction": "MOV:G.B #H'24, @SCI1_SMR",
            "channel": "SCI1",
            "register": "SMR",
            "register_address": 65240,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)",
            "value": 36,
            "value_hex": "H'24"
          }
        ],
        "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)"
      },
      "4250": {
        "accesses": [
          {
            "address": 4250,
            "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 60,
            "value_hex": "H'3C",
            "scr": {
              "value": 60,
              "value_hex": "H'3C",
              "tie": false,
              "rie": false,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "4255": {
        "accesses": [
          {
            "address": 4255,
            "instruction": "MOV:G.B #H'07, @SCI1_BRR",
            "channel": "SCI1",
            "register": "BRR",
            "register_address": 65241,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)",
            "value": 7,
            "value_hex": "H'07"
          }
        ],
        "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)"
      },
      "4260": {
        "accesses": [
          {
            "address": 4260,
            "instruction": "MOV:G.B #H'24, @SCI2_SMR",
            "channel": "SCI2",
            "register": "SMR",
            "register_address": 65264,
            "access": "write",
            "traced_to_max202": false,
            "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96",
            "value": 36,
            "value_hex": "H'24",
            "p9sci2e": false
          }
        ],
        "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96"
      },
      "4265": {
        "accesses": [
          {
            "address": 4265,
            "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
            "channel": "SCI2",
            "register": "SCR",
            "register_address": 65266,
            "access": "write",
            "traced_to_max202": false,
            "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96",
            "value": 12,
            "value_hex": "H'0C",
            "scr": {
              "value": 12,
              "value_hex": "H'0C",
              "tie": false,
              "rie": false,
              "tx_enabled": false,
              "rx_enabled": false
            },
            "p9sci2e": false
          }
        ],
        "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96"
      },
      "4270": {
        "accesses": [
          {
            "address": 4270,
            "instruction": "MOV:G.B #H'07, @SCI2_BRR",
            "channel": "SCI2",
            "register": "BRR",
            "register_address": 65265,
            "access": "write",
            "traced_to_max202": false,
            "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96",
            "value": 7,
            "value_hex": "H'07",
            "p9sci2e": false
          }
        ],
        "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96"
      },
      "17258": {
        "accesses": [
          {
            "address": 17258,
            "instruction": "BSET.B #6, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 124,
            "value_hex": "H'7C",
            "scr": {
              "value": 124,
              "value_hex": "H'7C",
              "tie": false,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "17274": {
        "accesses": [
          {
            "address": 17274,
            "instruction": "BSET.B #4, @SYSCR2",
            "register": "SYSCR2",
            "register_address": 65277,
            "access": "write",
            "p9sci2e": false,
            "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96",
            "value": 148,
            "value_hex": "H'94"
          }
        ],
        "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96"
      },
      "17278": {
        "accesses": [
          {
            "address": 17278,
            "instruction": "BSET.B #5, @SYSCR2",
            "register": "SYSCR2",
            "register_address": 65277,
            "access": "write",
            "p9sci2e": false,
            "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96",
            "value": 180,
            "value_hex": "H'B4"
          }
        ],
        "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96"
      },
      "47720": {
        "accesses": [
          {
            "address": 47720,
            "instruction": "BTST.B #7, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "read",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "47730": {
        "accesses": [
          {
            "address": 47730,
            "instruction": "MOV:G.B R0, @SCI1_TDR",
            "channel": "SCI1",
            "register": "TDR",
            "register_address": 65243,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
          }
        ],
        "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
      },
      "47739": {
        "accesses": [
          {
            "address": 47739,
            "instruction": "BCLR.B #7, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "47743": {
        "accesses": [
          {
            "address": 47743,
            "instruction": "BSET.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 252,
            "value_hex": "H'FC",
            "scr": {
              "value": 252,
              "value_hex": "H'FC",
              "tie": true,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "47774": {
        "accesses": [
          {
            "address": 47774,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 124,
            "value_hex": "H'7C",
            "scr": {
              "value": 124,
              "value_hex": "H'7C",
              "tie": false,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "47797": {
        "accesses": [
          {
            "address": 47797,
            "instruction": "MOV:G.B R0, @SCI1_TDR",
            "channel": "SCI1",
            "register": "TDR",
            "register_address": 65243,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
          }
        ],
        "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
      },
      "47803": {
        "accesses": [
          {
            "address": 47803,
            "instruction": "BCLR.B #7, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "47818": {
        "accesses": [
          {
            "address": 47818,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 124,
            "value_hex": "H'7C",
            "scr": {
              "value": 124,
              "value_hex": "H'7C",
              "tie": false,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "47963": {
        "accesses": [
          {
            "address": 47963,
            "instruction": "BCLR.B #5, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "47967": {
        "accesses": [
          {
            "address": 47967,
            "instruction": "BCLR.B #4, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "47971": {
        "accesses": [
          {
            "address": 47971,
            "instruction": "BCLR.B #3, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "47977": {
        "accesses": [
          {
            "address": 47977,
            "instruction": "BCLR.B #6, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "47981": {
        "accesses": [
          {
            "address": 47981,
            "instruction": "MOV:G.B @SCI1_RDR, R0",
            "channel": "SCI1",
            "register": "RDR",
            "register_address": 65245,
            "access": "read",
            "traced_to_max202": true,
            "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD"
          }
        ],
        "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD"
      }
    },
    "state": {
      "SYSCR2": {
        "value": 180,
        "value_hex": "H'B4"
      },
      "P9SCI2E": false
    }
  },
  "peripheral_access": {
    "manual_references": [
      "Manual/0900766b802125d0.md:12185 FRT FRC/OCRA/OCRB/ICR use TEMP for 16-bit CPU access",
      "Manual/0900766b802125d0.md:12193 FRT byte access order is upper byte then lower byte",
      "Manual/0900766b802125d0.md:12212 OCRA/OCRB reads are direct; writes still use TEMP",
      "Manual/0900766b802125d0.md:17546 A/D ADDRA-ADDRD lower byte is accessed through TEMP",
      "Manual/0900766b802125d0.md:17556 A/D full-result byte reads must be upper byte then lower byte"
    ],
    "warnings": []
  },
  "indirect_flow": {
    "sites": [
      {
        "address": 7192,
        "instruction": "JSR @R0",
        "kind": "call",
        "target_register": "R0",
        "confidence": "unknown",
        "summary": "JSR @R0 uses R0; target not resolved"
      },
      {
        "address": 10403,
        "instruction": "JMP @R1",
        "kind": "jump",
        "target_register": "R1",
        "confidence": "table_load",
        "table": {
          "base": 10406,
          "index_register": "R4",
          "target_register": "R1",
          "load_address": 10399,
          "load_instruction": "MOV:G.W @(H'28A6,R4), R1",
          "entry_size": 2,
          "entry_count": 128,
          "decoded_target_count": 103,
          "entries": [
            {
              "index": 0,
              "entry_address": 10406,
              "target": 11449,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 1,
              "entry_address": 10408,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 2,
              "entry_address": 10410,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 3,
              "entry_address": 10412,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 4,
              "entry_address": 10414,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 5,
              "entry_address": 10416,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 6,
              "entry_address": 10418,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 7,
              "entry_address": 10420,
              "target": 11715,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 8,
              "entry_address": 10422,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 9,
              "entry_address": 10424,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 10,
              "entry_address": 10426,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 11,
              "entry_address": 10428,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 12,
              "entry_address": 10430,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 13,
              "entry_address": 10432,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 14,
              "entry_address": 10434,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 15,
              "entry_address": 10436,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 16,
              "entry_address": 10438,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 17,
              "entry_address": 10440,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 18,
              "entry_address": 10442,
              "target": 11779,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 19,
              "entry_address": 10444,
              "target": 11782,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 20,
              "entry_address": 10446,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 21,
              "entry_address": 10448,
              "target": 11833,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 22,
              "entry_address": 10450,
              "target": 11866,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 23,
              "entry_address": 10452,
              "target": 11909,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 24,
              "entry_address": 10454,
              "target": 11887,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 25,
              "entry_address": 10456,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 26,
              "entry_address": 10458,
              "target": 11972,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 27,
              "entry_address": 10460,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 28,
              "entry_address": 10462,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 29,
              "entry_address": 10464,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 30,
              "entry_address": 10466,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 31,
              "entry_address": 10468,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 32,
              "entry_address": 10470,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 33,
              "entry_address": 10472,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 34,
              "entry_address": 10474,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 35,
              "entry_address": 10476,
              "target": 12006,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 36,
              "entry_address": 10478,
              "target": 12044,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 37,
              "entry_address": 10480,
              "target": 12060,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 38,
              "entry_address": 10482,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 39,
              "entry_address": 10484,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 40,
              "entry_address": 10486,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 41,
              "entry_address": 10488,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 42,
              "entry_address": 10490,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 43,
              "entry_address": 10492,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 44,
              "entry_address": 10494,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 45,
              "entry_address": 10496,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 46,
              "entry_address": 10498,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 47,
              "entry_address": 10500,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 48,
              "entry_address": 10502,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 49,
              "entry_address": 10504,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 50,
              "entry_address": 10506,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 51,
              "entry_address": 10508,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 52,
              "entry_address": 10510,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 53,
              "entry_address": 10512,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 54,
              "entry_address": 10514,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 55,
              "entry_address": 10516,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 56,
              "entry_address": 10518,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 57,
              "entry_address": 10520,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 58,
              "entry_address": 10522,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 59,
              "entry_address": 10524,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 60,
              "entry_address": 10526,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 61,
              "entry_address": 10528,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 62,
              "entry_address": 10530,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 63,
              "entry_address": 10532,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 64,
              "entry_address": 10534,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 65,
              "entry_address": 10536,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 66,
              "entry_address": 10538,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 67,
              "entry_address": 10540,
              "target": 12106,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 68,
              "entry_address": 10542,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 69,
              "entry_address": 10544,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 70,
              "entry_address": 10546,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 71,
              "entry_address": 10548,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 72,
              "entry_address": 10550,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 73,
              "entry_address": 10552,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 74,
              "entry_address": 10554,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 75,
              "entry_address": 10556,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 76,
              "entry_address": 10558,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 77,
              "entry_address": 10560,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 78,
              "entry_address": 10562,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 79,
              "entry_address": 10564,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 80,
              "entry_address": 10566,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 81,
              "entry_address": 10568,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 82,
              "entry_address": 10570,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 83,
              "entry_address": 10572,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 84,
              "entry_address": 10574,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 85,
              "entry_address": 10576,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 86,
              "entry_address": 10578,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 87,
              "entry_address": 10580,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 88,
              "entry_address": 10582,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 89,
              "entry_address": 10584,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 90,
              "entry_address": 10586,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 91,
              "entry_address": 10588,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 92,
              "entry_address": 10590,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 93,
              "entry_address": 10592,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 94,
              "entry_address": 10594,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 95,
              "entry_address": 10596,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 96,
              "entry_address": 10598,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 97,
              "entry_address": 10600,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 98,
              "entry_address": 10602,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 99,
              "entry_address": 10604,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 100,
              "entry_address": 10606,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 101,
              "entry_address": 10608,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 102,
              "entry_address": 10610,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 103,
              "entry_address": 10612,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 104,
              "entry_address": 10614,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 105,
              "entry_address": 10616,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 106,
              "entry_address": 10618,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 107,
              "entry_address": 10620,
              "target": 12146,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 108,
              "entry_address": 10622,
              "target": 12207,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 109,
              "entry_address": 10624,
              "target": 12309,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 110,
              "entry_address": 10626,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 111,
              "entry_address": 10628,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 112,
              "entry_address": 10630,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 113,
              "entry_address": 10632,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 114,
              "entry_address": 10634,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 115,
              "entry_address": 10636,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 116,
              "entry_address": 10638,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 117,
              "entry_address": 10640,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 118,
              "entry_address": 10642,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 119,
              "entry_address": 10644,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 120,
              "entry_address": 10646,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 121,
              "entry_address": 10648,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 122,
              "entry_address": 10650,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 123,
              "entry_address": 10652,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 124,
              "entry_address": 10654,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 125,
              "entry_address": 10656,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 126,
              "entry_address": 10658,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 127,
              "entry_address": 10660,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            }
          ]
        },
        "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)"
      },
      {
        "address": 18747,
        "instruction": "JSR @R0",
        "kind": "call",
        "target_register": "R0",
        "confidence": "table_load",
        "table": {
          "base": 18750,
          "index_register": "R0",
          "target_register": "R0",
          "load_address": 18743,
          "load_instruction": "MOV:G.W @(H'493E,R0), R0",
          "entry_size": 2,
          "entry_count": 52,
          "decoded_target_count": 0,
          "entries": [
            {
              "index": 0,
              "entry_address": 18750,
              "target": 25193,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 1,
              "entry_address": 18752,
              "target": 25372,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 2,
              "entry_address": 18754,
              "target": 25318,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 3,
              "entry_address": 18756,
              "target": 25292,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 4,
              "entry_address": 18758,
              "target": 25268,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 5,
              "entry_address": 18760,
              "target": 25248,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 6,
              "entry_address": 18762,
              "target": 25224,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 7,
              "entry_address": 18764,
              "target": 25205,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 8,
              "entry_address": 18766,
              "target": 25192,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 9,
              "entry_address": 18768,
              "target": 33086,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 10,
              "entry_address": 18770,
              "target": 33062,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 11,
              "entry_address": 18772,
              "target": 33042,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 12,
              "entry_address": 18774,
              "target": 33022,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 13,
              "entry_address": 18776,
              "target": 33002,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 14,
              "entry_address": 18778,
              "target": 32974,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 15,
              "entry_address": 18780,
              "target": 32938,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 16,
              "entry_address": 18782,
              "target": 25192,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 17,
              "entry_address": 18784,
              "target": 37844,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 18,
              "entry_address": 18786,
              "target": 37822,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 19,
              "entry_address": 18788,
              "target": 25192,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 20,
              "entry_address": 18790,
              "target": 37802,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 21,
              "entry_address": 18792,
              "target": 37778,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 22,
              "entry_address": 18794,
              "target": 37756,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 23,
              "entry_address": 18796,
              "target": 37722,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 24,
              "entry_address": 18798,
              "target": 37670,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 25,
              "entry_address": 18800,
              "target": 37642,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 26,
              "entry_address": 18802,
              "target": 37618,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 27,
              "entry_address": 18804,
              "target": 37614,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 28,
              "entry_address": 18806,
              "target": 37580,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 29,
              "entry_address": 18808,
              "target": 5627,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 30,
              "entry_address": 18810,
              "target": 983,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 31,
              "entry_address": 18812,
              "target": 9736,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 32,
              "entry_address": 18814,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 33,
              "entry_address": 18816,
              "target": 12928,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 34,
              "entry_address": 18818,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 35,
              "entry_address": 18820,
              "target": 13456,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 36,
              "entry_address": 18822,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 37,
              "entry_address": 18824,
              "target": 12807,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 38,
              "entry_address": 18826,
              "target": 6912,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 39,
              "entry_address": 18828,
              "target": 7935,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 40,
              "entry_address": 18830,
              "target": 27417,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 41,
              "entry_address": 18832,
              "target": 5627,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 42,
              "entry_address": 18834,
              "target": 983,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 43,
              "entry_address": 18836,
              "target": 9736,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 44,
              "entry_address": 18838,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 45,
              "entry_address": 18840,
              "target": 12928,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 46,
              "entry_address": 18842,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 47,
              "entry_address": 18844,
              "target": 13456,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 48,
              "entry_address": 18846,
              "target": 5623,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 49,
              "entry_address": 18848,
              "target": 12804,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 50,
              "entry_address": 18850,
              "target": 6695,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 51,
              "entry_address": 18852,
              "target": 1565,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            }
          ]
        },
        "summary": "JSR @R0 uses R0 loaded from pointer table H'493E via R0 (0/52 decoded targets)"
      }
    ]
  },
  "dataflow": {
    "blocks": [
      {
        "start": 4096,
        "instructions": [
          4096,
          4099,
          4103,
          4108,
          4113,
          4118,
          4123,
          4128,
          4133,
          4138,
          4143,
          4148,
          4153,
          4158,
          4163,
          4168,
          4174,
          4179,
          4184,
          4189,
          4195,
          4200,
          4205,
          4210,
          4215,
          4220,
          4225,
          4230,
          4235,
          4240,
          4245,
          4250,
          4255,
          4260,
          4265,
          4270,
          4275,
          4280,
          4285,
          4290,
          4295,
          4299
        ],
        "end": 4299,
        "end_exclusive": 4302
      },
      {
        "start": 4302,
        "instructions": [
          4302,
          4305,
          4308,
          4311,
          4314,
          4317,
          4320,
          4323,
          4326,
          4329,
          4332,
          4335,
          4338,
          4341,
          4344,
          4347,
          4350,
          4353,
          4356,
          4359,
          4362,
          4365,
          4368,
          4371,
          4374,
          4377,
          4380,
          4383,
          4386,
          4389,
          4392,
          4395,
          4398,
          4401,
          4404,
          4407,
          4410,
          4413,
          4416,
          4419,
          4422,
          4425,
          4428,
          4431,
          4434,
          4437,
          4440,
          4443,
          4446,
          4449,
          4452,
          4455,
          4458,
          4461,
          4464,
          4467,
          4470,
          4473,
          4476,
          4479,
          4482,
          4485,
          4488,
          4491,
          4494,
          4497,
          4500,
          4503,
          4506,
          4509,
          4512,
          4515,
          4518,
          4521,
          4524,
          4527,
          4530,
          4533,
          4536,
          4539,
          4542,
          4545,
          4548,
          4551,
          4554,
          4557,
          4560,
          4563,
          4566,
          4569,
          4572,
          4575,
          4578,
          4581,
          4584,
          4587,
          4590,
          4593,
          4596,
          4599,
          4602,
          4605,
          4608,
          4611,
          4614,
          4617,
          4620,
          4623,
          4626,
          4629,
          4632,
          4635,
          4638,
          4641,
          4644,
          4647,
          4650,
          4653,
          4656,
          4659,
          4662,
          4665,
          4668,
          4671,
          4674,
          4677,
          4680,
          4683,
          4686,
          4689,
          4692,
          4695,
          4698,
          4701,
          4704,
          4707,
          4710,
          4713,
          4716,
          4719,
          4722,
          4725,
          4728,
          4731,
          4734,
          4737,
          4740,
          4743,
          4746,
          4749,
          4752,
          4755,
          4758,
          4761,
          4764,
          4767,
          4770,
          4773,
          4776,
          4779,
          4782,
          4785,
          4788,
          4791,
          4794,
          4797,
          4800,
          4803,
          4806,
          4809,
          4812,
          4815,
          4818,
          4821,
          4824,
          4827,
          4830,
          4833,
          4836,
          4839,
          4842,
          4845,
          4848,
          4851,
          4854,
          4857,
          4860,
          4863,
          4866,
          4869,
          4872,
          4875,
          4878,
          4881,
          4884,
          4887,
          4890,
          4893,
          4896,
          4899,
          4902,
          4905,
          4908,
          4911,
          4914,
          4917,
          4920,
          4923,
          4926,
          4929,
          4932,
          4935,
          4938,
          4941,
          4944,
          4947,
          4950
        ],
        "end": 4950,
        "end_exclusive": 4951
      },
      {
        "start": 5600,
        "instructions": [
          5600,
          5603,
          5607
        ],
        "end": 5607,
        "end_exclusive": 5609
      },
      {
        "start": 5609,
        "instructions": [
          5609,
          5613,
          5617,
          5619,
          5622
        ],
        "end": 5622,
        "end_exclusive": 5625
      },
      {
        "start": 5625,
        "instructions": [
          5625,
          5629
        ],
        "end": 5629,
        "end_exclusive": 5631
      },
      {
        "start": 5631,
        "instructions": [
          5631,
          5635
        ],
        "end": 5635,
        "end_exclusive": 5637
      },
      {
        "start": 5637,
        "instructions": [
          5637
        ],
        "end": 5637,
        "end_exclusive": 5640
      },
      {
        "start": 5640,
        "instructions": [
          5640,
          5644
        ],
        "end": 5644,
        "end_exclusive": 5646
      },
      {
        "start": 5646,
        "instructions": [
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        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 16540,
        "last_access": 16540,
        "accesses": [
          {
            "address": 57350,
            "instruction_address": 16540,
            "instruction": "MOV:G.W #H'8000, @H'E006",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'E006",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 57414,
        "name": "mem_E046",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 16428,
        "last_access": 16428,
        "accesses": [
          {
            "address": 57414,
            "instruction_address": 16428,
            "instruction": "CLR.W @H'E046",
            "mnemonic": "CLR.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'E046",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 57472,
        "name": "mem_E080",
        "region": "program_or_external",
        "kind": "memory",
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        "read_count": 0,
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        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 16546,
        "last_access": 16546,
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          {
            "address": 57472,
            "instruction_address": 16546,
            "instruction": "MOV:G.W #H'FFFF, @H'E080",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'E080",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 57602,
        "name": "mem_E102",
        "region": "program_or_external",
        "kind": "memory",
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        "unknown_count": 0,
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          "word"
        ],
        "width": "word",
        "first_access": 15834,
        "last_access": 15866,
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          {
            "address": 57602,
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            "instruction": "MOV:G.W @H'E102, R0",
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            "operand": "@H'E102",
            "operand_index": 0
          },
          {
            "address": 57602,
            "instruction_address": 15866,
            "instruction": "CMP:G.W @H'E102, R1",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'E102",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 57636,
        "name": "mem_E124",
        "region": "program_or_external",
        "kind": "memory",
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        "unknown_count": 0,
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          "word"
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        "width": "word",
        "first_access": 9815,
        "last_access": 9867,
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          {
            "address": 57636,
            "instruction_address": 9815,
            "instruction": "MOV:G.W @H'E124, R0",
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            "operand": "@H'E124",
            "operand_index": 0
          },
          {
            "address": 57636,
            "instruction_address": 9867,
            "instruction": "CMP:G.W @H'E124, R0",
            "mnemonic": "CMP:G.W",
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            "width": "word",
            "operand": "@H'E124",
            "operand_index": 0
          }
        ]
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      {
        "address": 57638,
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        "kind": "memory",
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          "word"
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        "width": "word",
        "first_access": 6096,
        "last_access": 6388,
        "accesses": [
          {
            "address": 57638,
            "instruction_address": 6096,
            "instruction": "BTST.W #12, @H'E126",
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            "width": "word",
            "operand": "@H'E126",
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          },
          {
            "address": 57638,
            "instruction_address": 6146,
            "instruction": "BTST.W #12, @H'E126",
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            "width": "word",
            "operand": "@H'E126",
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          },
          {
            "address": 57638,
            "instruction_address": 6202,
            "instruction": "BTST.W #5, @H'E126",
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            "direction": "read",
            "width": "word",
            "operand": "@H'E126",
            "operand_index": 1
          },
          {
            "address": 57638,
            "instruction_address": 6302,
            "instruction": "BTST.W #5, @H'E126",
            "mnemonic": "BTST.W",
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            "width": "word",
            "operand": "@H'E126",
            "operand_index": 1
          },
          {
            "address": 57638,
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            "instruction": "BTST.W #5, @H'E126",
            "mnemonic": "BTST.W",
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            "width": "word",
            "operand": "@H'E126",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 57678,
        "name": "mem_E14E",
        "region": "program_or_external",
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        "unknown_count": 0,
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          "word"
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        "width": "word",
        "first_access": 5900,
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          {
            "address": 57678,
            "instruction_address": 5900,
            "instruction": "BTST.W #15, @H'E14E",
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            "width": "word",
            "operand": "@H'E14E",
            "operand_index": 1
          }
        ]
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        "address": 57710,
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          "word"
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        "width": "word",
        "first_access": 5978,
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          {
            "address": 57710,
            "instruction_address": 5978,
            "instruction": "BTST.W #13, @H'E16E",
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            "width": "word",
            "operand": "@H'E16E",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 57714,
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        "region": "program_or_external",
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          "word"
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        "width": "word",
        "first_access": 6044,
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        "accesses": [
          {
            "address": 57714,
            "instruction_address": 6044,
            "instruction": "BTST.W #13, @H'E172",
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            "width": "word",
            "operand": "@H'E172",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 57836,
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          "word"
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        "width": "word",
        "first_access": 18703,
        "last_access": 18709,
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          {
            "address": 57836,
            "instruction_address": 18703,
            "instruction": "BTST.W #13, @H'E1EC",
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            "operand": "@H'E1EC",
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          {
            "address": 57836,
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            "instruction": "MOV:G.W @H'E1EC, R0",
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            "width": "word",
            "operand": "@H'E1EC",
            "operand_index": 0
          }
        ]
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        "address": 57888,
        "name": "mem_E220",
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          "word"
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        "first_access": 6055,
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          {
            "address": 57888,
            "instruction_address": 6055,
            "instruction": "BTST.W #15, @H'E220",
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            "operand": "@H'E220",
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        ]
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        "address": 59392,
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          "word"
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          {
            "address": 59392,
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            "instruction": "MOV:G.W #H'0080, @H'E800",
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            "width": "word",
            "operand": "@H'E800",
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          }
        ]
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        "address": 59398,
        "name": "mem_E806",
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        "kind": "memory",
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          "word"
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        "first_access": 16558,
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          {
            "address": 59398,
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            "instruction": "MOV:G.W #H'8000, @H'E806",
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            "width": "word",
            "operand": "@H'E806",
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        ]
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        "address": 59520,
        "name": "mem_E880",
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          "word"
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        "first_access": 16564,
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          {
            "address": 59520,
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            "instruction": "MOV:G.W #H'FFFF, @H'E880",
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            "width": "word",
            "operand": "@H'E880",
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          }
        ]
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        "address": 59650,
        "name": "mem_E902",
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          "word"
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        "first_access": 5613,
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            "address": 59650,
            "instruction_address": 5613,
            "instruction": "MOV:G.W R1, @H'E902",
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            "operand": "@H'E902",
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          }
        ]
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        "address": 59684,
        "name": "mem_E924",
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        "kind": "memory",
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          "word"
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        "first_access": 9873,
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          {
            "address": 59684,
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            "instruction": "MOV:G.W R0, @H'E924",
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            "operand": "@H'E924",
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          }
        ]
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        "address": 59884,
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          "word"
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        "width": "word",
        "first_access": 18717,
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          {
            "address": 59884,
            "instruction_address": 18717,
            "instruction": "MOV:G.W R0, @H'E9EC",
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            "operand": "@H'E9EC",
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          }
        ]
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        "address": 61440,
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        "region": "program_or_external",
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          "byte"
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        "first_access": 14906,
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          {
            "address": 61440,
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            "instruction": "BTST.B #1, @H'F000",
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            "operand": "@H'F000",
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          {
            "address": 61440,
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            "operand": "@H'F000",
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        ]
      },
      {
        "address": 61441,
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          "byte"
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            "address": 61441,
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            "operand": "@H'F001",
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          },
          {
            "address": 61441,
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            "instruction": "MOV:G.B @H'F001, R0",
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            "operand": "@H'F001",
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            "address": 61441,
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            "operand": "@H'F001",
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        ]
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      {
        "address": 61442,
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        "region": "program_or_external",
        "kind": "memory",
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          "byte",
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        ],
        "width": "mixed",
        "first_access": 14925,
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            "address": 61442,
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            "instruction": "MOV:G.B R0, @H'F002",
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            "operand": "@H'F002",
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          {
            "address": 61442,
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            "instruction": "MOV:G.W @H'F002, R0",
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            "operand": "@H'F002",
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            "address": 61442,
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            "instruction": "MOV:G.B @H'F002, R0",
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            "width": "byte",
            "operand": "@H'F002",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61443,
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        "region": "program_or_external",
        "kind": "memory",
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          "byte"
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        "width": "byte",
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          {
            "address": 61443,
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            "instruction": "MOV:G.B R0, @H'F003",
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            "operand": "@H'F003",
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          },
          {
            "address": 61443,
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            "instruction": "MOV:G.B @H'F003, R0",
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            "width": "byte",
            "operand": "@H'F003",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61444,
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        "region": "program_or_external",
        "kind": "memory",
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          "byte",
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            "address": 61444,
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            "instruction": "MOV:G.B R0, @H'F004",
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            "operand": "@H'F004",
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          },
          {
            "address": 61444,
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            "instruction": "MOV:G.W @H'F004, R0",
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            "operand": "@H'F004",
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            "address": 61444,
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            "instruction": "MOV:G.B @H'F004, R0",
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            "width": "byte",
            "operand": "@H'F004",
            "operand_index": 0
          }
        ]
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      {
        "address": 61445,
        "name": "mem_F005",
        "region": "program_or_external",
        "kind": "memory",
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          "byte"
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        "width": "byte",
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            "address": 61445,
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            "instruction": "MOV:G.B R0, @H'F005",
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            "operand": "@H'F005",
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          {
            "address": 61445,
            "instruction_address": 15686,
            "instruction": "MOV:G.B @H'F005, R0",
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            "direction": "read",
            "width": "byte",
            "operand": "@H'F005",
            "operand_index": 0
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        ]
      },
      {
        "address": 61446,
        "name": "mem_F006",
        "region": "program_or_external",
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          "byte",
          "word"
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        "width": "mixed",
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        "accesses": [
          {
            "address": 61446,
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            "instruction": "MOV:G.W @H'F006, R0",
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            "width": "word",
            "operand": "@H'F006",
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          },
          {
            "address": 61446,
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            "instruction": "MOV:G.B @H'F006, R0",
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            "direction": "read",
            "width": "byte",
            "operand": "@H'F006",
            "operand_index": 0
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        ]
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      {
        "address": 61447,
        "name": "mem_F007",
        "region": "program_or_external",
        "kind": "memory",
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        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15650,
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        "accesses": [
          {
            "address": 61447,
            "instruction_address": 15650,
            "instruction": "MOV:G.B @H'F007, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F007",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61448,
        "name": "mem_F008",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 2,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 15480,
        "last_access": 15632,
        "accesses": [
          {
            "address": 61448,
            "instruction_address": 15480,
            "instruction": "MOV:G.W @H'F008, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F008",
            "operand_index": 0
          },
          {
            "address": 61448,
            "instruction_address": 15632,
            "instruction": "MOV:G.B @H'F008, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F008",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61449,
        "name": "mem_F009",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14981,
        "last_access": 15614,
        "accesses": [
          {
            "address": 61449,
            "instruction_address": 14981,
            "instruction": "MOV:G.B R0, @H'F009",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F009",
            "operand_index": 1
          },
          {
            "address": 61449,
            "instruction_address": 15614,
            "instruction": "MOV:G.B @H'F009, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F009",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61450,
        "name": "mem_F00A",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 14989,
        "last_access": 15596,
        "accesses": [
          {
            "address": 61450,
            "instruction_address": 14989,
            "instruction": "MOV:G.B R0, @H'F00A",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F00A",
            "operand_index": 1
          },
          {
            "address": 61450,
            "instruction_address": 15462,
            "instruction": "MOV:G.W @H'F00A, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F00A",
            "operand_index": 0
          },
          {
            "address": 61450,
            "instruction_address": 15596,
            "instruction": "MOV:G.W @H'F00A, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F00A",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61451,
        "name": "mem_F00B",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14997,
        "last_access": 14997,
        "accesses": [
          {
            "address": 61451,
            "instruction_address": 14997,
            "instruction": "MOV:G.B R0, @H'F00B",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F00B",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 61452,
        "name": "mem_F00C",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 15005,
        "last_access": 15578,
        "accesses": [
          {
            "address": 61452,
            "instruction_address": 15005,
            "instruction": "MOV:G.B R0, @H'F00C",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F00C",
            "operand_index": 1
          },
          {
            "address": 61452,
            "instruction_address": 15444,
            "instruction": "MOV:G.W @H'F00C, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F00C",
            "operand_index": 0
          },
          {
            "address": 61452,
            "instruction_address": 15578,
            "instruction": "MOV:G.W @H'F00C, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F00C",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61453,
        "name": "mem_F00D",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15013,
        "last_access": 15013,
        "accesses": [
          {
            "address": 61453,
            "instruction_address": 15013,
            "instruction": "MOV:G.B R0, @H'F00D",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F00D",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 61454,
        "name": "mem_F00E",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15021,
        "last_access": 15021,
        "accesses": [
          {
            "address": 61454,
            "instruction_address": 15021,
            "instruction": "MOV:G.B R0, @H'F00E",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F00E",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 61455,
        "name": "mem_F00F",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15037,
        "last_access": 15417,
        "accesses": [
          {
            "address": 61455,
            "instruction_address": 15037,
            "instruction": "MOV:G.B R0, @H'F00F",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F00F",
            "operand_index": 1
          },
          {
            "address": 61455,
            "instruction_address": 15417,
            "instruction": "MOV:G.B @H'F00F, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F00F",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61696,
        "name": "mem_F100",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 2,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14753,
        "last_access": 15049,
        "accesses": [
          {
            "address": 61696,
            "instruction_address": 14753,
            "instruction": "BTST.B #1, @H'F100",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F100",
            "operand_index": 1
          },
          {
            "address": 61696,
            "instruction_address": 15049,
            "instruction": "BTST.B #1, @H'F100",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F100",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 61697,
        "name": "mem_F101",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14748,
        "last_access": 15397,
        "accesses": [
          {
            "address": 61697,
            "instruction_address": 14748,
            "instruction": "MOV:G.B #H'A0, @H'F101",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F101",
            "operand_index": 1
          },
          {
            "address": 61697,
            "instruction_address": 15191,
            "instruction": "MOV:G.B @H'F101, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F101",
            "operand_index": 0
          },
          {
            "address": 61697,
            "instruction_address": 15397,
            "instruction": "MOV:G.B @H'F101, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F101",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61698,
        "name": "mem_F102",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 14772,
        "last_access": 15379,
        "accesses": [
          {
            "address": 61698,
            "instruction_address": 14772,
            "instruction": "MOV:G.B R0, @H'F102",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F102",
            "operand_index": 1
          },
          {
            "address": 61698,
            "instruction_address": 15173,
            "instruction": "MOV:G.W @H'F102, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F102",
            "operand_index": 0
          },
          {
            "address": 61698,
            "instruction_address": 15379,
            "instruction": "MOV:G.B @H'F102, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F102",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61699,
        "name": "mem_F103",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14788,
        "last_access": 15361,
        "accesses": [
          {
            "address": 61699,
            "instruction_address": 14788,
            "instruction": "MOV:G.B R0, @H'F103",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F103",
            "operand_index": 1
          },
          {
            "address": 61699,
            "instruction_address": 15361,
            "instruction": "MOV:G.B @H'F103, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F103",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61700,
        "name": "mem_F104",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 14804,
        "last_access": 15343,
        "accesses": [
          {
            "address": 61700,
            "instruction_address": 14804,
            "instruction": "MOV:G.B R0, @H'F104",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F104",
            "operand_index": 1
          },
          {
            "address": 61700,
            "instruction_address": 15155,
            "instruction": "MOV:G.W @H'F104, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F104",
            "operand_index": 0
          },
          {
            "address": 61700,
            "instruction_address": 15343,
            "instruction": "MOV:G.B @H'F104, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F104",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61701,
        "name": "mem_F105",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14820,
        "last_access": 15325,
        "accesses": [
          {
            "address": 61701,
            "instruction_address": 14820,
            "instruction": "MOV:G.B R0, @H'F105",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F105",
            "operand_index": 1
          },
          {
            "address": 61701,
            "instruction_address": 15325,
            "instruction": "MOV:G.B @H'F105, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F105",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61702,
        "name": "mem_F106",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 2,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 15137,
        "last_access": 15307,
        "accesses": [
          {
            "address": 61702,
            "instruction_address": 15137,
            "instruction": "MOV:G.W @H'F106, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F106",
            "operand_index": 0
          },
          {
            "address": 61702,
            "instruction_address": 15307,
            "instruction": "MOV:G.B @H'F106, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F106",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61703,
        "name": "mem_F107",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15289,
        "last_access": 15289,
        "accesses": [
          {
            "address": 61703,
            "instruction_address": 15289,
            "instruction": "MOV:G.B @H'F107, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F107",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61704,
        "name": "mem_F108",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 2,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 15119,
        "last_access": 15271,
        "accesses": [
          {
            "address": 61704,
            "instruction_address": 15119,
            "instruction": "MOV:G.W @H'F108, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F108",
            "operand_index": 0
          },
          {
            "address": 61704,
            "instruction_address": 15271,
            "instruction": "MOV:G.B @H'F108, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F108",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61705,
        "name": "mem_F109",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14828,
        "last_access": 15253,
        "accesses": [
          {
            "address": 61705,
            "instruction_address": 14828,
            "instruction": "MOV:G.B R0, @H'F109",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F109",
            "operand_index": 1
          },
          {
            "address": 61705,
            "instruction_address": 15253,
            "instruction": "MOV:G.B @H'F109, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F109",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61706,
        "name": "mem_F10A",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 14836,
        "last_access": 15235,
        "accesses": [
          {
            "address": 61706,
            "instruction_address": 14836,
            "instruction": "MOV:G.B R0, @H'F10A",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F10A",
            "operand_index": 1
          },
          {
            "address": 61706,
            "instruction_address": 15101,
            "instruction": "MOV:G.W @H'F10A, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F10A",
            "operand_index": 0
          },
          {
            "address": 61706,
            "instruction_address": 15235,
            "instruction": "MOV:G.W @H'F10A, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F10A",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61707,
        "name": "mem_F10B",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14844,
        "last_access": 14844,
        "accesses": [
          {
            "address": 61707,
            "instruction_address": 14844,
            "instruction": "MOV:G.B R0, @H'F10B",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F10B",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 61708,
        "name": "mem_F10C",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 14852,
        "last_access": 15217,
        "accesses": [
          {
            "address": 61708,
            "instruction_address": 14852,
            "instruction": "MOV:G.B R0, @H'F10C",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F10C",
            "operand_index": 1
          },
          {
            "address": 61708,
            "instruction_address": 15083,
            "instruction": "MOV:G.W @H'F10C, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F10C",
            "operand_index": 0
          },
          {
            "address": 61708,
            "instruction_address": 15217,
            "instruction": "MOV:G.W @H'F10C, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F10C",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61709,
        "name": "mem_F10D",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14860,
        "last_access": 14860,
        "accesses": [
          {
            "address": 61709,
            "instruction_address": 14860,
            "instruction": "MOV:G.B R0, @H'F10D",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F10D",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 61710,
        "name": "mem_F10E",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14868,
        "last_access": 14868,
        "accesses": [
          {
            "address": 61710,
            "instruction_address": 14868,
            "instruction": "MOV:G.B R0, @H'F10E",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F10E",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 61711,
        "name": "mem_F10F",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14884,
        "last_access": 15056,
        "accesses": [
          {
            "address": 61711,
            "instruction_address": 14884,
            "instruction": "MOV:G.B R0, @H'F10F",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F10F",
            "operand_index": 1
          },
          {
            "address": 61711,
            "instruction_address": 15056,
            "instruction": "MOV:G.B @H'F10F, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F10F",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 61952,
        "name": "mem_F200",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16202,
        "last_access": 16219,
        "accesses": [
          {
            "address": 61952,
            "instruction_address": 16202,
            "instruction": "MOVFPE.B @H'F200, R0",
            "mnemonic": "MOVFPE.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F200",
            "operand_index": 0
          },
          {
            "address": 61952,
            "instruction_address": 16219,
            "instruction": "MOVTPE.B R4, @H'F200",
            "mnemonic": "MOVTPE.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F200",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 61953,
        "name": "mem_F201",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16226,
        "last_access": 16237,
        "accesses": [
          {
            "address": 61953,
            "instruction_address": 16226,
            "instruction": "MOVTPE.B R4, @H'F201",
            "mnemonic": "MOVTPE.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F201",
            "operand_index": 1
          },
          {
            "address": 61953,
            "instruction_address": 16237,
            "instruction": "MOVFPE.B @H'F201, R4",
            "mnemonic": "MOVFPE.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F201",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 62466,
        "name": "mem_F402",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 16634,
        "last_access": 16634,
        "accesses": [
          {
            "address": 62466,
            "instruction_address": 16634,
            "instruction": "CMP:G.W #H'6B6F, @H'F402",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F402",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 62468,
        "name": "mem_F404",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 8,
        "read_count": 8,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6119,
        "last_access": 9888,
        "accesses": [
          {
            "address": 62468,
            "instruction_address": 6119,
            "instruction": "BTST.B #3, @H'F404",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F404",
            "operand_index": 1
          },
          {
            "address": 62468,
            "instruction_address": 6169,
            "instruction": "BTST.B #3, @H'F404",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F404",
            "operand_index": 1
          },
          {
            "address": 62468,
            "instruction_address": 6225,
            "instruction": "BTST.B #2, @H'F404",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F404",
            "operand_index": 1
          },
          {
            "address": 62468,
            "instruction_address": 6269,
            "instruction": "BTST.B #1, @H'F404",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F404",
            "operand_index": 1
          },
          {
            "address": 62468,
            "instruction_address": 6355,
            "instruction": "BTST.B #1, @H'F404",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F404",
            "operand_index": 1
          },
          {
            "address": 62468,
            "instruction_address": 6411,
            "instruction": "BTST.B #2, @H'F404",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F404",
            "operand_index": 1
          },
          {
            "address": 62468,
            "instruction_address": 6455,
            "instruction": "BTST.B #1, @H'F404",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F404",
            "operand_index": 1
          },
          {
            "address": 62468,
            "instruction_address": 9888,
            "instruction": "BTST.B #4, @H'F404",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F404",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 62634,
        "name": "mem_F4AA",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 17173,
        "last_access": 17173,
        "accesses": [
          {
            "address": 62634,
            "instruction_address": 17173,
            "instruction": "MOV:G.B #H'55, @H'F4AA",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F4AA",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 62805,
        "name": "mem_F555",
        "region": "program_or_external",
        "kind": "memory",
        "access_count": 2,
        "read_count": 0,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 17168,
        "last_access": 17178,
        "accesses": [
          {
            "address": 62805,
            "instruction_address": 17168,
            "instruction": "MOV:G.B #H'AA, @H'F555",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F555",
            "operand_index": 1
          },
          {
            "address": 62805,
            "instruction_address": 17178,
            "instruction": "MOV:G.B #H'CC, @H'F555",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F555",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63112,
        "name": "ram_F688",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14670,
        "last_access": 14683,
        "accesses": [
          {
            "address": 63112,
            "instruction_address": 14670,
            "instruction": "BSET.B R0, @H'F688",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F688",
            "operand_index": 1
          },
          {
            "address": 63112,
            "instruction_address": 14683,
            "instruction": "BCLR.B R0, @H'F688",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F688",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63113,
        "name": "ram_F689",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 5603,
        "last_access": 15876,
        "accesses": [
          {
            "address": 63113,
            "instruction_address": 5603,
            "instruction": "BCLR.B #7, @H'F689",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F689",
            "operand_index": 1
          },
          {
            "address": 63113,
            "instruction_address": 15876,
            "instruction": "BSET.B #7, @H'F689",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F689",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63114,
        "name": "ram_F68A",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15775,
        "last_access": 15809,
        "accesses": [
          {
            "address": 63114,
            "instruction_address": 15775,
            "instruction": "MOV:G.B @H'F68A, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F68A",
            "operand_index": 0
          },
          {
            "address": 63114,
            "instruction_address": 15799,
            "instruction": "CMP:G.B @H'F68A, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F68A",
            "operand_index": 0
          },
          {
            "address": 63114,
            "instruction_address": 15805,
            "instruction": "MOV:G.B @H'F68A, R2",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F68A",
            "operand_index": 0
          },
          {
            "address": 63114,
            "instruction_address": 15809,
            "instruction": "MOV:G.B R0, @H'F68A",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F68A",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63115,
        "name": "ram_F68B",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15880,
        "last_access": 15912,
        "accesses": [
          {
            "address": 63115,
            "instruction_address": 15880,
            "instruction": "MOV:G.B @H'F68B, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F68B",
            "operand_index": 0
          },
          {
            "address": 63115,
            "instruction_address": 15906,
            "instruction": "CMP:G.B @H'F68B, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F68B",
            "operand_index": 0
          },
          {
            "address": 63115,
            "instruction_address": 15912,
            "instruction": "MOV:G.B R0, @H'F68B",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F68B",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63116,
        "name": "ram_F68C",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 1,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6536,
        "last_access": 15945,
        "accesses": [
          {
            "address": 63116,
            "instruction_address": 6536,
            "instruction": "MULXU.W @H'F68C, R0",
            "mnemonic": "MULXU.W",
            "direction": "unknown",
            "width": "word",
            "operand": "@H'F68C",
            "operand_index": 0
          },
          {
            "address": 63116,
            "instruction_address": 15900,
            "instruction": "TST.W @H'F68C",
            "mnemonic": "TST.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F68C",
            "operand_index": 0
          },
          {
            "address": 63116,
            "instruction_address": 15945,
            "instruction": "MOV:G.W R0, @H'F68C",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F68C",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63118,
        "name": "ram_F68E",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 5609,
        "last_access": 15872,
        "accesses": [
          {
            "address": 63118,
            "instruction_address": 5609,
            "instruction": "MOV:G.W @H'F68E, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F68E",
            "operand_index": 0
          },
          {
            "address": 63118,
            "instruction_address": 15872,
            "instruction": "MOV:G.W R1, @H'F68E",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F68E",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63120,
        "name": "ram_F690",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 15177,
        "last_access": 15187,
        "accesses": [
          {
            "address": 63120,
            "instruction_address": 15177,
            "instruction": "CMP:G.W @H'F690, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F690",
            "operand_index": 0
          },
          {
            "address": 63120,
            "instruction_address": 15187,
            "instruction": "MOV:G.W R0, @H'F690",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F690",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63122,
        "name": "ram_F692",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6066,
        "last_access": 15169,
        "accesses": [
          {
            "address": 63122,
            "instruction_address": 6066,
            "instruction": "MOV:G.W @H'F692, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F692",
            "operand_index": 0
          },
          {
            "address": 63122,
            "instruction_address": 6080,
            "instruction": "MOV:G.W @H'F692, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F692",
            "operand_index": 0
          },
          {
            "address": 63122,
            "instruction_address": 15159,
            "instruction": "CMP:G.W @H'F692, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F692",
            "operand_index": 0
          },
          {
            "address": 63122,
            "instruction_address": 15169,
            "instruction": "MOV:G.W R0, @H'F692",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F692",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63124,
        "name": "ram_F694",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6014,
        "last_access": 15151,
        "accesses": [
          {
            "address": 63124,
            "instruction_address": 6014,
            "instruction": "MOV:G.W @H'F694, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F694",
            "operand_index": 0
          },
          {
            "address": 63124,
            "instruction_address": 6028,
            "instruction": "MOV:G.W @H'F694, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F694",
            "operand_index": 0
          },
          {
            "address": 63124,
            "instruction_address": 15141,
            "instruction": "CMP:G.W @H'F694, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F694",
            "operand_index": 0
          },
          {
            "address": 63124,
            "instruction_address": 15151,
            "instruction": "MOV:G.W R0, @H'F694",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F694",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63126,
        "name": "ram_F696",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 5942,
        "last_access": 15133,
        "accesses": [
          {
            "address": 63126,
            "instruction_address": 5942,
            "instruction": "MOV:G.W @H'F696, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F696",
            "operand_index": 0
          },
          {
            "address": 63126,
            "instruction_address": 5956,
            "instruction": "MOV:G.W @H'F696, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F696",
            "operand_index": 0
          },
          {
            "address": 63126,
            "instruction_address": 15123,
            "instruction": "CMP:G.W @H'F696, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F696",
            "operand_index": 0
          },
          {
            "address": 63126,
            "instruction_address": 15133,
            "instruction": "MOV:G.W R0, @H'F696",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F696",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63128,
        "name": "ram_F698",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
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        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 15105,
        "last_access": 15115,
        "accesses": [
          {
            "address": 63128,
            "instruction_address": 15105,
            "instruction": "CMP:G.W @H'F698, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F698",
            "operand_index": 0
          },
          {
            "address": 63128,
            "instruction_address": 15115,
            "instruction": "MOV:G.W R0, @H'F698",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F698",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63130,
        "name": "ram_F69A",
        "region": "on_chip_ram",
        "kind": "ram",
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        "unknown_count": 0,
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          "word"
        ],
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        "first_access": 15087,
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          {
            "address": 63130,
            "instruction_address": 15087,
            "instruction": "CMP:G.W @H'F69A, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F69A",
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          },
          {
            "address": 63130,
            "instruction_address": 15097,
            "instruction": "MOV:G.W R0, @H'F69A",
            "mnemonic": "MOV:G.W",
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            "width": "word",
            "operand": "@H'F69A",
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          },
          {
            "address": 63130,
            "instruction_address": 17712,
            "instruction": "MOV:G.W @H'F69A, R4",
            "mnemonic": "MOV:G.W",
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            "width": "word",
            "operand": "@H'F69A",
            "operand_index": 0
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          {
            "address": 63130,
            "instruction_address": 17832,
            "instruction": "MOV:G.W @H'F69A, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F69A",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63132,
        "name": "ram_F69C",
        "region": "on_chip_ram",
        "kind": "ram",
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        "unknown_count": 0,
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          "word"
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        "width": "word",
        "first_access": 15239,
        "last_access": 17637,
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          {
            "address": 63132,
            "instruction_address": 15239,
            "instruction": "CMP:G.W @H'F69C, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F69C",
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          },
          {
            "address": 63132,
            "instruction_address": 15249,
            "instruction": "MOV:G.W R0, @H'F69C",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F69C",
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          },
          {
            "address": 63132,
            "instruction_address": 17517,
            "instruction": "MOV:G.W @H'F69C, R4",
            "mnemonic": "MOV:G.W",
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            "width": "word",
            "operand": "@H'F69C",
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          {
            "address": 63132,
            "instruction_address": 17637,
            "instruction": "MOV:G.W @H'F69C, R4",
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            "width": "word",
            "operand": "@H'F69C",
            "operand_index": 0
          }
        ]
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      {
        "address": 63134,
        "name": "ram_F69E",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 3,
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          "word"
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        "width": "word",
        "first_access": 15221,
        "last_access": 17442,
        "accesses": [
          {
            "address": 63134,
            "instruction_address": 15221,
            "instruction": "CMP:G.W @H'F69E, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F69E",
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          },
          {
            "address": 63134,
            "instruction_address": 15231,
            "instruction": "MOV:G.W R0, @H'F69E",
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            "direction": "write",
            "width": "word",
            "operand": "@H'F69E",
            "operand_index": 1
          },
          {
            "address": 63134,
            "instruction_address": 17322,
            "instruction": "MOV:G.W @H'F69E, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F69E",
            "operand_index": 0
          },
          {
            "address": 63134,
            "instruction_address": 17442,
            "instruction": "MOV:G.W @H'F69E, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F69E",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63136,
        "name": "ram_F6A0",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
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        "width": "word",
        "first_access": 15538,
        "last_access": 15548,
        "accesses": [
          {
            "address": 63136,
            "instruction_address": 15538,
            "instruction": "CMP:G.W @H'F6A0, R0",
            "mnemonic": "CMP:G.W",
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            "width": "word",
            "operand": "@H'F6A0",
            "operand_index": 0
          },
          {
            "address": 63136,
            "instruction_address": 15548,
            "instruction": "MOV:G.W R0, @H'F6A0",
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            "direction": "write",
            "width": "word",
            "operand": "@H'F6A0",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63138,
        "name": "ram_F6A2",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
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        "width": "word",
        "first_access": 6528,
        "last_access": 15530,
        "accesses": [
          {
            "address": 63138,
            "instruction_address": 6528,
            "instruction": "MOV:G.W @H'F6A2, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6A2",
            "operand_index": 0
          },
          {
            "address": 63138,
            "instruction_address": 6553,
            "instruction": "MOV:G.W @H'F6A2, R4",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6A2",
            "operand_index": 0
          },
          {
            "address": 63138,
            "instruction_address": 15520,
            "instruction": "CMP:G.W @H'F6A2, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6A2",
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          },
          {
            "address": 63138,
            "instruction_address": 15530,
            "instruction": "MOV:G.W R0, @H'F6A2",
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            "width": "word",
            "operand": "@H'F6A2",
            "operand_index": 1
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        ]
      },
      {
        "address": 63140,
        "name": "ram_F6A4",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 3,
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        "unknown_count": 0,
        "width_hints": [
          "word"
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        "width": "word",
        "first_access": 6481,
        "last_access": 15512,
        "accesses": [
          {
            "address": 63140,
            "instruction_address": 6481,
            "instruction": "MOV:G.W @H'F6A4, R4",
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            "direction": "read",
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            "operand": "@H'F6A4",
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          },
          {
            "address": 63140,
            "instruction_address": 6512,
            "instruction": "MOV:G.W @H'F6A4, R4",
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            "width": "word",
            "operand": "@H'F6A4",
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          },
          {
            "address": 63140,
            "instruction_address": 15502,
            "instruction": "CMP:G.W @H'F6A4, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6A4",
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          },
          {
            "address": 63140,
            "instruction_address": 15512,
            "instruction": "MOV:G.W R0, @H'F6A4",
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            "direction": "write",
            "width": "word",
            "operand": "@H'F6A4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63142,
        "name": "ram_F6A6",
        "region": "on_chip_ram",
        "kind": "ram",
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          "word"
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        "first_access": 6394,
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        "accesses": [
          {
            "address": 63142,
            "instruction_address": 6394,
            "instruction": "MOV:G.W @H'F6A6, R4",
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            "width": "word",
            "operand": "@H'F6A6",
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          {
            "address": 63142,
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            "instruction": "MOV:G.W @H'F6A6, R4",
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            "width": "word",
            "operand": "@H'F6A6",
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          {
            "address": 63142,
            "instruction_address": 6438,
            "instruction": "MOV:G.W @H'F6A6, R4",
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            "width": "word",
            "operand": "@H'F6A6",
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          {
            "address": 63142,
            "instruction_address": 6465,
            "instruction": "MOV:G.W @H'F6A6, R4",
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            "width": "word",
            "operand": "@H'F6A6",
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          },
          {
            "address": 63142,
            "instruction_address": 15484,
            "instruction": "CMP:G.W @H'F6A6, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6A6",
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          },
          {
            "address": 63142,
            "instruction_address": 15494,
            "instruction": "MOV:G.W R0, @H'F6A6",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6A6",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63144,
        "name": "ram_F6A8",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 5,
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        "width_hints": [
          "word"
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        "width": "word",
        "first_access": 6308,
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        "accesses": [
          {
            "address": 63144,
            "instruction_address": 6308,
            "instruction": "MOV:G.W @H'F6A8, R4",
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            "operand": "@H'F6A8",
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          {
            "address": 63144,
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            "instruction": "MOV:G.W @H'F6A8, R4",
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            "operand": "@H'F6A8",
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          },
          {
            "address": 63144,
            "instruction_address": 6338,
            "instruction": "MOV:G.W @H'F6A8, R4",
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            "width": "word",
            "operand": "@H'F6A8",
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          {
            "address": 63144,
            "instruction_address": 6366,
            "instruction": "MOV:G.W @H'F6A8, R4",
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            "width": "word",
            "operand": "@H'F6A8",
            "operand_index": 0
          },
          {
            "address": 63144,
            "instruction_address": 15466,
            "instruction": "CMP:G.W @H'F6A8, R0",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6A8",
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          },
          {
            "address": 63144,
            "instruction_address": 15476,
            "instruction": "MOV:G.W R0, @H'F6A8",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6A8",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63146,
        "name": "ram_F6AA",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 6,
        "read_count": 5,
        "write_count": 1,
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        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6208,
        "last_access": 15458,
        "accesses": [
          {
            "address": 63146,
            "instruction_address": 6208,
            "instruction": "MOV:G.W @H'F6AA, R4",
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            "width": "word",
            "operand": "@H'F6AA",
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          },
          {
            "address": 63146,
            "instruction_address": 6236,
            "instruction": "MOV:G.W @H'F6AA, R4",
            "mnemonic": "MOV:G.W",
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            "width": "word",
            "operand": "@H'F6AA",
            "operand_index": 0
          },
          {
            "address": 63146,
            "instruction_address": 6252,
            "instruction": "MOV:G.W @H'F6AA, R4",
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            "width": "word",
            "operand": "@H'F6AA",
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          },
          {
            "address": 63146,
            "instruction_address": 6280,
            "instruction": "MOV:G.W @H'F6AA, R4",
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            "width": "word",
            "operand": "@H'F6AA",
            "operand_index": 0
          },
          {
            "address": 63146,
            "instruction_address": 15448,
            "instruction": "CMP:G.W @H'F6AA, R0",
            "mnemonic": "CMP:G.W",
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            "width": "word",
            "operand": "@H'F6AA",
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          },
          {
            "address": 63146,
            "instruction_address": 15458,
            "instruction": "MOV:G.W R0, @H'F6AA",
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            "direction": "write",
            "width": "word",
            "operand": "@H'F6AA",
            "operand_index": 1
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        ]
      },
      {
        "address": 63148,
        "name": "ram_F6AC",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 3,
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        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6152,
        "last_access": 15610,
        "accesses": [
          {
            "address": 63148,
            "instruction_address": 6152,
            "instruction": "MOV:G.W @H'F6AC, R4",
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            "width": "word",
            "operand": "@H'F6AC",
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          {
            "address": 63148,
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            "instruction": "MOV:G.W @H'F6AC, R4",
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            "width": "word",
            "operand": "@H'F6AC",
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          },
          {
            "address": 63148,
            "instruction_address": 15600,
            "instruction": "CMP:G.W @H'F6AC, R0",
            "mnemonic": "CMP:G.W",
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            "width": "word",
            "operand": "@H'F6AC",
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          },
          {
            "address": 63148,
            "instruction_address": 15610,
            "instruction": "MOV:G.W R0, @H'F6AC",
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            "direction": "write",
            "width": "word",
            "operand": "@H'F6AC",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63150,
        "name": "ram_F6AE",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 3,
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        "unknown_count": 0,
        "width_hints": [
          "word"
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        "width": "word",
        "first_access": 6102,
        "last_access": 15592,
        "accesses": [
          {
            "address": 63150,
            "instruction_address": 6102,
            "instruction": "MOV:G.W @H'F6AE, R4",
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            "width": "word",
            "operand": "@H'F6AE",
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          },
          {
            "address": 63150,
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            "instruction": "MOV:G.W @H'F6AE, R4",
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            "width": "word",
            "operand": "@H'F6AE",
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          },
          {
            "address": 63150,
            "instruction_address": 15582,
            "instruction": "CMP:G.W @H'F6AE, R0",
            "mnemonic": "CMP:G.W",
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            "width": "word",
            "operand": "@H'F6AE",
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          },
          {
            "address": 63150,
            "instruction_address": 15592,
            "instruction": "MOV:G.W R0, @H'F6AE",
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            "width": "word",
            "operand": "@H'F6AE",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63154,
        "name": "ram_F6B2",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6070,
        "last_access": 6084,
        "accesses": [
          {
            "address": 63154,
            "instruction_address": 6070,
            "instruction": "SUB.W @H'F6B2, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6B2",
            "operand_index": 0
          },
          {
            "address": 63154,
            "instruction_address": 6084,
            "instruction": "MOV:G.W R4, @H'F6B2",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6B2",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63156,
        "name": "ram_F6B4",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6018,
        "last_access": 6032,
        "accesses": [
          {
            "address": 63156,
            "instruction_address": 6018,
            "instruction": "SUB.W @H'F6B4, R4",
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            "direction": "read",
            "width": "word",
            "operand": "@H'F6B4",
            "operand_index": 0
          },
          {
            "address": 63156,
            "instruction_address": 6032,
            "instruction": "MOV:G.W R4, @H'F6B4",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6B4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63158,
        "name": "ram_F6B6",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
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        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 5946,
        "last_access": 5960,
        "accesses": [
          {
            "address": 63158,
            "instruction_address": 5946,
            "instruction": "SUB.W @H'F6B6, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6B6",
            "operand_index": 0
          },
          {
            "address": 63158,
            "instruction_address": 5960,
            "instruction": "MOV:G.W R4, @H'F6B6",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6B6",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63162,
        "name": "ram_F6BA",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 17716,
        "last_access": 17836,
        "accesses": [
          {
            "address": 63162,
            "instruction_address": 17716,
            "instruction": "SUB.W @H'F6BA, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6BA",
            "operand_index": 0
          },
          {
            "address": 63162,
            "instruction_address": 17836,
            "instruction": "MOV:G.W R4, @H'F6BA",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6BA",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63164,
        "name": "ram_F6BC",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 17521,
        "last_access": 17641,
        "accesses": [
          {
            "address": 63164,
            "instruction_address": 17521,
            "instruction": "SUB.W @H'F6BC, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6BC",
            "operand_index": 0
          },
          {
            "address": 63164,
            "instruction_address": 17641,
            "instruction": "MOV:G.W R4, @H'F6BC",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6BC",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63166,
        "name": "ram_F6BE",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 17326,
        "last_access": 17446,
        "accesses": [
          {
            "address": 63166,
            "instruction_address": 17326,
            "instruction": "SUB.W @H'F6BE, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6BE",
            "operand_index": 0
          },
          {
            "address": 63166,
            "instruction_address": 17446,
            "instruction": "MOV:G.W R4, @H'F6BE",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6BE",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63170,
        "name": "ram_F6C2",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6532,
        "last_access": 6557,
        "accesses": [
          {
            "address": 63170,
            "instruction_address": 6532,
            "instruction": "SUB.W @H'F6C2, R0",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6C2",
            "operand_index": 0
          },
          {
            "address": 63170,
            "instruction_address": 6557,
            "instruction": "MOV:G.W R4, @H'F6C2",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6C2",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63172,
        "name": "ram_F6C4",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6485,
        "last_access": 6516,
        "accesses": [
          {
            "address": 63172,
            "instruction_address": 6485,
            "instruction": "SUB.W @H'F6C4, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6C4",
            "operand_index": 0
          },
          {
            "address": 63172,
            "instruction_address": 6516,
            "instruction": "MOV:G.W R4, @H'F6C4",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6C4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63174,
        "name": "ram_F6C6",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6398,
        "last_access": 6469,
        "accesses": [
          {
            "address": 63174,
            "instruction_address": 6398,
            "instruction": "SUB.W @H'F6C6, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6C6",
            "operand_index": 0
          },
          {
            "address": 63174,
            "instruction_address": 6426,
            "instruction": "MOV:G.W R4, @H'F6C6",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6C6",
            "operand_index": 1
          },
          {
            "address": 63174,
            "instruction_address": 6442,
            "instruction": "SUB.W @H'F6C6, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6C6",
            "operand_index": 0
          },
          {
            "address": 63174,
            "instruction_address": 6469,
            "instruction": "MOV:G.W R4, @H'F6C6",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6C6",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63176,
        "name": "ram_F6C8",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6312,
        "last_access": 6370,
        "accesses": [
          {
            "address": 63176,
            "instruction_address": 6312,
            "instruction": "SUB.W @H'F6C8, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6C8",
            "operand_index": 0
          },
          {
            "address": 63176,
            "instruction_address": 6326,
            "instruction": "MOV:G.W R4, @H'F6C8",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6C8",
            "operand_index": 1
          },
          {
            "address": 63176,
            "instruction_address": 6342,
            "instruction": "SUB.W @H'F6C8, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6C8",
            "operand_index": 0
          },
          {
            "address": 63176,
            "instruction_address": 6370,
            "instruction": "MOV:G.W R4, @H'F6C8",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6C8",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63178,
        "name": "ram_F6CA",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6212,
        "last_access": 6284,
        "accesses": [
          {
            "address": 63178,
            "instruction_address": 6212,
            "instruction": "SUB.W @H'F6CA, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6CA",
            "operand_index": 0
          },
          {
            "address": 63178,
            "instruction_address": 6240,
            "instruction": "MOV:G.W R4, @H'F6CA",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6CA",
            "operand_index": 1
          },
          {
            "address": 63178,
            "instruction_address": 6256,
            "instruction": "SUB.W @H'F6CA, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6CA",
            "operand_index": 0
          },
          {
            "address": 63178,
            "instruction_address": 6284,
            "instruction": "MOV:G.W R4, @H'F6CA",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6CA",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63180,
        "name": "ram_F6CC",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6156,
        "last_access": 6184,
        "accesses": [
          {
            "address": 63180,
            "instruction_address": 6156,
            "instruction": "SUB.W @H'F6CC, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6CC",
            "operand_index": 0
          },
          {
            "address": 63180,
            "instruction_address": 6184,
            "instruction": "MOV:G.W R4, @H'F6CC",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6CC",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63182,
        "name": "ram_F6CE",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 6106,
        "last_access": 6134,
        "accesses": [
          {
            "address": 63182,
            "instruction_address": 6106,
            "instruction": "SUB.W @H'F6CE, R4",
            "mnemonic": "SUB.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6CE",
            "operand_index": 0
          },
          {
            "address": 63182,
            "instruction_address": 6134,
            "instruction": "MOV:G.W R4, @H'F6CE",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6CE",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63184,
        "name": "ram_F6D0",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7049,
        "last_access": 15267,
        "accesses": [
          {
            "address": 63184,
            "instruction_address": 7049,
            "instruction": "MOV:G.B @H'F6D0, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D0",
            "operand_index": 0
          },
          {
            "address": 63184,
            "instruction_address": 7063,
            "instruction": "MOV:G.B @H'F6D0, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D0",
            "operand_index": 0
          },
          {
            "address": 63184,
            "instruction_address": 15257,
            "instruction": "CMP:G.B @H'F6D0, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D0",
            "operand_index": 0
          },
          {
            "address": 63184,
            "instruction_address": 15267,
            "instruction": "MOV:G.B R0, @H'F6D0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D0",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63185,
        "name": "ram_F6D1",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7026,
        "last_access": 15285,
        "accesses": [
          {
            "address": 63185,
            "instruction_address": 7026,
            "instruction": "MOV:G.B @H'F6D1, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D1",
            "operand_index": 0
          },
          {
            "address": 63185,
            "instruction_address": 7040,
            "instruction": "MOV:G.B @H'F6D1, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D1",
            "operand_index": 0
          },
          {
            "address": 63185,
            "instruction_address": 15275,
            "instruction": "CMP:G.B @H'F6D1, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D1",
            "operand_index": 0
          },
          {
            "address": 63185,
            "instruction_address": 15285,
            "instruction": "MOV:G.B R0, @H'F6D1",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D1",
            "operand_index": 1
          }
        ],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 18602,
            "target": 63185
          }
        ]
      },
      {
        "address": 63186,
        "name": "ram_F6D2",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7116,
        "last_access": 15303,
        "accesses": [
          {
            "address": 63186,
            "instruction_address": 7116,
            "instruction": "MOV:G.B @H'F6D2, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D2",
            "operand_index": 0
          },
          {
            "address": 63186,
            "instruction_address": 7129,
            "instruction": "MOV:G.B @H'F6D2, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D2",
            "operand_index": 0
          },
          {
            "address": 63186,
            "instruction_address": 15293,
            "instruction": "CMP:G.B @H'F6D2, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D2",
            "operand_index": 0
          },
          {
            "address": 63186,
            "instruction_address": 15303,
            "instruction": "MOV:G.B R0, @H'F6D2",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D2",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63187,
        "name": "ram_F6D3",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7094,
        "last_access": 15321,
        "accesses": [
          {
            "address": 63187,
            "instruction_address": 7094,
            "instruction": "MOV:G.B @H'F6D3, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D3",
            "operand_index": 0
          },
          {
            "address": 63187,
            "instruction_address": 7107,
            "instruction": "MOV:G.B @H'F6D3, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D3",
            "operand_index": 0
          },
          {
            "address": 63187,
            "instruction_address": 15311,
            "instruction": "CMP:G.B @H'F6D3, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D3",
            "operand_index": 0
          },
          {
            "address": 63187,
            "instruction_address": 15321,
            "instruction": "MOV:G.B R0, @H'F6D3",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D3",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63188,
        "name": "ram_F6D4",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7072,
        "last_access": 15339,
        "accesses": [
          {
            "address": 63188,
            "instruction_address": 7072,
            "instruction": "MOV:G.B @H'F6D4, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D4",
            "operand_index": 0
          },
          {
            "address": 63188,
            "instruction_address": 7085,
            "instruction": "MOV:G.B @H'F6D4, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D4",
            "operand_index": 0
          },
          {
            "address": 63188,
            "instruction_address": 15329,
            "instruction": "CMP:G.B @H'F6D4, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D4",
            "operand_index": 0
          },
          {
            "address": 63188,
            "instruction_address": 15339,
            "instruction": "MOV:G.B R0, @H'F6D4",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63189,
        "name": "ram_F6D5",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7003,
        "last_access": 15357,
        "accesses": [
          {
            "address": 63189,
            "instruction_address": 7003,
            "instruction": "MOV:G.B @H'F6D5, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D5",
            "operand_index": 0
          },
          {
            "address": 63189,
            "instruction_address": 7017,
            "instruction": "MOV:G.B @H'F6D5, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D5",
            "operand_index": 0
          },
          {
            "address": 63189,
            "instruction_address": 15347,
            "instruction": "CMP:G.B @H'F6D5, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D5",
            "operand_index": 0
          },
          {
            "address": 63189,
            "instruction_address": 15357,
            "instruction": "MOV:G.B R0, @H'F6D5",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D5",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63190,
        "name": "ram_F6D6",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6980,
        "last_access": 15375,
        "accesses": [
          {
            "address": 63190,
            "instruction_address": 6980,
            "instruction": "MOV:G.B @H'F6D6, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D6",
            "operand_index": 0
          },
          {
            "address": 63190,
            "instruction_address": 6994,
            "instruction": "MOV:G.B @H'F6D6, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D6",
            "operand_index": 0
          },
          {
            "address": 63190,
            "instruction_address": 15365,
            "instruction": "CMP:G.B @H'F6D6, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D6",
            "operand_index": 0
          },
          {
            "address": 63190,
            "instruction_address": 15375,
            "instruction": "MOV:G.B R0, @H'F6D6",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D6",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63191,
        "name": "ram_F6D7",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6957,
        "last_access": 15393,
        "accesses": [
          {
            "address": 63191,
            "instruction_address": 6957,
            "instruction": "MOV:G.B @H'F6D7, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D7",
            "operand_index": 0
          },
          {
            "address": 63191,
            "instruction_address": 6971,
            "instruction": "MOV:G.B @H'F6D7, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D7",
            "operand_index": 0
          },
          {
            "address": 63191,
            "instruction_address": 15383,
            "instruction": "CMP:G.B @H'F6D7, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D7",
            "operand_index": 0
          },
          {
            "address": 63191,
            "instruction_address": 15393,
            "instruction": "MOV:G.B R0, @H'F6D7",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D7",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63192,
        "name": "ram_F6D8",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15618,
        "last_access": 15628,
        "accesses": [
          {
            "address": 63192,
            "instruction_address": 15618,
            "instruction": "CMP:G.B @H'F6D8, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D8",
            "operand_index": 0
          },
          {
            "address": 63192,
            "instruction_address": 15628,
            "instruction": "MOV:G.B R0, @H'F6D8",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D8",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63193,
        "name": "ram_F6D9",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15636,
        "last_access": 15646,
        "accesses": [
          {
            "address": 63193,
            "instruction_address": 15636,
            "instruction": "CMP:G.B @H'F6D9, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6D9",
            "operand_index": 0
          },
          {
            "address": 63193,
            "instruction_address": 15646,
            "instruction": "MOV:G.B R0, @H'F6D9",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6D9",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63194,
        "name": "ram_F6DA",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15654,
        "last_access": 15664,
        "accesses": [
          {
            "address": 63194,
            "instruction_address": 15654,
            "instruction": "CMP:G.B @H'F6DA, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DA",
            "operand_index": 0
          },
          {
            "address": 63194,
            "instruction_address": 15664,
            "instruction": "MOV:G.B R0, @H'F6DA",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6DA",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63195,
        "name": "ram_F6DB",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7160,
        "last_access": 15682,
        "accesses": [
          {
            "address": 63195,
            "instruction_address": 7160,
            "instruction": "MOV:G.B @H'F6DB, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DB",
            "operand_index": 0
          },
          {
            "address": 63195,
            "instruction_address": 7173,
            "instruction": "MOV:G.B @H'F6DB, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DB",
            "operand_index": 0
          },
          {
            "address": 63195,
            "instruction_address": 15672,
            "instruction": "CMP:G.B @H'F6DB, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DB",
            "operand_index": 0
          },
          {
            "address": 63195,
            "instruction_address": 15682,
            "instruction": "MOV:G.B R0, @H'F6DB",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6DB",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63196,
        "name": "ram_F6DC",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7138,
        "last_access": 15700,
        "accesses": [
          {
            "address": 63196,
            "instruction_address": 7138,
            "instruction": "MOV:G.B @H'F6DC, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DC",
            "operand_index": 0
          },
          {
            "address": 63196,
            "instruction_address": 7151,
            "instruction": "MOV:G.B @H'F6DC, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DC",
            "operand_index": 0
          },
          {
            "address": 63196,
            "instruction_address": 15690,
            "instruction": "CMP:G.B @H'F6DC, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DC",
            "operand_index": 0
          },
          {
            "address": 63196,
            "instruction_address": 15700,
            "instruction": "MOV:G.B R0, @H'F6DC",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6DC",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63197,
        "name": "ram_F6DD",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15708,
        "last_access": 15718,
        "accesses": [
          {
            "address": 63197,
            "instruction_address": 15708,
            "instruction": "CMP:G.B @H'F6DD, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DD",
            "operand_index": 0
          },
          {
            "address": 63197,
            "instruction_address": 15718,
            "instruction": "MOV:G.B R0, @H'F6DD",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6DD",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63198,
        "name": "ram_F6DE",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15726,
        "last_access": 15736,
        "accesses": [
          {
            "address": 63198,
            "instruction_address": 15726,
            "instruction": "CMP:G.B @H'F6DE, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DE",
            "operand_index": 0
          },
          {
            "address": 63198,
            "instruction_address": 15736,
            "instruction": "MOV:G.B R0, @H'F6DE",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6DE",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63199,
        "name": "ram_F6DF",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15744,
        "last_access": 15754,
        "accesses": [
          {
            "address": 63199,
            "instruction_address": 15744,
            "instruction": "CMP:G.B @H'F6DF, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6DF",
            "operand_index": 0
          },
          {
            "address": 63199,
            "instruction_address": 15754,
            "instruction": "MOV:G.B R0, @H'F6DF",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6DF",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63200,
        "name": "ram_F6E0",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7053,
        "last_access": 7067,
        "accesses": [
          {
            "address": 63200,
            "instruction_address": 7053,
            "instruction": "XOR.B @H'F6E0, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6E0",
            "operand_index": 0
          },
          {
            "address": 63200,
            "instruction_address": 7067,
            "instruction": "MOV:G.B R4, @H'F6E0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6E0",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63201,
        "name": "ram_F6E1",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7030,
        "last_access": 7044,
        "accesses": [
          {
            "address": 63201,
            "instruction_address": 7030,
            "instruction": "XOR.B @H'F6E1, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6E1",
            "operand_index": 0
          },
          {
            "address": 63201,
            "instruction_address": 7044,
            "instruction": "MOV:G.B R4, @H'F6E1",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6E1",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63202,
        "name": "ram_F6E2",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7120,
        "last_access": 7133,
        "accesses": [
          {
            "address": 63202,
            "instruction_address": 7120,
            "instruction": "XOR.B @H'F6E2, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6E2",
            "operand_index": 0
          },
          {
            "address": 63202,
            "instruction_address": 7133,
            "instruction": "MOV:G.B R4, @H'F6E2",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6E2",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63203,
        "name": "ram_F6E3",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7098,
        "last_access": 7111,
        "accesses": [
          {
            "address": 63203,
            "instruction_address": 7098,
            "instruction": "XOR.B @H'F6E3, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6E3",
            "operand_index": 0
          },
          {
            "address": 63203,
            "instruction_address": 7111,
            "instruction": "MOV:G.B R4, @H'F6E3",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6E3",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63204,
        "name": "ram_F6E4",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7076,
        "last_access": 7089,
        "accesses": [
          {
            "address": 63204,
            "instruction_address": 7076,
            "instruction": "XOR.B @H'F6E4, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6E4",
            "operand_index": 0
          },
          {
            "address": 63204,
            "instruction_address": 7089,
            "instruction": "MOV:G.B R4, @H'F6E4",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6E4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63205,
        "name": "ram_F6E5",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7007,
        "last_access": 7021,
        "accesses": [
          {
            "address": 63205,
            "instruction_address": 7007,
            "instruction": "XOR.B @H'F6E5, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6E5",
            "operand_index": 0
          },
          {
            "address": 63205,
            "instruction_address": 7021,
            "instruction": "MOV:G.B R4, @H'F6E5",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6E5",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63206,
        "name": "ram_F6E6",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6984,
        "last_access": 6998,
        "accesses": [
          {
            "address": 63206,
            "instruction_address": 6984,
            "instruction": "XOR.B @H'F6E6, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6E6",
            "operand_index": 0
          },
          {
            "address": 63206,
            "instruction_address": 6998,
            "instruction": "MOV:G.B R4, @H'F6E6",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6E6",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63207,
        "name": "ram_F6E7",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6961,
        "last_access": 6975,
        "accesses": [
          {
            "address": 63207,
            "instruction_address": 6961,
            "instruction": "XOR.B @H'F6E7, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6E7",
            "operand_index": 0
          },
          {
            "address": 63207,
            "instruction_address": 6975,
            "instruction": "MOV:G.B R4, @H'F6E7",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6E7",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63211,
        "name": "ram_F6EB",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7164,
        "last_access": 7177,
        "accesses": [
          {
            "address": 63211,
            "instruction_address": 7164,
            "instruction": "XOR.B @H'F6EB, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6EB",
            "operand_index": 0
          },
          {
            "address": 63211,
            "instruction_address": 7177,
            "instruction": "MOV:G.B R4, @H'F6EB",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6EB",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63212,
        "name": "ram_F6EC",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 7142,
        "last_access": 7155,
        "accesses": [
          {
            "address": 63212,
            "instruction_address": 7142,
            "instruction": "XOR.B @H'F6EC, R4",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6EC",
            "operand_index": 0
          },
          {
            "address": 63212,
            "instruction_address": 7155,
            "instruction": "MOV:G.B R4, @H'F6EC",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6EC",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63216,
        "name": "ram_F6F0",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 21,
        "read_count": 19,
        "write_count": 18,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 5625,
        "last_access": 15245,
        "accesses": [
          {
            "address": 63216,
            "instruction_address": 5625,
            "instruction": "TST.B @H'F6F0",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 0
          },
          {
            "address": 63216,
            "instruction_address": 5631,
            "instruction": "BCLR.B #7, @H'F6F0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 5640,
            "instruction": "BCLR.B #6, @H'F6F0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 5649,
            "instruction": "BCLR.B #5, @H'F6F0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 5658,
            "instruction": "BCLR.B #4, @H'F6F0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 5662,
            "instruction": "BCLR.B #3, @H'F6F0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 5671,
            "instruction": "BCLR.B #2, @H'F6F0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 5680,
            "instruction": "BCLR.B #1, @H'F6F0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 5689,
            "instruction": "BCLR.B #0, @H'F6F0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15072,
            "instruction": "MOV:G.B @H'F6F0, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 0
          },
          {
            "address": 63216,
            "instruction_address": 15079,
            "instruction": "MOV:G.B R0, @H'F6F0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15093,
            "instruction": "BSET.B #5, @H'F6F0",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15111,
            "instruction": "BSET.B #4, @H'F6F0",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15129,
            "instruction": "BSET.B #3, @H'F6F0",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15147,
            "instruction": "BSET.B #2, @H'F6F0",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15165,
            "instruction": "BSET.B #1, @H'F6F0",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15183,
            "instruction": "BSET.B #0, @H'F6F0",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15202,
            "instruction": "MOV:G.B @H'F6F0, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 0
          },
          {
            "address": 63216,
            "instruction_address": 15209,
            "instruction": "MOV:G.B R0, @H'F6F0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15227,
            "instruction": "BSET.B #7, @H'F6F0",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          },
          {
            "address": 63216,
            "instruction_address": 15245,
            "instruction": "BSET.B #6, @H'F6F0",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F0",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63217,
        "name": "ram_F6F1",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 21,
        "read_count": 19,
        "write_count": 18,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 5693,
        "last_access": 15606,
        "accesses": [
          {
            "address": 63217,
            "instruction_address": 5693,
            "instruction": "TST.B @H'F6F1",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 0
          },
          {
            "address": 63217,
            "instruction_address": 5699,
            "instruction": "BCLR.B #7, @H'F6F1",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 5708,
            "instruction": "BCLR.B #6, @H'F6F1",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 5717,
            "instruction": "BCLR.B #5, @H'F6F1",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 5726,
            "instruction": "BCLR.B #4, @H'F6F1",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 5735,
            "instruction": "BCLR.B #3, @H'F6F1",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 5744,
            "instruction": "BCLR.B #2, @H'F6F1",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 5753,
            "instruction": "BCLR.B #1, @H'F6F1",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 5762,
            "instruction": "BCLR.B #0, @H'F6F1",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15433,
            "instruction": "MOV:G.B @H'F6F1, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 0
          },
          {
            "address": 63217,
            "instruction_address": 15440,
            "instruction": "MOV:G.B R0, @H'F6F1",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15454,
            "instruction": "BSET.B #5, @H'F6F1",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15472,
            "instruction": "BSET.B #4, @H'F6F1",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15490,
            "instruction": "BSET.B #3, @H'F6F1",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15508,
            "instruction": "BSET.B #2, @H'F6F1",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15526,
            "instruction": "BSET.B #1, @H'F6F1",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15544,
            "instruction": "BSET.B #0, @H'F6F1",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15563,
            "instruction": "MOV:G.B @H'F6F1, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 0
          },
          {
            "address": 63217,
            "instruction_address": 15570,
            "instruction": "MOV:G.B R0, @H'F6F1",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15588,
            "instruction": "BSET.B #7, @H'F6F1",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          },
          {
            "address": 63217,
            "instruction_address": 15606,
            "instruction": "BSET.B #6, @H'F6F1",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F1",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63218,
        "name": "ram_F6F2",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 18,
        "read_count": 17,
        "write_count": 17,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 5766,
        "last_access": 15389,
        "accesses": [
          {
            "address": 63218,
            "instruction_address": 5766,
            "instruction": "TST.B @H'F6F2",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 0
          },
          {
            "address": 63218,
            "instruction_address": 5772,
            "instruction": "BCLR.B #7, @H'F6F2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 5781,
            "instruction": "BCLR.B #6, @H'F6F2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 5790,
            "instruction": "BCLR.B #5, @H'F6F2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 5799,
            "instruction": "BCLR.B #4, @H'F6F2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 5808,
            "instruction": "BCLR.B #3, @H'F6F2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 5817,
            "instruction": "BCLR.B #2, @H'F6F2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 5826,
            "instruction": "BCLR.B #1, @H'F6F2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 5835,
            "instruction": "BCLR.B #0, @H'F6F2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 15213,
            "instruction": "CLR.B @H'F6F2",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 0
          },
          {
            "address": 63218,
            "instruction_address": 15263,
            "instruction": "BSET.B #0, @H'F6F2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 15281,
            "instruction": "BSET.B #1, @H'F6F2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 15299,
            "instruction": "BSET.B #2, @H'F6F2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 15317,
            "instruction": "BSET.B #3, @H'F6F2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 15335,
            "instruction": "BSET.B #4, @H'F6F2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 15353,
            "instruction": "BSET.B #5, @H'F6F2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 15371,
            "instruction": "BSET.B #6, @H'F6F2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          },
          {
            "address": 63218,
            "instruction_address": 15389,
            "instruction": "BSET.B #7, @H'F6F2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F2",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63219,
        "name": "ram_F6F3",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 18,
        "read_count": 17,
        "write_count": 17,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 5844,
        "last_access": 15750,
        "accesses": [
          {
            "address": 63219,
            "instruction_address": 5844,
            "instruction": "TST.B @H'F6F3",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 0
          },
          {
            "address": 63219,
            "instruction_address": 5850,
            "instruction": "BCLR.B #7, @H'F6F3",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 5854,
            "instruction": "BCLR.B #6, @H'F6F3",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 5858,
            "instruction": "BCLR.B #5, @H'F6F3",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 5862,
            "instruction": "BCLR.B #4, @H'F6F3",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 5871,
            "instruction": "BCLR.B #3, @H'F6F3",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 5880,
            "instruction": "BCLR.B #2, @H'F6F3",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 5884,
            "instruction": "BCLR.B #1, @H'F6F3",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 5888,
            "instruction": "BCLR.B #0, @H'F6F3",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 15574,
            "instruction": "CLR.B @H'F6F3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 0
          },
          {
            "address": 63219,
            "instruction_address": 15624,
            "instruction": "BSET.B #0, @H'F6F3",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 15642,
            "instruction": "BSET.B #1, @H'F6F3",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 15660,
            "instruction": "BSET.B #2, @H'F6F3",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 15678,
            "instruction": "BSET.B #3, @H'F6F3",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 15696,
            "instruction": "BSET.B #4, @H'F6F3",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 15714,
            "instruction": "BSET.B #5, @H'F6F3",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 15732,
            "instruction": "BSET.B #6, @H'F6F3",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          },
          {
            "address": 63219,
            "instruction_address": 15750,
            "instruction": "BSET.B #7, @H'F6F3",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F3",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63220,
        "name": "ram_F6F4",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 2,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 9905,
        "last_access": 48926,
        "accesses": [
          {
            "address": 63220,
            "instruction_address": 9905,
            "instruction": "MOV:G.W #H'07D0, @H'F6F4",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6F4",
            "operand_index": 1
          },
          {
            "address": 63220,
            "instruction_address": 9913,
            "instruction": "MOV:G.W #H'00C8, @H'F6F4",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F6F4",
            "operand_index": 1
          },
          {
            "address": 63220,
            "instruction_address": 48914,
            "instruction": "TST.W @H'F6F4",
            "mnemonic": "TST.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F6F4",
            "operand_index": 0
          },
          {
            "address": 63220,
            "instruction_address": 48926,
            "instruction": "ADD:Q.W #-1, @H'F6F4",
            "mnemonic": "ADD:Q.W",
            "direction": "read_write",
            "width": "word",
            "operand": "@H'F6F4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63222,
        "name": "ram_F6F6",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 5,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 9808,
        "last_access": 48920,
        "accesses": [
          {
            "address": 63222,
            "instruction_address": 9808,
            "instruction": "BCLR.B #5, @H'F6F6",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F6",
            "operand_index": 1
          },
          {
            "address": 63222,
            "instruction_address": 9823,
            "instruction": "BTST.B #6, @H'F6F6",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F6",
            "operand_index": 1
          },
          {
            "address": 63222,
            "instruction_address": 9899,
            "instruction": "BSET.B #0, @H'F6F6",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F6",
            "operand_index": 1
          },
          {
            "address": 63222,
            "instruction_address": 48908,
            "instruction": "BTST.B #7, @H'F6F6",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F6",
            "operand_index": 1
          },
          {
            "address": 63222,
            "instruction_address": 48920,
            "instruction": "BSET.B #5, @H'F6F6",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F6F6",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63223,
        "name": "ram_F6F7",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 1,
        "write_count": 4,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16613,
        "last_access": 17486,
        "accesses": [
          {
            "address": 63223,
            "instruction_address": 16613,
            "instruction": "MOV:G.B #H'80, @H'F6F7",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F7",
            "operand_index": 1
          },
          {
            "address": 63223,
            "instruction_address": 17455,
            "instruction": "ADD:G.B @H'F6F7, R4",
            "mnemonic": "ADD:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F7",
            "operand_index": 0
          },
          {
            "address": 63223,
            "instruction_address": 17467,
            "instruction": "MOV:G.B R4, @H'F6F7",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F7",
            "operand_index": 1
          },
          {
            "address": 63223,
            "instruction_address": 17476,
            "instruction": "MOV:G.B #H'80, @H'F6F7",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F7",
            "operand_index": 1
          },
          {
            "address": 63223,
            "instruction_address": 17486,
            "instruction": "MOV:G.B #H'80, @H'F6F7",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F7",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63224,
        "name": "ram_F6F8",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 1,
        "write_count": 4,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16618,
        "last_access": 17681,
        "accesses": [
          {
            "address": 63224,
            "instruction_address": 16618,
            "instruction": "MOV:G.B #H'80, @H'F6F8",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F8",
            "operand_index": 1
          },
          {
            "address": 63224,
            "instruction_address": 17650,
            "instruction": "ADD:G.B @H'F6F8, R4",
            "mnemonic": "ADD:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F8",
            "operand_index": 0
          },
          {
            "address": 63224,
            "instruction_address": 17662,
            "instruction": "MOV:G.B R4, @H'F6F8",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F8",
            "operand_index": 1
          },
          {
            "address": 63224,
            "instruction_address": 17671,
            "instruction": "MOV:G.B #H'80, @H'F6F8",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F8",
            "operand_index": 1
          },
          {
            "address": 63224,
            "instruction_address": 17681,
            "instruction": "MOV:G.B #H'80, @H'F6F8",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F8",
            "operand_index": 1
          }
        ],
        "xref_count": 2,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 6686,
            "target": 63224
          },
          {
            "source": "pointer_table",
            "address": 53384,
            "target": 63224
          }
        ]
      },
      {
        "address": 63225,
        "name": "ram_F6F9",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 1,
        "write_count": 4,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16623,
        "last_access": 17876,
        "accesses": [
          {
            "address": 63225,
            "instruction_address": 16623,
            "instruction": "MOV:G.B #H'80, @H'F6F9",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F9",
            "operand_index": 1
          },
          {
            "address": 63225,
            "instruction_address": 17845,
            "instruction": "ADD:G.B @H'F6F9, R4",
            "mnemonic": "ADD:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F6F9",
            "operand_index": 0
          },
          {
            "address": 63225,
            "instruction_address": 17857,
            "instruction": "MOV:G.B R4, @H'F6F9",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F9",
            "operand_index": 1
          },
          {
            "address": 63225,
            "instruction_address": 17866,
            "instruction": "MOV:G.B #H'80, @H'F6F9",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F9",
            "operand_index": 1
          },
          {
            "address": 63225,
            "instruction_address": 17876,
            "instruction": "MOV:G.B #H'80, @H'F6F9",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F6F9",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63232,
        "name": "ram_F700",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 14856,
        "last_access": 16931,
        "accesses": [
          {
            "address": 63232,
            "instruction_address": 14856,
            "instruction": "MOV:G.B @H'F700, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F700",
            "operand_index": 0
          },
          {
            "address": 63232,
            "instruction_address": 16931,
            "instruction": "MOV:G.W #H'2424, @H'F700",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F700",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63233,
        "name": "ram_F701",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14864,
        "last_access": 14864,
        "accesses": [
          {
            "address": 63233,
            "instruction_address": 14864,
            "instruction": "MOV:G.B @H'F701, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F701",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63234,
        "name": "ram_F702",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 14824,
        "last_access": 16937,
        "accesses": [
          {
            "address": 63234,
            "instruction_address": 14824,
            "instruction": "MOV:G.B @H'F702, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F702",
            "operand_index": 0
          },
          {
            "address": 63234,
            "instruction_address": 16937,
            "instruction": "MOV:G.W #H'2424, @H'F702",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F702",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63235,
        "name": "ram_F703",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14832,
        "last_access": 14832,
        "accesses": [
          {
            "address": 63235,
            "instruction_address": 14832,
            "instruction": "MOV:G.B @H'F703, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F703",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63236,
        "name": "ram_F704",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 14840,
        "last_access": 16943,
        "accesses": [
          {
            "address": 63236,
            "instruction_address": 14840,
            "instruction": "MOV:G.B @H'F704, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F704",
            "operand_index": 0
          },
          {
            "address": 63236,
            "instruction_address": 16943,
            "instruction": "MOV:G.W #H'2424, @H'F704",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F704",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63237,
        "name": "ram_F705",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14848,
        "last_access": 14848,
        "accesses": [
          {
            "address": 63237,
            "instruction_address": 14848,
            "instruction": "MOV:G.B @H'F705, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F705",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63238,
        "name": "ram_F706",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 15009,
        "last_access": 16949,
        "accesses": [
          {
            "address": 63238,
            "instruction_address": 15009,
            "instruction": "MOV:G.B @H'F706, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F706",
            "operand_index": 0
          },
          {
            "address": 63238,
            "instruction_address": 16949,
            "instruction": "MOV:G.W #H'2424, @H'F706",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F706",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63239,
        "name": "ram_F707",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15017,
        "last_access": 15017,
        "accesses": [
          {
            "address": 63239,
            "instruction_address": 15017,
            "instruction": "MOV:G.B @H'F707, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F707",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63240,
        "name": "ram_F708",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14977,
        "last_access": 16955,
        "accesses": [
          {
            "address": 63240,
            "instruction_address": 14977,
            "instruction": "MOV:G.B @H'F708, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F708",
            "operand_index": 0
          },
          {
            "address": 63240,
            "instruction_address": 16955,
            "instruction": "MOV:G.B #H'7F, @H'F708",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F708",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63241,
        "name": "ram_F709",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14985,
        "last_access": 16960,
        "accesses": [
          {
            "address": 63241,
            "instruction_address": 14985,
            "instruction": "MOV:G.B @H'F709, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F709",
            "operand_index": 0
          },
          {
            "address": 63241,
            "instruction_address": 16960,
            "instruction": "MOV:G.B #H'24, @H'F709",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F709",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63242,
        "name": "ram_F70A",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 14993,
        "last_access": 16965,
        "accesses": [
          {
            "address": 63242,
            "instruction_address": 14993,
            "instruction": "MOV:G.B @H'F70A, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F70A",
            "operand_index": 0
          },
          {
            "address": 63242,
            "instruction_address": 16965,
            "instruction": "MOV:G.W #H'2424, @H'F70A",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F70A",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63243,
        "name": "ram_F70B",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15001,
        "last_access": 15001,
        "accesses": [
          {
            "address": 63243,
            "instruction_address": 15001,
            "instruction": "MOV:G.B @H'F70B, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F70B",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63248,
        "name": "ram_F710",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14816,
        "last_access": 16971,
        "accesses": [
          {
            "address": 63248,
            "instruction_address": 14816,
            "instruction": "AND.B @H'F710, R0",
            "mnemonic": "AND.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F710",
            "operand_index": 0
          },
          {
            "address": 63248,
            "instruction_address": 16971,
            "instruction": "CLR.B @H'F710",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F710",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63249,
        "name": "ram_F711",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 6,
        "read_count": 5,
        "write_count": 5,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14800,
        "last_access": 49055,
        "accesses": [
          {
            "address": 63249,
            "instruction_address": 14800,
            "instruction": "AND.B @H'F711, R0",
            "mnemonic": "AND.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F711",
            "operand_index": 0
          },
          {
            "address": 63249,
            "instruction_address": 16975,
            "instruction": "CLR.B @H'F711",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F711",
            "operand_index": 0
          },
          {
            "address": 63249,
            "instruction_address": 49043,
            "instruction": "BCLR.B #7, @H'F711",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F711",
            "operand_index": 1
          },
          {
            "address": 63249,
            "instruction_address": 49047,
            "instruction": "BCLR.B #6, @H'F711",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F711",
            "operand_index": 1
          },
          {
            "address": 63249,
            "instruction_address": 49051,
            "instruction": "BCLR.B #5, @H'F711",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F711",
            "operand_index": 1
          },
          {
            "address": 63249,
            "instruction_address": 49055,
            "instruction": "BCLR.B #4, @H'F711",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F711",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63250,
        "name": "ram_F712",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14784,
        "last_access": 16979,
        "accesses": [
          {
            "address": 63250,
            "instruction_address": 14784,
            "instruction": "AND.B @H'F712, R0",
            "mnemonic": "AND.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F712",
            "operand_index": 0
          },
          {
            "address": 63250,
            "instruction_address": 16979,
            "instruction": "CLR.B @H'F712",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F712",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63251,
        "name": "ram_F713",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14768,
        "last_access": 49037,
        "accesses": [
          {
            "address": 63251,
            "instruction_address": 14768,
            "instruction": "AND.B @H'F713, R0",
            "mnemonic": "AND.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F713",
            "operand_index": 0
          },
          {
            "address": 63251,
            "instruction_address": 16983,
            "instruction": "CLR.B @H'F713",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F713",
            "operand_index": 0
          },
          {
            "address": 63251,
            "instruction_address": 49037,
            "instruction": "BCLR.B #6, @H'F713",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F713",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63252,
        "name": "ram_F714",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14969,
        "last_access": 16987,
        "accesses": [
          {
            "address": 63252,
            "instruction_address": 14969,
            "instruction": "AND.B @H'F714, R0",
            "mnemonic": "AND.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F714",
            "operand_index": 0
          },
          {
            "address": 63252,
            "instruction_address": 16987,
            "instruction": "CLR.B @H'F714",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F714",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63253,
        "name": "ram_F715",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14953,
        "last_access": 16991,
        "accesses": [
          {
            "address": 63253,
            "instruction_address": 14953,
            "instruction": "AND.B @H'F715, R0",
            "mnemonic": "AND.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F715",
            "operand_index": 0
          },
          {
            "address": 63253,
            "instruction_address": 16991,
            "instruction": "CLR.B @H'F715",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F715",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63254,
        "name": "ram_F716",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14937,
        "last_access": 16995,
        "accesses": [
          {
            "address": 63254,
            "instruction_address": 14937,
            "instruction": "AND.B @H'F716, R0",
            "mnemonic": "AND.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F716",
            "operand_index": 0
          },
          {
            "address": 63254,
            "instruction_address": 16995,
            "instruction": "CLR.B @H'F716",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F716",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63255,
        "name": "ram_F717",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 4,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6189,
        "last_access": 16999,
        "accesses": [
          {
            "address": 63255,
            "instruction_address": 6189,
            "instruction": "BTST.B #2, @H'F717",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F717",
            "operand_index": 1
          },
          {
            "address": 63255,
            "instruction_address": 6289,
            "instruction": "BTST.B #2, @H'F717",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F717",
            "operand_index": 1
          },
          {
            "address": 63255,
            "instruction_address": 6375,
            "instruction": "BTST.B #2, @H'F717",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F717",
            "operand_index": 1
          },
          {
            "address": 63255,
            "instruction_address": 14921,
            "instruction": "AND.B @H'F717, R0",
            "mnemonic": "AND.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F717",
            "operand_index": 0
          },
          {
            "address": 63255,
            "instruction_address": 16999,
            "instruction": "CLR.B @H'F717",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F717",
            "operand_index": 0
          }
        ],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 13788,
            "target": 63255
          }
        ]
      },
      {
        "address": 63256,
        "name": "ram_F718",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14808,
        "last_access": 17003,
        "accesses": [
          {
            "address": 63256,
            "instruction_address": 14808,
            "instruction": "MOV:G.B @H'F718, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F718",
            "operand_index": 0
          },
          {
            "address": 63256,
            "instruction_address": 17003,
            "instruction": "MOV:G.B #H'FF, @H'F718",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F718",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63257,
        "name": "ram_F719",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14792,
        "last_access": 17008,
        "accesses": [
          {
            "address": 63257,
            "instruction_address": 14792,
            "instruction": "MOV:G.B @H'F719, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F719",
            "operand_index": 0
          },
          {
            "address": 63257,
            "instruction_address": 17008,
            "instruction": "MOV:G.B #H'FF, @H'F719",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F719",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63258,
        "name": "ram_F71A",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14776,
        "last_access": 17013,
        "accesses": [
          {
            "address": 63258,
            "instruction_address": 14776,
            "instruction": "MOV:G.B @H'F71A, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F71A",
            "operand_index": 0
          },
          {
            "address": 63258,
            "instruction_address": 17013,
            "instruction": "MOV:G.B #H'FF, @H'F71A",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F71A",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63259,
        "name": "ram_F71B",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14760,
        "last_access": 17018,
        "accesses": [
          {
            "address": 63259,
            "instruction_address": 14760,
            "instruction": "MOV:G.B @H'F71B, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F71B",
            "operand_index": 0
          },
          {
            "address": 63259,
            "instruction_address": 17018,
            "instruction": "MOV:G.B #H'FF, @H'F71B",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F71B",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63260,
        "name": "ram_F71C",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14961,
        "last_access": 17023,
        "accesses": [
          {
            "address": 63260,
            "instruction_address": 14961,
            "instruction": "MOV:G.B @H'F71C, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F71C",
            "operand_index": 0
          },
          {
            "address": 63260,
            "instruction_address": 17023,
            "instruction": "MOV:G.B #H'FF, @H'F71C",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F71C",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63261,
        "name": "ram_F71D",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14945,
        "last_access": 17028,
        "accesses": [
          {
            "address": 63261,
            "instruction_address": 14945,
            "instruction": "MOV:G.B @H'F71D, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F71D",
            "operand_index": 0
          },
          {
            "address": 63261,
            "instruction_address": 17028,
            "instruction": "MOV:G.B #H'FF, @H'F71D",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F71D",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63262,
        "name": "ram_F71E",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14929,
        "last_access": 17033,
        "accesses": [
          {
            "address": 63262,
            "instruction_address": 14929,
            "instruction": "MOV:G.B @H'F71E, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F71E",
            "operand_index": 0
          },
          {
            "address": 63262,
            "instruction_address": 17033,
            "instruction": "MOV:G.B #H'FF, @H'F71E",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F71E",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63263,
        "name": "ram_F71F",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14913,
        "last_access": 17038,
        "accesses": [
          {
            "address": 63263,
            "instruction_address": 14913,
            "instruction": "MOV:G.B @H'F71F, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F71F",
            "operand_index": 0
          },
          {
            "address": 63263,
            "instruction_address": 17038,
            "instruction": "MOV:G.B #H'FF, @H'F71F",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F71F",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63264,
        "name": "ram_F720",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14741,
        "last_access": 15401,
        "accesses": [
          {
            "address": 63264,
            "instruction_address": 14741,
            "instruction": "TST.B @H'F720",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F720",
            "operand_index": 0
          },
          {
            "address": 63264,
            "instruction_address": 14888,
            "instruction": "MOV:G.B #H'03, @H'F720",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F720",
            "operand_index": 1
          },
          {
            "address": 63264,
            "instruction_address": 15195,
            "instruction": "BCLR.B #0, @H'F720",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F720",
            "operand_index": 1
          },
          {
            "address": 63264,
            "instruction_address": 15401,
            "instruction": "BCLR.B #1, @H'F720",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F720",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63265,
        "name": "ram_F721",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14894,
        "last_access": 15762,
        "accesses": [
          {
            "address": 63265,
            "instruction_address": 14894,
            "instruction": "TST.B @H'F721",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F721",
            "operand_index": 0
          },
          {
            "address": 63265,
            "instruction_address": 15041,
            "instruction": "MOV:G.B #H'03, @H'F721",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F721",
            "operand_index": 1
          },
          {
            "address": 63265,
            "instruction_address": 15556,
            "instruction": "BCLR.B #0, @H'F721",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F721",
            "operand_index": 1
          },
          {
            "address": 63265,
            "instruction_address": 15762,
            "instruction": "BCLR.B #1, @H'F721",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F721",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63266,
        "name": "ram_F722",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 4,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14690,
        "last_access": 14725,
        "accesses": [
          {
            "address": 63266,
            "instruction_address": 14690,
            "instruction": "ADD:Q.B #1, @H'F722",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F722",
            "operand_index": 1
          },
          {
            "address": 63266,
            "instruction_address": 14694,
            "instruction": "CMP:G.B #H'3C, @H'F722",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F722",
            "operand_index": 1
          },
          {
            "address": 63266,
            "instruction_address": 14701,
            "instruction": "CMP:G.B #H'78, @H'F722",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F722",
            "operand_index": 1
          },
          {
            "address": 63266,
            "instruction_address": 14708,
            "instruction": "CMP:G.B #H'B4, @H'F722",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F722",
            "operand_index": 1
          },
          {
            "address": 63266,
            "instruction_address": 14725,
            "instruction": "CLR.B @H'F722",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F722",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63267,
        "name": "ram_F723",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 9,
        "read_count": 9,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 14764,
        "last_access": 48972,
        "accesses": [
          {
            "address": 63267,
            "instruction_address": 14764,
            "instruction": "OR.B @H'F723, R0",
            "mnemonic": "OR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F723",
            "operand_index": 0
          },
          {
            "address": 63267,
            "instruction_address": 14780,
            "instruction": "OR.B @H'F723, R0",
            "mnemonic": "OR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F723",
            "operand_index": 0
          },
          {
            "address": 63267,
            "instruction_address": 14796,
            "instruction": "OR.B @H'F723, R0",
            "mnemonic": "OR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F723",
            "operand_index": 0
          },
          {
            "address": 63267,
            "instruction_address": 14812,
            "instruction": "OR.B @H'F723, R0",
            "mnemonic": "OR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F723",
            "operand_index": 0
          },
          {
            "address": 63267,
            "instruction_address": 14917,
            "instruction": "OR.B @H'F723, R0",
            "mnemonic": "OR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F723",
            "operand_index": 0
          },
          {
            "address": 63267,
            "instruction_address": 14933,
            "instruction": "OR.B @H'F723, R0",
            "mnemonic": "OR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F723",
            "operand_index": 0
          },
          {
            "address": 63267,
            "instruction_address": 14949,
            "instruction": "OR.B @H'F723, R0",
            "mnemonic": "OR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F723",
            "operand_index": 0
          },
          {
            "address": 63267,
            "instruction_address": 14965,
            "instruction": "OR.B @H'F723, R0",
            "mnemonic": "OR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F723",
            "operand_index": 0
          },
          {
            "address": 63267,
            "instruction_address": 48972,
            "instruction": "NOT.B @H'F723",
            "mnemonic": "NOT.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F723",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63268,
        "name": "ram_F724",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 48955,
        "last_access": 48967,
        "accesses": [
          {
            "address": 63268,
            "instruction_address": 48955,
            "instruction": "TST.B @H'F724",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F724",
            "operand_index": 0
          },
          {
            "address": 63268,
            "instruction_address": 48961,
            "instruction": "ADD:Q.B #-1, @H'F724",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F724",
            "operand_index": 1
          },
          {
            "address": 63268,
            "instruction_address": 48967,
            "instruction": "MOV:G.B #H'03, @H'F724",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F724",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63270,
        "name": "ram_F726",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 49025,
        "last_access": 49031,
        "accesses": [
          {
            "address": 63270,
            "instruction_address": 49025,
            "instruction": "TST.B @H'F726",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F726",
            "operand_index": 0
          },
          {
            "address": 63270,
            "instruction_address": 49031,
            "instruction": "ADD:Q.B #-1, @H'F726",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F726",
            "operand_index": 1
          }
        ],
        "xref_count": 2,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 13216,
            "target": 63270
          },
          {
            "source": "pointer_table",
            "address": 18602,
            "target": 63270
          }
        ]
      },
      {
        "address": 63271,
        "name": "ram_F727",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 0,
        "read_count": 0,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [],
        "width": null,
        "first_access": null,
        "last_access": null,
        "accesses": [],
        "xref_count": 2,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 7856,
            "target": 63271
          },
          {
            "source": "pointer_table",
            "address": 13432,
            "target": 63271
          }
        ]
      },
      {
        "address": 63280,
        "name": "ram_F730",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 5906,
        "last_access": 16396,
        "accesses": [
          {
            "address": 63280,
            "instruction_address": 5906,
            "instruction": "BTST.B #6, @H'F730",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F730",
            "operand_index": 1
          },
          {
            "address": 63280,
            "instruction_address": 5972,
            "instruction": "BTST.B #7, @H'F730",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F730",
            "operand_index": 1
          },
          {
            "address": 63280,
            "instruction_address": 16396,
            "instruction": "CLR.B @H'F730",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F730",
            "operand_index": 0
          }
        ],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 7856,
            "target": 63280
          }
        ]
      },
      {
        "address": 63281,
        "name": "ram_F731",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 22,
        "read_count": 22,
        "write_count": 4,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 5893,
        "last_access": 49087,
        "accesses": [
          {
            "address": 63281,
            "instruction_address": 5893,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 5965,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6037,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6089,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6139,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6195,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6245,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6295,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6331,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6381,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6431,
            "instruction": "CMP:G.B #H'02, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6474,
            "instruction": "CMP:G.B #H'03, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 6521,
            "instruction": "CMP:G.B #H'03, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 15813,
            "instruction": "CMP:G.B #H'03, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 16923,
            "instruction": "BSET.B #7, @H'F731",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 17300,
            "instruction": "CMP:G.B #H'01, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 17495,
            "instruction": "CMP:G.B #H'01, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 17690,
            "instruction": "CMP:G.B #H'01, @H'F731",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 48532,
            "instruction": "BTST.B #7, @H'F731",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 48565,
            "instruction": "BCLR.B #7, @H'F731",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 49071,
            "instruction": "BCLR.B #7, @H'F731",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          },
          {
            "address": 63281,
            "instruction_address": 49087,
            "instruction": "BCLR.B #7, @H'F731",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F731",
            "operand_index": 1
          }
        ],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 7856,
            "target": 63281
          }
        ]
      },
      {
        "address": 63282,
        "name": "ram_F732",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 11,
        "read_count": 6,
        "write_count": 5,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 5918,
        "last_access": 18735,
        "accesses": [
          {
            "address": 63282,
            "instruction_address": 5918,
            "instruction": "MOV:G.W @H'F732, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F732",
            "operand_index": 0
          },
          {
            "address": 63282,
            "instruction_address": 5926,
            "instruction": "MOV:G.W #H'1C07, @H'F732",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F732",
            "operand_index": 1
          },
          {
            "address": 63282,
            "instruction_address": 5990,
            "instruction": "MOV:G.W @H'F732, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F732",
            "operand_index": 0
          },
          {
            "address": 63282,
            "instruction_address": 5998,
            "instruction": "MOV:G.W #H'1C06, @H'F732",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F732",
            "operand_index": 1
          },
          {
            "address": 63282,
            "instruction_address": 8493,
            "instruction": "MOV:G.W @H'F732, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F732",
            "operand_index": 0
          },
          {
            "address": 63282,
            "instruction_address": 8501,
            "instruction": "MOV:G.W #H'1C03, @H'F732",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F732",
            "operand_index": 1
          },
          {
            "address": 63282,
            "instruction_address": 16416,
            "instruction": "CLR.W @H'F732",
            "mnemonic": "CLR.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F732",
            "operand_index": 0
          },
          {
            "address": 63282,
            "instruction_address": 18675,
            "instruction": "MOV:G.W R0, @H'F732",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F732",
            "operand_index": 1
          },
          {
            "address": 63282,
            "instruction_address": 18688,
            "instruction": "CMP:G.B #H'1A, @H'F732",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F732",
            "operand_index": 1
          },
          {
            "address": 63282,
            "instruction_address": 18695,
            "instruction": "CMP:G.W #H'1900, @H'F732",
            "mnemonic": "CMP:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F732",
            "operand_index": 1
          },
          {
            "address": 63282,
            "instruction_address": 18735,
            "instruction": "MOV:G.B @H'F732, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F732",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63283,
        "name": "ram_F733",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6818,
        "last_access": 6876,
        "accesses": [
          {
            "address": 63283,
            "instruction_address": 6818,
            "instruction": "MOV:G.B @H'F733, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F733",
            "operand_index": 0
          },
          {
            "address": 63283,
            "instruction_address": 6860,
            "instruction": "MOV:G.B R0, @H'F733",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F733",
            "operand_index": 1
          },
          {
            "address": 63283,
            "instruction_address": 6870,
            "instruction": "ADD:Q.B #1, @H'F733",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F733",
            "operand_index": 1
          },
          {
            "address": 63283,
            "instruction_address": 6876,
            "instruction": "ADD:Q.B #-1, @H'F733",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F733",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63284,
        "name": "ram_F734",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 1,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 5922,
        "last_access": 18671,
        "accesses": [
          {
            "address": 63284,
            "instruction_address": 5922,
            "instruction": "MOV:G.W R1, @H'F734",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F734",
            "operand_index": 1
          },
          {
            "address": 63284,
            "instruction_address": 5994,
            "instruction": "MOV:G.W R1, @H'F734",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F734",
            "operand_index": 1
          },
          {
            "address": 63284,
            "instruction_address": 8497,
            "instruction": "MOV:G.W R1, @H'F734",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F734",
            "operand_index": 1
          },
          {
            "address": 63284,
            "instruction_address": 18671,
            "instruction": "MOV:G.W @H'F734, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F734",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63286,
        "name": "ram_F736",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 10295,
        "last_access": 17315,
        "accesses": [
          {
            "address": 63286,
            "instruction_address": 10295,
            "instruction": "MOV:G.W @H'F736, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F736",
            "operand_index": 0
          },
          {
            "address": 63286,
            "instruction_address": 17315,
            "instruction": "MOV:G.W @H'F736, R3",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F736",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63288,
        "name": "ram_F738",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 10308,
        "last_access": 17510,
        "accesses": [
          {
            "address": 63288,
            "instruction_address": 10308,
            "instruction": "MOV:G.W @H'F738, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F738",
            "operand_index": 0
          },
          {
            "address": 63288,
            "instruction_address": 17510,
            "instruction": "MOV:G.W @H'F738, R3",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F738",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63290,
        "name": "ram_F73A",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 10321,
        "last_access": 17705,
        "accesses": [
          {
            "address": 63290,
            "instruction_address": 10321,
            "instruction": "MOV:G.W @H'F73A, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F73A",
            "operand_index": 0
          },
          {
            "address": 63290,
            "instruction_address": 17705,
            "instruction": "MOV:G.W @H'F73A, R3",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F73A",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63292,
        "name": "ram_F73C",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 10334,
        "last_access": 10334,
        "accesses": [
          {
            "address": 63292,
            "instruction_address": 10334,
            "instruction": "MOV:G.W @H'F73C, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F73C",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63294,
        "name": "ram_F73E",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 10347,
        "last_access": 10347,
        "accesses": [
          {
            "address": 63294,
            "instruction_address": 10347,
            "instruction": "MOV:G.W @H'F73E, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F73E",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63296,
        "name": "ram_F740",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 10360,
        "last_access": 10360,
        "accesses": [
          {
            "address": 63296,
            "instruction_address": 10360,
            "instruction": "MOV:G.W @H'F740, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F740",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63298,
        "name": "ram_F742",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 10373,
        "last_access": 10373,
        "accesses": [
          {
            "address": 63298,
            "instruction_address": 10373,
            "instruction": "MOV:G.W @H'F742, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F742",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63308,
        "name": "ram_F74C",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 0,
        "read_count": 0,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [],
        "width": null,
        "first_access": null,
        "last_access": null,
        "accesses": [],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 23074,
            "target": 63308
          }
        ]
      },
      {
        "address": 63312,
        "name": "ram_F750",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 0,
        "read_count": 0,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [],
        "width": null,
        "first_access": null,
        "last_access": null,
        "accesses": [],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 18072,
            "target": 63312
          }
        ]
      },
      {
        "address": 63314,
        "name": "ram_F752",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 0,
        "read_count": 0,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [],
        "width": null,
        "first_access": null,
        "last_access": null,
        "accesses": [],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 18350,
            "target": 63314
          }
        ]
      },
      {
        "address": 63316,
        "name": "ram_F754",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 10386,
        "last_access": 10386,
        "accesses": [
          {
            "address": 63316,
            "instruction_address": 10386,
            "instruction": "MOV:G.W @H'F754, R1",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F754",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63318,
        "name": "ram_F756",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16400,
        "last_access": 16400,
        "accesses": [
          {
            "address": 63318,
            "instruction_address": 16400,
            "instruction": "CLR.B @H'F756",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F756",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63319,
        "name": "ram_F757",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16404,
        "last_access": 16404,
        "accesses": [
          {
            "address": 63319,
            "instruction_address": 16404,
            "instruction": "CLR.B @H'F757",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F757",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63320,
        "name": "ram_F758",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16408,
        "last_access": 16408,
        "accesses": [
          {
            "address": 63320,
            "instruction_address": 16408,
            "instruction": "CLR.B @H'F758",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F758",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63321,
        "name": "ram_F759",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16412,
        "last_access": 16412,
        "accesses": [
          {
            "address": 63321,
            "instruction_address": 16412,
            "instruction": "CLR.B @H'F759",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F759",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63323,
        "name": "ram_F75B",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6884,
        "last_access": 6949,
        "accesses": [
          {
            "address": 63323,
            "instruction_address": 6884,
            "instruction": "MOV:G.B @H'F75B, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F75B",
            "operand_index": 0
          },
          {
            "address": 63323,
            "instruction_address": 6923,
            "instruction": "MOV:G.B @H'F75B, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F75B",
            "operand_index": 0
          },
          {
            "address": 63323,
            "instruction_address": 6949,
            "instruction": "MOV:G.B R0, @H'F75B",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F75B",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63324,
        "name": "ram_F75C",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 16420,
        "last_access": 16420,
        "accesses": [
          {
            "address": 63324,
            "instruction_address": 16420,
            "instruction": "CLR.W @H'F75C",
            "mnemonic": "CLR.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F75C",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63337,
        "name": "ram_F769",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 11430,
        "last_access": 11442,
        "accesses": [
          {
            "address": 63337,
            "instruction_address": 11430,
            "instruction": "BCLR.B #7, @H'F769",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F769",
            "operand_index": 1
          },
          {
            "address": 63337,
            "instruction_address": 11442,
            "instruction": "BSET.B #7, @H'F769",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F769",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63338,
        "name": "ram_F76A",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 16432,
        "last_access": 16432,
        "accesses": [
          {
            "address": 63338,
            "instruction_address": 16432,
            "instruction": "CLR.W @H'F76A",
            "mnemonic": "CLR.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F76A",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63340,
        "name": "ram_F76C",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 49005,
        "last_access": 49011,
        "accesses": [
          {
            "address": 63340,
            "instruction_address": 49005,
            "instruction": "TST.B @H'F76C",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F76C",
            "operand_index": 0
          },
          {
            "address": 63340,
            "instruction_address": 49011,
            "instruction": "ADD:Q.B #-1, @H'F76C",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F76C",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63341,
        "name": "ram_F76D",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6508,
        "last_access": 6508,
        "accesses": [
          {
            "address": 63341,
            "instruction_address": 6508,
            "instruction": "BSET.B #7, @H'F76D",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F76D",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63342,
        "name": "ram_F76E",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16444,
        "last_access": 48465,
        "accesses": [
          {
            "address": 63342,
            "instruction_address": 16444,
            "instruction": "CLR.B @H'F76E",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F76E",
            "operand_index": 0
          },
          {
            "address": 63342,
            "instruction_address": 18729,
            "instruction": "BTST.B #6, @H'F76E",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F76E",
            "operand_index": 1
          },
          {
            "address": 63342,
            "instruction_address": 48457,
            "instruction": "BTST.B #7, @H'F76E",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F76E",
            "operand_index": 1
          },
          {
            "address": 63342,
            "instruction_address": 48465,
            "instruction": "MOV:G.B @H'F76E, R4",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F76E",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63344,
        "name": "ram_F770",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 6,
        "read_count": 0,
        "write_count": 6,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 17407,
        "last_access": 17818,
        "accesses": [
          {
            "address": 63344,
            "instruction_address": 17407,
            "instruction": "MOV:G.B #H'80, @H'F770",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F770",
            "operand_index": 1
          },
          {
            "address": 63344,
            "instruction_address": 17428,
            "instruction": "MOV:G.B #H'80, @H'F770",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F770",
            "operand_index": 1
          },
          {
            "address": 63344,
            "instruction_address": 17602,
            "instruction": "MOV:G.B #H'40, @H'F770",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F770",
            "operand_index": 1
          },
          {
            "address": 63344,
            "instruction_address": 17623,
            "instruction": "MOV:G.B #H'40, @H'F770",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F770",
            "operand_index": 1
          },
          {
            "address": 63344,
            "instruction_address": 17797,
            "instruction": "MOV:G.B #H'20, @H'F770",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F770",
            "operand_index": 1
          },
          {
            "address": 63344,
            "instruction_address": 17818,
            "instruction": "MOV:G.B #H'20, @H'F770",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F770",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63346,
        "name": "ram_F772",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 6,
        "read_count": 0,
        "write_count": 6,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 17412,
        "last_access": 17823,
        "accesses": [
          {
            "address": 63346,
            "instruction_address": 17412,
            "instruction": "MOV:G.W R4, @H'F772",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F772",
            "operand_index": 1
          },
          {
            "address": 63346,
            "instruction_address": 17433,
            "instruction": "MOV:G.W R4, @H'F772",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F772",
            "operand_index": 1
          },
          {
            "address": 63346,
            "instruction_address": 17607,
            "instruction": "MOV:G.W R4, @H'F772",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F772",
            "operand_index": 1
          },
          {
            "address": 63346,
            "instruction_address": 17628,
            "instruction": "MOV:G.W R4, @H'F772",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F772",
            "operand_index": 1
          },
          {
            "address": 63346,
            "instruction_address": 17802,
            "instruction": "MOV:G.W R4, @H'F772",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F772",
            "operand_index": 1
          },
          {
            "address": 63346,
            "instruction_address": 17823,
            "instruction": "MOV:G.W R4, @H'F772",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F772",
            "operand_index": 1
          }
        ],
        "xref_count": 3,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 29948,
            "target": 63346
          },
          {
            "source": "pointer_table",
            "address": 46560,
            "target": 63346
          },
          {
            "source": "pointer_table",
            "address": 47052,
            "target": 63346
          }
        ]
      },
      {
        "address": 63376,
        "name": "ram_F790",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 48569,
        "last_access": 48569,
        "accesses": [
          {
            "address": 63376,
            "instruction_address": 48569,
            "instruction": "BCLR.B #7, @H'F790",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F790",
            "operand_index": 1
          }
        ],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 13432,
            "target": 63376
          }
        ]
      },
      {
        "address": 63377,
        "name": "ram_F791",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 12,
        "read_count": 11,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 6113,
        "last_access": 47828,
        "accesses": [
          {
            "address": 63377,
            "instruction_address": 6113,
            "instruction": "BTST.B #7, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 6163,
            "instruction": "BTST.B #7, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 6219,
            "instruction": "BTST.B #7, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 6263,
            "instruction": "BTST.B #7, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 6349,
            "instruction": "BTST.B #7, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 6405,
            "instruction": "BTST.B #7, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 6449,
            "instruction": "BTST.B #7, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 6498,
            "instruction": "BTST.B #5, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 6543,
            "instruction": "BTST.B #5, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 9882,
            "instruction": "BTST.B #7, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          },
          {
            "address": 63377,
            "instruction_address": 16436,
            "instruction": "CLR.B @H'F791",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 0
          },
          {
            "address": 63377,
            "instruction_address": 47828,
            "instruction": "BTST.B #7, @H'F791",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F791",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63380,
        "name": "ram_F794",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16311,
        "last_access": 49106,
        "accesses": [
          {
            "address": 63380,
            "instruction_address": 16311,
            "instruction": "CLR.B @H'F794",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F794",
            "operand_index": 0
          },
          {
            "address": 63380,
            "instruction_address": 49102,
            "instruction": "ADD:Q.B #1, @H'F794",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F794",
            "operand_index": 1
          },
          {
            "address": 63380,
            "instruction_address": 49106,
            "instruction": "CMP:G.B #H'0A, @H'F794",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F794",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63381,
        "name": "ram_F795",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 1,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16440,
        "last_access": 47822,
        "accesses": [
          {
            "address": 63381,
            "instruction_address": 16440,
            "instruction": "CLR.B @H'F795",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F795",
            "operand_index": 0
          },
          {
            "address": 63381,
            "instruction_address": 47822,
            "instruction": "BTST.B #6, @H'F795",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F795",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63383,
        "name": "ram_F797",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 49059,
        "last_access": 49065,
        "accesses": [
          {
            "address": 63383,
            "instruction_address": 49059,
            "instruction": "TST.B @H'F797",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F797",
            "operand_index": 0
          },
          {
            "address": 63383,
            "instruction_address": 49065,
            "instruction": "ADD:Q.B #-1, @H'F797",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F797",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63384,
        "name": "ram_F798",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16919,
        "last_access": 49081,
        "accesses": [
          {
            "address": 63384,
            "instruction_address": 16919,
            "instruction": "CLR.B @H'F798",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F798",
            "operand_index": 0
          },
          {
            "address": 63384,
            "instruction_address": 49075,
            "instruction": "TST.B @H'F798",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F798",
            "operand_index": 0
          },
          {
            "address": 63384,
            "instruction_address": 49081,
            "instruction": "ADD:Q.B #-1, @H'F798",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F798",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63552,
        "name": "ram_F840",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 8,
        "read_count": 6,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 49015,
        "last_access": 49211,
        "accesses": [
          {
            "address": 63552,
            "instruction_address": 49015,
            "instruction": "TST.B @H'F840",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F840",
            "operand_index": 0
          },
          {
            "address": 63552,
            "instruction_address": 49021,
            "instruction": "ADD:Q.B #-1, @H'F840",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F840",
            "operand_index": 1
          },
          {
            "address": 63552,
            "instruction_address": 49120,
            "instruction": "MOV:G.B #H'0A, @H'F840",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F840",
            "operand_index": 1
          },
          {
            "address": 63552,
            "instruction_address": 49135,
            "instruction": "TST.B @H'F840",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F840",
            "operand_index": 0
          },
          {
            "address": 63552,
            "instruction_address": 49150,
            "instruction": "MOV:G.B #H'0A, @H'F840",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F840",
            "operand_index": 1
          },
          {
            "address": 63552,
            "instruction_address": 49157,
            "instruction": "TST.B @H'F840",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F840",
            "operand_index": 0
          },
          {
            "address": 63552,
            "instruction_address": 49170,
            "instruction": "TST.B @H'F840",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F840",
            "operand_index": 0
          },
          {
            "address": 63552,
            "instruction_address": 49211,
            "instruction": "TST.B @H'F840",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F840",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63553,
        "name": "ram_F841",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 49145,
        "last_access": 49163,
        "accesses": [
          {
            "address": 63553,
            "instruction_address": 49145,
            "instruction": "BSET.B #7, @H'F841",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F841",
            "operand_index": 1
          },
          {
            "address": 63553,
            "instruction_address": 49163,
            "instruction": "BSET.B #6, @H'F841",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F841",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63568,
        "name": "ram_F850",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 6,
        "read_count": 1,
        "write_count": 5,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 47670,
        "last_access": 48717,
        "accesses": [
          {
            "address": 63568,
            "instruction_address": 47670,
            "instruction": "MOV:G.W @H'F850, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F850",
            "operand_index": 0
          },
          {
            "address": 63568,
            "instruction_address": 47900,
            "instruction": "MOV:G.B R1, @H'F850",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F850",
            "operand_index": 1
          },
          {
            "address": 63568,
            "instruction_address": 48304,
            "instruction": "MOV:G.B #H'04, @H'F850",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F850",
            "operand_index": 1
          },
          {
            "address": 63568,
            "instruction_address": 48343,
            "instruction": "MOV:G.B #H'04, @H'F850",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F850",
            "operand_index": 1
          },
          {
            "address": 63568,
            "instruction_address": 48649,
            "instruction": "MOV:G.W R0, @H'F850",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F850",
            "operand_index": 1
          },
          {
            "address": 63568,
            "instruction_address": 48717,
            "instruction": "MOV:G.B #H'07, @H'F850",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F850",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63569,
        "name": "ram_F851",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 0,
        "write_count": 5,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47915,
        "last_access": 48726,
        "accesses": [
          {
            "address": 63569,
            "instruction_address": 47915,
            "instruction": "MOV:G.B R5, @H'F851",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F851",
            "operand_index": 1
          },
          {
            "address": 63569,
            "instruction_address": 48313,
            "instruction": "MOV:G.B R0, @H'F851",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F851",
            "operand_index": 1
          },
          {
            "address": 63569,
            "instruction_address": 48352,
            "instruction": "MOV:G.B R0, @H'F851",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F851",
            "operand_index": 1
          },
          {
            "address": 63569,
            "instruction_address": 48360,
            "instruction": "MOV:G.B R0, @H'F851",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F851",
            "operand_index": 1
          },
          {
            "address": 63569,
            "instruction_address": 48726,
            "instruction": "MOV:G.B R0, @H'F851",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F851",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63570,
        "name": "ram_F852",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 1,
        "write_count": 4,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 47678,
        "last_access": 48734,
        "accesses": [
          {
            "address": 63570,
            "instruction_address": 47678,
            "instruction": "MOV:G.W @H'F852, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F852",
            "operand_index": 0
          },
          {
            "address": 63570,
            "instruction_address": 47904,
            "instruction": "MOV:G.B R5, @H'F852",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F852",
            "operand_index": 1
          },
          {
            "address": 63570,
            "instruction_address": 48321,
            "instruction": "MOV:G.W R0, @H'F852",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F852",
            "operand_index": 1
          },
          {
            "address": 63570,
            "instruction_address": 48657,
            "instruction": "MOV:G.W R0, @H'F852",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F852",
            "operand_index": 1
          },
          {
            "address": 63570,
            "instruction_address": 48734,
            "instruction": "MOV:G.W R0, @H'F852",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F852",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63571,
        "name": "ram_F853",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 0,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47935,
        "last_access": 48374,
        "accesses": [
          {
            "address": 63571,
            "instruction_address": 47935,
            "instruction": "MOV:G.B R4, @H'F853",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F853",
            "operand_index": 1
          },
          {
            "address": 63571,
            "instruction_address": 48374,
            "instruction": "MOV:G.B R0, @H'F853",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F853",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63572,
        "name": "ram_F854",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 6,
        "read_count": 1,
        "write_count": 5,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 47686,
        "last_access": 48742,
        "accesses": [
          {
            "address": 63572,
            "instruction_address": 47686,
            "instruction": "MOV:G.B @H'F854, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F854",
            "operand_index": 0
          },
          {
            "address": 63572,
            "instruction_address": 47929,
            "instruction": "MOV:G.B R4, @H'F854",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F854",
            "operand_index": 1
          },
          {
            "address": 63572,
            "instruction_address": 48329,
            "instruction": "MOV:G.B R0, @H'F854",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F854",
            "operand_index": 1
          },
          {
            "address": 63572,
            "instruction_address": 48368,
            "instruction": "MOV:G.B R0, @H'F854",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F854",
            "operand_index": 1
          },
          {
            "address": 63572,
            "instruction_address": 48665,
            "instruction": "MOV:G.W R0, @H'F854",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F854",
            "operand_index": 1
          },
          {
            "address": 63572,
            "instruction_address": 48742,
            "instruction": "MOV:G.B R0, @H'F854",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F854",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63576,
        "name": "ram_F858",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 47674,
        "last_access": 48645,
        "accesses": [
          {
            "address": 63576,
            "instruction_address": 47674,
            "instruction": "MOV:G.W R0, @H'F858",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F858",
            "operand_index": 1
          },
          {
            "address": 63576,
            "instruction_address": 47696,
            "instruction": "XOR.B @H'F858, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F858",
            "operand_index": 0
          },
          {
            "address": 63576,
            "instruction_address": 47726,
            "instruction": "MOV:G.B @H'F858, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F858",
            "operand_index": 0
          },
          {
            "address": 63576,
            "instruction_address": 48645,
            "instruction": "MOV:G.W @H'F858, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F858",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63577,
        "name": "ram_F859",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47700,
        "last_access": 47700,
        "accesses": [
          {
            "address": 63577,
            "instruction_address": 47700,
            "instruction": "XOR.B @H'F859, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F859",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63578,
        "name": "ram_F85A",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 47682,
        "last_access": 48653,
        "accesses": [
          {
            "address": 63578,
            "instruction_address": 47682,
            "instruction": "MOV:G.W R0, @H'F85A",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F85A",
            "operand_index": 1
          },
          {
            "address": 63578,
            "instruction_address": 47704,
            "instruction": "XOR.B @H'F85A, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F85A",
            "operand_index": 0
          },
          {
            "address": 63578,
            "instruction_address": 48653,
            "instruction": "MOV:G.W @H'F85A, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F85A",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63579,
        "name": "ram_F85B",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47708,
        "last_access": 47708,
        "accesses": [
          {
            "address": 63579,
            "instruction_address": 47708,
            "instruction": "XOR.B @H'F85B, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F85B",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63580,
        "name": "ram_F85C",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 47690,
        "last_access": 48661,
        "accesses": [
          {
            "address": 63580,
            "instruction_address": 47690,
            "instruction": "MOV:G.B R0, @H'F85C",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F85C",
            "operand_index": 1
          },
          {
            "address": 63580,
            "instruction_address": 47712,
            "instruction": "XOR.B @H'F85C, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F85C",
            "operand_index": 0
          },
          {
            "address": 63580,
            "instruction_address": 48661,
            "instruction": "MOV:G.W @H'F85C, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F85C",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63581,
        "name": "ram_F85D",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 0,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47716,
        "last_access": 47716,
        "accesses": [
          {
            "address": 63581,
            "instruction_address": 47716,
            "instruction": "MOV:G.B R0, @H'F85D",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F85D",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63584,
        "name": "ram_F860",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 48055,
        "last_access": 48136,
        "accesses": [
          {
            "address": 63584,
            "instruction_address": 48055,
            "instruction": "MOV:G.W R0, @H'F860",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F860",
            "operand_index": 1
          },
          {
            "address": 63584,
            "instruction_address": 48088,
            "instruction": "XOR.B @H'F860, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F860",
            "operand_index": 0
          },
          {
            "address": 63584,
            "instruction_address": 48136,
            "instruction": "MOV:G.B @H'F860, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F860",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63585,
        "name": "ram_F861",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 7,
        "read_count": 7,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 48092,
        "last_access": 48722,
        "accesses": [
          {
            "address": 63585,
            "instruction_address": 48092,
            "instruction": "XOR.B @H'F861, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F861",
            "operand_index": 0
          },
          {
            "address": 63585,
            "instruction_address": 48119,
            "instruction": "MOV:G.B @H'F861, R5",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F861",
            "operand_index": 0
          },
          {
            "address": 63585,
            "instruction_address": 48153,
            "instruction": "BTST.B #7, @H'F861",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F861",
            "operand_index": 1
          },
          {
            "address": 63585,
            "instruction_address": 48190,
            "instruction": "BTST.B #7, @H'F861",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F861",
            "operand_index": 1
          },
          {
            "address": 63585,
            "instruction_address": 48309,
            "instruction": "MOV:G.B @H'F861, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F861",
            "operand_index": 0
          },
          {
            "address": 63585,
            "instruction_address": 48348,
            "instruction": "MOV:G.B @H'F861, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F861",
            "operand_index": 0
          },
          {
            "address": 63585,
            "instruction_address": 48722,
            "instruction": "MOV:G.B @H'F861, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F861",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63586,
        "name": "ram_F862",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 6,
        "read_count": 5,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 48063,
        "last_access": 48730,
        "accesses": [
          {
            "address": 63586,
            "instruction_address": 48063,
            "instruction": "MOV:G.W R0, @H'F862",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F862",
            "operand_index": 1
          },
          {
            "address": 63586,
            "instruction_address": 48096,
            "instruction": "XOR.B @H'F862, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F862",
            "operand_index": 0
          },
          {
            "address": 63586,
            "instruction_address": 48125,
            "instruction": "MOV:G.B @H'F862, R5",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F862",
            "operand_index": 0
          },
          {
            "address": 63586,
            "instruction_address": 48317,
            "instruction": "MOV:G.W @H'F862, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F862",
            "operand_index": 0
          },
          {
            "address": 63586,
            "instruction_address": 48356,
            "instruction": "MOV:G.B @H'F862, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F862",
            "operand_index": 0
          },
          {
            "address": 63586,
            "instruction_address": 48730,
            "instruction": "MOV:G.W @H'F862, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F862",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63587,
        "name": "ram_F863",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 6,
        "read_count": 6,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 48100,
        "last_access": 48603,
        "accesses": [
          {
            "address": 63587,
            "instruction_address": 48100,
            "instruction": "XOR.B @H'F863, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F863",
            "operand_index": 0
          },
          {
            "address": 63587,
            "instruction_address": 48237,
            "instruction": "MOV:G.B @H'F863, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F863",
            "operand_index": 0
          },
          {
            "address": 63587,
            "instruction_address": 48267,
            "instruction": "MOV:G.B @H'F863, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F863",
            "operand_index": 0
          },
          {
            "address": 63587,
            "instruction_address": 48402,
            "instruction": "MOV:G.B @H'F863, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F863",
            "operand_index": 0
          },
          {
            "address": 63587,
            "instruction_address": 48427,
            "instruction": "MOV:G.B @H'F863, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F863",
            "operand_index": 0
          },
          {
            "address": 63587,
            "instruction_address": 48603,
            "instruction": "MOV:G.B @H'F863, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F863",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63588,
        "name": "ram_F864",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 8,
        "read_count": 6,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte",
          "word"
        ],
        "width": "mixed",
        "first_access": 48071,
        "last_access": 48738,
        "accesses": [
          {
            "address": 63588,
            "instruction_address": 48071,
            "instruction": "MOV:G.W R0, @H'F864",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F864",
            "operand_index": 1
          },
          {
            "address": 63588,
            "instruction_address": 48104,
            "instruction": "XOR.B @H'F864, R0",
            "mnemonic": "XOR.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F864",
            "operand_index": 0
          },
          {
            "address": 63588,
            "instruction_address": 48253,
            "instruction": "MOV:G.B #H'80, @H'F864",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F864",
            "operand_index": 1
          },
          {
            "address": 63588,
            "instruction_address": 48273,
            "instruction": "MOV:G.B @H'F864, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F864",
            "operand_index": 0
          },
          {
            "address": 63588,
            "instruction_address": 48325,
            "instruction": "MOV:G.B @H'F864, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F864",
            "operand_index": 0
          },
          {
            "address": 63588,
            "instruction_address": 48433,
            "instruction": "MOV:G.B @H'F864, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F864",
            "operand_index": 0
          },
          {
            "address": 63588,
            "instruction_address": 48609,
            "instruction": "MOV:G.B @H'F864, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F864",
            "operand_index": 0
          },
          {
            "address": 63588,
            "instruction_address": 48738,
            "instruction": "MOV:G.B @H'F864, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F864",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63589,
        "name": "ram_F865",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 48108,
        "last_access": 48108,
        "accesses": [
          {
            "address": 63589,
            "instruction_address": 48108,
            "instruction": "CMP:G.B @H'F865, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F865",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63592,
        "name": "ram_F868",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 48051,
        "last_access": 48051,
        "accesses": [
          {
            "address": 63592,
            "instruction_address": 48051,
            "instruction": "MOV:G.W @H'F868, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F868",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63594,
        "name": "ram_F86A",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 48059,
        "last_access": 48059,
        "accesses": [
          {
            "address": 63594,
            "instruction_address": 48059,
            "instruction": "MOV:G.W @H'F86A, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F86A",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63596,
        "name": "ram_F86C",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 48067,
        "last_access": 48067,
        "accesses": [
          {
            "address": 63596,
            "instruction_address": 48067,
            "instruction": "MOV:G.W @H'F86C, R0",
            "mnemonic": "MOV:G.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F86C",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63920,
        "name": "ram_F9B0",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 9,
        "read_count": 8,
        "write_count": 5,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15968,
        "last_access": 47864,
        "accesses": [
          {
            "address": 63920,
            "instruction_address": 15968,
            "instruction": "MOV:G.B @H'F9B0, R1",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B0",
            "operand_index": 0
          },
          {
            "address": 63920,
            "instruction_address": 15994,
            "instruction": "ADD:Q.B #1, @H'F9B0",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B0",
            "operand_index": 1
          },
          {
            "address": 63920,
            "instruction_address": 15998,
            "instruction": "BCLR.B #7, @H'F9B0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B0",
            "operand_index": 1
          },
          {
            "address": 63920,
            "instruction_address": 16002,
            "instruction": "MOV:G.B @H'F9B0, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B0",
            "operand_index": 0
          },
          {
            "address": 63920,
            "instruction_address": 16377,
            "instruction": "CLR.B @H'F9B0",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9B0",
            "operand_index": 0
          },
          {
            "address": 63920,
            "instruction_address": 16473,
            "instruction": "MOV:G.B @H'F9B0, R2",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B0",
            "operand_index": 0
          },
          {
            "address": 63920,
            "instruction_address": 16492,
            "instruction": "ADD:Q.B #1, @H'F9B0",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B0",
            "operand_index": 1
          },
          {
            "address": 63920,
            "instruction_address": 16496,
            "instruction": "BCLR.B #7, @H'F9B0",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B0",
            "operand_index": 1
          },
          {
            "address": 63920,
            "instruction_address": 47864,
            "instruction": "CMP:G.B @H'F9B0, R1",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B0",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63924,
        "name": "ram_F9B4",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 7,
        "read_count": 7,
        "write_count": 4,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 10252,
        "last_access": 48793,
        "accesses": [
          {
            "address": 63924,
            "instruction_address": 10252,
            "instruction": "CMP:G.B @H'F9B4, R1",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B4",
            "operand_index": 0
          },
          {
            "address": 63924,
            "instruction_address": 16038,
            "instruction": "MOV:G.B @H'F9B4, R1",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B4",
            "operand_index": 0
          },
          {
            "address": 63924,
            "instruction_address": 16067,
            "instruction": "ADD:Q.B #1, @H'F9B4",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B4",
            "operand_index": 1
          },
          {
            "address": 63924,
            "instruction_address": 16071,
            "instruction": "BCLR.B #5, @H'F9B4",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B4",
            "operand_index": 1
          },
          {
            "address": 63924,
            "instruction_address": 48760,
            "instruction": "MOV:G.B @H'F9B4, R1",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B4",
            "operand_index": 0
          },
          {
            "address": 63924,
            "instruction_address": 48789,
            "instruction": "ADD:Q.B #1, @H'F9B4",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B4",
            "operand_index": 1
          },
          {
            "address": 63924,
            "instruction_address": 48793,
            "instruction": "BCLR.B #5, @H'F9B4",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63925,
        "name": "ram_F9B5",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 11,
        "read_count": 10,
        "write_count": 7,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 15960,
        "last_access": 48631,
        "accesses": [
          {
            "address": 63925,
            "instruction_address": 15960,
            "instruction": "MOV:G.B @H'F9B5, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 0
          },
          {
            "address": 63925,
            "instruction_address": 16011,
            "instruction": "CMP:G.B @H'F9B5, R0",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 0
          },
          {
            "address": 63925,
            "instruction_address": 16373,
            "instruction": "CLR.B @H'F9B5",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 0
          },
          {
            "address": 63925,
            "instruction_address": 16479,
            "instruction": "CMP:G.B @H'F9B5, R2",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 0
          },
          {
            "address": 63925,
            "instruction_address": 47858,
            "instruction": "MOV:G.B @H'F9B5, R1",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 0
          },
          {
            "address": 63925,
            "instruction_address": 48493,
            "instruction": "ADD:Q.B #1, @H'F9B5",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 1
          },
          {
            "address": 63925,
            "instruction_address": 48497,
            "instruction": "BCLR.B #7, @H'F9B5",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 1
          },
          {
            "address": 63925,
            "instruction_address": 48584,
            "instruction": "ADD:Q.B #1, @H'F9B5",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 1
          },
          {
            "address": 63925,
            "instruction_address": 48588,
            "instruction": "BCLR.B #7, @H'F9B5",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 1
          },
          {
            "address": 63925,
            "instruction_address": 48627,
            "instruction": "ADD:Q.B #1, @H'F9B5",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 1
          },
          {
            "address": 63925,
            "instruction_address": 48631,
            "instruction": "BCLR.B #7, @H'F9B5",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9B5",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63929,
        "name": "ram_F9B9",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 1,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 10246,
        "last_access": 48752,
        "accesses": [
          {
            "address": 63929,
            "instruction_address": 10246,
            "instruction": "MOV:G.B @H'F9B9, R1",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B9",
            "operand_index": 0
          },
          {
            "address": 63929,
            "instruction_address": 10274,
            "instruction": "MOV:G.B R1, @H'F9B9",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9B9",
            "operand_index": 1
          },
          {
            "address": 63929,
            "instruction_address": 16030,
            "instruction": "MOV:G.B @H'F9B9, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B9",
            "operand_index": 0
          },
          {
            "address": 63929,
            "instruction_address": 48752,
            "instruction": "MOV:G.B @H'F9B9, R3",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9B9",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63936,
        "name": "ram_F9C0",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 11,
        "read_count": 4,
        "write_count": 8,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16357,
        "last_access": 48884,
        "accesses": [
          {
            "address": 63936,
            "instruction_address": 16357,
            "instruction": "TST.B @H'F9C0",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 0
          },
          {
            "address": 63936,
            "instruction_address": 47654,
            "instruction": "TST.B @H'F9C0",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 0
          },
          {
            "address": 63936,
            "instruction_address": 47660,
            "instruction": "MOV:G.B #H'64, @H'F9C0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 1
          },
          {
            "address": 63936,
            "instruction_address": 47778,
            "instruction": "MOV:G.B #H'1F, @H'F9C0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 1
          },
          {
            "address": 63936,
            "instruction_address": 47834,
            "instruction": "MOV:G.B #H'09, @H'F9C0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 1
          },
          {
            "address": 63936,
            "instruction_address": 47841,
            "instruction": "MOV:G.B #H'09, @H'F9C0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 1
          },
          {
            "address": 63936,
            "instruction_address": 47848,
            "instruction": "MOV:G.B #H'F0, @H'F9C0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 1
          },
          {
            "address": 63936,
            "instruction_address": 48669,
            "instruction": "MOV:G.B #H'1F, @H'F9C0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 1
          },
          {
            "address": 63936,
            "instruction_address": 48702,
            "instruction": "MOV:G.B #H'1F, @H'F9C0",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 1
          },
          {
            "address": 63936,
            "instruction_address": 48878,
            "instruction": "TST.B @H'F9C0",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 0
          },
          {
            "address": 63936,
            "instruction_address": 48884,
            "instruction": "ADD:Q.B #-1, @H'F9C0",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9C0",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63937,
        "name": "ram_F9C1",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 3,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47853,
        "last_access": 48894,
        "accesses": [
          {
            "address": 63937,
            "instruction_address": 47853,
            "instruction": "CLR.B @H'F9C1",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C1",
            "operand_index": 0
          },
          {
            "address": 63937,
            "instruction_address": 47985,
            "instruction": "TST.B @H'F9C1",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C1",
            "operand_index": 0
          },
          {
            "address": 63937,
            "instruction_address": 48035,
            "instruction": "MOV:G.B #H'05, @H'F9C1",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C1",
            "operand_index": 1
          },
          {
            "address": 63937,
            "instruction_address": 48888,
            "instruction": "TST.B @H'F9C1",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C1",
            "operand_index": 0
          },
          {
            "address": 63937,
            "instruction_address": 48894,
            "instruction": "ADD:Q.B #-1, @H'F9C1",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9C1",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63938,
        "name": "ram_F9C2",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47734,
        "last_access": 47811,
        "accesses": [
          {
            "address": 63938,
            "instruction_address": 47734,
            "instruction": "MOV:G.B #H'01, @H'F9C2",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C2",
            "operand_index": 1
          },
          {
            "address": 63938,
            "instruction_address": 47787,
            "instruction": "MOV:G.B @H'F9C2, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C2",
            "operand_index": 0
          },
          {
            "address": 63938,
            "instruction_address": 47807,
            "instruction": "ADD:Q.B #1, @H'F9C2",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9C2",
            "operand_index": 1
          },
          {
            "address": 63938,
            "instruction_address": 47811,
            "instruction": "CMP:G.B #H'06, @H'F9C2",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C2",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63939,
        "name": "ram_F9C3",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 10,
        "read_count": 6,
        "write_count": 4,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16351,
        "last_access": 48849,
        "accesses": [
          {
            "address": 63939,
            "instruction_address": 16351,
            "instruction": "TST.B @H'F9C3",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 0
          },
          {
            "address": 63939,
            "instruction_address": 16466,
            "instruction": "TST.B @H'F9C3",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 0
          },
          {
            "address": 63939,
            "instruction_address": 47760,
            "instruction": "TST.B @H'F9C3",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 0
          },
          {
            "address": 63939,
            "instruction_address": 47991,
            "instruction": "CLR.B @H'F9C3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 0
          },
          {
            "address": 63939,
            "instruction_address": 47997,
            "instruction": "CMP:G.B #H'05, @H'F9C3",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 1
          },
          {
            "address": 63939,
            "instruction_address": 48010,
            "instruction": "MOV:G.B @H'F9C3, R1",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 0
          },
          {
            "address": 63939,
            "instruction_address": 48022,
            "instruction": "MOV:G.B R1, @H'F9C3",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 1
          },
          {
            "address": 63939,
            "instruction_address": 48043,
            "instruction": "CMP:G.B #H'06, @H'F9C3",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 1
          },
          {
            "address": 63939,
            "instruction_address": 48075,
            "instruction": "CLR.B @H'F9C3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 0
          },
          {
            "address": 63939,
            "instruction_address": 48849,
            "instruction": "CLR.B @H'F9C3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C3",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 63940,
        "name": "ram_F9C4",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 3,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16454,
        "last_access": 48941,
        "accesses": [
          {
            "address": 63940,
            "instruction_address": 16454,
            "instruction": "TST.B @H'F9C4",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C4",
            "operand_index": 0
          },
          {
            "address": 63940,
            "instruction_address": 16608,
            "instruction": "MOV:G.B #H'14, @H'F9C4",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C4",
            "operand_index": 1
          },
          {
            "address": 63940,
            "instruction_address": 47665,
            "instruction": "MOV:G.B #H'07, @H'F9C4",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C4",
            "operand_index": 1
          },
          {
            "address": 63940,
            "instruction_address": 48935,
            "instruction": "TST.B @H'F9C4",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C4",
            "operand_index": 0
          },
          {
            "address": 63940,
            "instruction_address": 48941,
            "instruction": "ADD:Q.B #-1, @H'F9C4",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9C4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63941,
        "name": "ram_F9C5",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 3,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16367,
        "last_access": 48951,
        "accesses": [
          {
            "address": 63941,
            "instruction_address": 16367,
            "instruction": "TST.B @H'F9C5",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C5",
            "operand_index": 0
          },
          {
            "address": 63941,
            "instruction_address": 48030,
            "instruction": "MOV:G.B #H'14, @H'F9C5",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C5",
            "operand_index": 1
          },
          {
            "address": 63941,
            "instruction_address": 48868,
            "instruction": "CLR.B @H'F9C5",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C5",
            "operand_index": 0
          },
          {
            "address": 63941,
            "instruction_address": 48945,
            "instruction": "TST.B @H'F9C5",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C5",
            "operand_index": 0
          },
          {
            "address": 63941,
            "instruction_address": 48951,
            "instruction": "ADD:Q.B #-1, @H'F9C5",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9C5",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63942,
        "name": "ram_F9C6",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 5,
        "read_count": 3,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 47942,
        "last_access": 48904,
        "accesses": [
          {
            "address": 63942,
            "instruction_address": 47942,
            "instruction": "MOV:G.W #H'01F4, @H'F9C6",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F9C6",
            "operand_index": 1
          },
          {
            "address": 63942,
            "instruction_address": 48821,
            "instruction": "TST.W @H'F9C6",
            "mnemonic": "TST.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F9C6",
            "operand_index": 0
          },
          {
            "address": 63942,
            "instruction_address": 48837,
            "instruction": "MOV:G.W #H'01F4, @H'F9C6",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'F9C6",
            "operand_index": 1
          },
          {
            "address": 63942,
            "instruction_address": 48898,
            "instruction": "TST.W @H'F9C6",
            "mnemonic": "TST.W",
            "direction": "read",
            "width": "word",
            "operand": "@H'F9C6",
            "operand_index": 0
          },
          {
            "address": 63942,
            "instruction_address": 48904,
            "instruction": "ADD:Q.W #-1, @H'F9C6",
            "mnemonic": "ADD:Q.W",
            "direction": "read_write",
            "width": "word",
            "operand": "@H'F9C6",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63944,
        "name": "ram_F9C8",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47948,
        "last_access": 48833,
        "accesses": [
          {
            "address": 63944,
            "instruction_address": 47948,
            "instruction": "MOV:G.B #H'14, @H'F9C8",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'F9C8",
            "operand_index": 1
          },
          {
            "address": 63944,
            "instruction_address": 48827,
            "instruction": "TST.B @H'F9C8",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'F9C8",
            "operand_index": 0
          },
          {
            "address": 63944,
            "instruction_address": 48833,
            "instruction": "ADD:Q.B #-1, @H'F9C8",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'F9C8",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 63995,
        "name": "ram_F9FB",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 0,
        "read_count": 0,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [],
        "width": null,
        "first_access": null,
        "last_access": null,
        "accesses": [],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 53384,
            "target": 63995
          }
        ]
      },
      {
        "address": 64132,
        "name": "ram_FA84",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 0,
        "read_count": 0,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [],
        "width": null,
        "first_access": null,
        "last_access": null,
        "accesses": [],
        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 25326,
            "target": 64132
          }
        ]
      },
      {
        "address": 64162,
        "name": "ram_FAA2",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 19,
        "read_count": 13,
        "write_count": 13,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16339,
        "last_access": 48815,
        "accesses": [
          {
            "address": 64162,
            "instruction_address": 16339,
            "instruction": "TST.B @H'FAA2",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 0
          },
          {
            "address": 64162,
            "instruction_address": 47748,
            "instruction": "BTST.B #3, @H'FAA2",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 47766,
            "instruction": "BCLR.B #3, @H'FAA2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 47872,
            "instruction": "BSET.B #3, @H'FAA2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 48143,
            "instruction": "TST.B @H'FAA2",
            "mnemonic": "TST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 0
          },
          {
            "address": 64162,
            "instruction_address": 48149,
            "instruction": "BSET.B #7, @H'FAA2",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 48179,
            "instruction": "CLR.B @H'FAA2",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 0
          },
          {
            "address": 64162,
            "instruction_address": 48220,
            "instruction": "BCLR.B #3, @H'FAA2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 48336,
            "instruction": "BCLR.B #7, @H'FAA2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 48381,
            "instruction": "BCLR.B #7, @H'FAA2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 48388,
            "instruction": "BCLR.B #7, @H'FAA2",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 48487,
            "instruction": "BTST.B #3, @H'FAA2",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 48505,
            "instruction": "CLR.B @H'FAA2",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 0
          },
          {
            "address": 64162,
            "instruction_address": 48578,
            "instruction": "BTST.B #3, @H'FAA2",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 48596,
            "instruction": "CLR.B @H'FAA2",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 0
          },
          {
            "address": 64162,
            "instruction_address": 48621,
            "instruction": "BTST.B #3, @H'FAA2",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 1
          },
          {
            "address": 64162,
            "instruction_address": 48639,
            "instruction": "CLR.B @H'FAA2",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 0
          },
          {
            "address": 64162,
            "instruction_address": 48711,
            "instruction": "CLR.B @H'FAA2",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 0
          },
          {
            "address": 64162,
            "instruction_address": 48815,
            "instruction": "CLR.B @H'FAA2",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA2",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 64163,
        "name": "ram_FAA3",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 10,
        "read_count": 2,
        "write_count": 8,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47770,
        "last_access": 48843,
        "accesses": [
          {
            "address": 64163,
            "instruction_address": 47770,
            "instruction": "CLR.B @H'FAA3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 0
          },
          {
            "address": 64163,
            "instruction_address": 47953,
            "instruction": "MOV:G.B #H'80, @H'FAA3",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 1
          },
          {
            "address": 64163,
            "instruction_address": 48227,
            "instruction": "CLR.B @H'FAA3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 0
          },
          {
            "address": 64163,
            "instruction_address": 48501,
            "instruction": "CLR.B @H'FAA3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 0
          },
          {
            "address": 64163,
            "instruction_address": 48592,
            "instruction": "CLR.B @H'FAA3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 0
          },
          {
            "address": 64163,
            "instruction_address": 48635,
            "instruction": "CLR.B @H'FAA3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 0
          },
          {
            "address": 64163,
            "instruction_address": 48707,
            "instruction": "CLR.B @H'FAA3",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 0
          },
          {
            "address": 64163,
            "instruction_address": 48805,
            "instruction": "AND.B @H'FAA3, R0",
            "mnemonic": "AND.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 0
          },
          {
            "address": 64163,
            "instruction_address": 48809,
            "instruction": "MOV:G.B R0, @H'FAA3",
            "mnemonic": "MOV:G.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 1
          },
          {
            "address": 64163,
            "instruction_address": 48843,
            "instruction": "BTST.B #7, @H'FAA3",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA3",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 64164,
        "name": "ram_FAA4",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 4,
        "read_count": 3,
        "write_count": 3,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 47959,
        "last_access": 48681,
        "accesses": [
          {
            "address": 64164,
            "instruction_address": 47959,
            "instruction": "BSET.B #7, @H'FAA4",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA4",
            "operand_index": 1
          },
          {
            "address": 64164,
            "instruction_address": 48004,
            "instruction": "CLR.B @H'FAA4",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA4",
            "operand_index": 0
          },
          {
            "address": 64164,
            "instruction_address": 48079,
            "instruction": "BTST.B #7, @H'FAA4",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA4",
            "operand_index": 1
          },
          {
            "address": 64164,
            "instruction_address": 48681,
            "instruction": "BCLR.B #7, @H'FAA4",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 64165,
        "name": "ram_FAA5",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 7,
        "read_count": 7,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 16345,
        "last_access": 48798,
        "accesses": [
          {
            "address": 64165,
            "instruction_address": 16345,
            "instruction": "BTST.B #7, @H'FAA5",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA5",
            "operand_index": 1
          },
          {
            "address": 64165,
            "instruction_address": 16381,
            "instruction": "BCLR.B #7, @H'FAA5",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA5",
            "operand_index": 1
          },
          {
            "address": 64165,
            "instruction_address": 16391,
            "instruction": "BSET.B #7, @H'FAA5",
            "mnemonic": "BSET.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA5",
            "operand_index": 1
          },
          {
            "address": 64165,
            "instruction_address": 16460,
            "instruction": "BTST.B #7, @H'FAA5",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA5",
            "operand_index": 1
          },
          {
            "address": 64165,
            "instruction_address": 47754,
            "instruction": "BTST.B #7, @H'FAA5",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA5",
            "operand_index": 1
          },
          {
            "address": 64165,
            "instruction_address": 48685,
            "instruction": "BTST.B #7, @H'FAA5",
            "mnemonic": "BTST.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA5",
            "operand_index": 1
          },
          {
            "address": 64165,
            "instruction_address": 48798,
            "instruction": "MOV:G.B @H'FAA5, R0",
            "mnemonic": "MOV:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA5",
            "operand_index": 0
          }
        ]
      },
      {
        "address": 64166,
        "name": "ram_FAA6",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 3,
        "read_count": 2,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 48115,
        "last_access": 48695,
        "accesses": [
          {
            "address": 64166,
            "instruction_address": 48115,
            "instruction": "CLR.B @H'FAA6",
            "mnemonic": "CLR.B",
            "direction": "write",
            "width": "byte",
            "operand": "@H'FAA6",
            "operand_index": 0
          },
          {
            "address": 64166,
            "instruction_address": 48691,
            "instruction": "ADD:Q.B #1, @H'FAA6",
            "mnemonic": "ADD:Q.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FAA6",
            "operand_index": 1
          },
          {
            "address": 64166,
            "instruction_address": 48695,
            "instruction": "CMP:G.B #H'02, @H'FAA6",
            "mnemonic": "CMP:G.B",
            "direction": "read",
            "width": "byte",
            "operand": "@H'FAA6",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 64240,
        "name": "ram_FAF0",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 0,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 17043,
        "last_access": 17097,
        "accesses": [
          {
            "address": 64240,
            "instruction_address": 17043,
            "instruction": "MOV:G.W #H'2043, @H'FAF0",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAF0",
            "operand_index": 1
          },
          {
            "address": 64240,
            "instruction_address": 17097,
            "instruction": "MOV:G.W #H'2020, @H'FAF0",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAF0",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 64242,
        "name": "ram_FAF2",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 0,
        "write_count": 2,
        "unknown_count": 0,
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          "word"
        ],
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        "first_access": 17049,
        "last_access": 17103,
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          {
            "address": 64242,
            "instruction_address": 17049,
            "instruction": "MOV:G.W #H'4F4E, @H'FAF2",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAF2",
            "operand_index": 1
          },
          {
            "address": 64242,
            "instruction_address": 17103,
            "instruction": "MOV:G.W #H'2020, @H'FAF2",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAF2",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 64244,
        "name": "ram_FAF4",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 0,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "word"
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        "width": "word",
        "first_access": 17055,
        "last_access": 17109,
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          {
            "address": 64244,
            "instruction_address": 17055,
            "instruction": "MOV:G.W #H'4E45, @H'FAF4",
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            "width": "word",
            "operand": "@H'FAF4",
            "operand_index": 1
          },
          {
            "address": 64244,
            "instruction_address": 17109,
            "instruction": "MOV:G.W #H'2020, @H'FAF4",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAF4",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 64246,
        "name": "ram_FAF6",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 0,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 17061,
        "last_access": 17115,
        "accesses": [
          {
            "address": 64246,
            "instruction_address": 17061,
            "instruction": "MOV:G.W #H'4354, @H'FAF6",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAF6",
            "operand_index": 1
          },
          {
            "address": 64246,
            "instruction_address": 17115,
            "instruction": "MOV:G.W #H'2020, @H'FAF6",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAF6",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 64248,
        "name": "ram_FAF8",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 0,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 17067,
        "last_access": 17121,
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          {
            "address": 64248,
            "instruction_address": 17067,
            "instruction": "MOV:G.W #H'3A4E, @H'FAF8",
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            "width": "word",
            "operand": "@H'FAF8",
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          },
          {
            "address": 64248,
            "instruction_address": 17121,
            "instruction": "MOV:G.W #H'2020, @H'FAF8",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAF8",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 64250,
        "name": "ram_FAFA",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 0,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 17073,
        "last_access": 17127,
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          {
            "address": 64250,
            "instruction_address": 17073,
            "instruction": "MOV:G.W #H'4F54, @H'FAFA",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAFA",
            "operand_index": 1
          },
          {
            "address": 64250,
            "instruction_address": 17127,
            "instruction": "MOV:G.W #H'2020, @H'FAFA",
            "mnemonic": "MOV:G.W",
            "direction": "write",
            "width": "word",
            "operand": "@H'FAFA",
            "operand_index": 1
          }
        ]
      },
      {
        "address": 64252,
        "name": "ram_FAFC",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 2,
        "read_count": 0,
        "write_count": 2,
        "unknown_count": 0,
        "width_hints": [
          "word"
        ],
        "width": "word",
        "first_access": 17079,
        "last_access": 17133,
        "accesses": [
          {
            "address": 64252,
            "instruction_address": 17079,
            "instruction": "MOV:G.W #H'2041, @H'FAFC",
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            "width": "word",
            "operand": "@H'FAFC",
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          },
          {
            "address": 64252,
            "instruction_address": 17133,
            "instruction": "MOV:G.W #H'2020, @H'FAFC",
            "mnemonic": "MOV:G.W",
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            "width": "word",
            "operand": "@H'FAFC",
            "operand_index": 1
          }
        ],
        "xref_count": 1,
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          {
            "source": "pointer_table",
            "address": 6686,
            "target": 64252
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        ]
      },
      {
        "address": 64254,
        "name": "ram_FAFE",
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        "width_hints": [
          "word"
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        "width": "word",
        "first_access": 17085,
        "last_access": 17139,
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          {
            "address": 64254,
            "instruction_address": 17085,
            "instruction": "MOV:G.W #H'4354, @H'FAFE",
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            "width": "word",
            "operand": "@H'FAFE",
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          {
            "address": 64254,
            "instruction_address": 17139,
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            "width": "word",
            "operand": "@H'FAFE",
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        "address": 64256,
        "name": "ram_FB00",
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          "word"
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            "address": 64256,
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            "operand": "@H'FB00",
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            "address": 64256,
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            "address": 64256,
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            "operand": "@H'FB00",
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            "address": 64256,
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            "operand": "@H'FB00",
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        "address": 64258,
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          "byte"
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        "first_access": 5932,
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            "address": 64258,
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            "address": 64258,
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            "address": 64258,
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            "address": 64258,
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            "operand": "@H'FB02",
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            "address": 64258,
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            "operand": "@H'FB02",
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            "address": 64258,
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            "operand": "@H'FB02",
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            "address": 64258,
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            "operand": "@H'FB02",
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            "address": 64258,
            "instruction_address": 48988,
            "instruction": "ADD:Q.B #-1, @H'FB02",
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            "width": "byte",
            "operand": "@H'FB02",
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          }
        ]
      },
      {
        "address": 64259,
        "name": "ram_FB03",
        "region": "on_chip_ram",
        "kind": "ram",
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        "write_count": 5,
        "unknown_count": 0,
        "width_hints": [
          "byte"
        ],
        "width": "byte",
        "first_access": 5912,
        "last_access": 48994,
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          {
            "address": 64259,
            "instruction_address": 5912,
            "instruction": "BSET.B #7, @H'FB03",
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            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FB03",
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          {
            "address": 64259,
            "instruction_address": 5984,
            "instruction": "BSET.B #7, @H'FB03",
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            "operand": "@H'FB03",
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          {
            "address": 64259,
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            "instruction": "BSET.B #7, @H'FB03",
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            "operand": "@H'FB03",
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          {
            "address": 64259,
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            "instruction": "CLR.B @H'FB03",
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            "operand": "@H'FB03",
            "operand_index": 0
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          {
            "address": 64259,
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            "instruction": "BTST.B #7, @H'FB03",
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            "operand": "@H'FB03",
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            "address": 64259,
            "instruction_address": 17503,
            "instruction": "BTST.B #7, @H'FB03",
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            "operand": "@H'FB03",
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            "address": 64259,
            "instruction_address": 17698,
            "instruction": "BTST.B #7, @H'FB03",
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            "operand": "@H'FB03",
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            "address": 64259,
            "instruction_address": 18682,
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            "operand": "@H'FB03",
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          {
            "address": 64259,
            "instruction_address": 48976,
            "instruction": "BTST.B #7, @H'FB03",
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            "operand": "@H'FB03",
            "operand_index": 1
          },
          {
            "address": 64259,
            "instruction_address": 48994,
            "instruction": "BCLR.B #7, @H'FB03",
            "mnemonic": "BCLR.B",
            "direction": "read_write",
            "width": "byte",
            "operand": "@H'FB03",
            "operand_index": 1
          }
        ],
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        "xrefs": [
          {
            "source": "pointer_table",
            "address": 18602,
            "target": 64259
          }
        ]
      },
      {
        "address": 64610,
        "name": "ram_FC62",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 0,
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        "unknown_count": 0,
        "width_hints": [],
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        "last_access": null,
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        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 25326,
            "target": 64610
          }
        ]
      },
      {
        "address": 64640,
        "name": "ram_FC80",
        "region": "on_chip_ram",
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        "unknown_count": 0,
        "width_hints": [],
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        "first_access": null,
        "last_access": null,
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        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 33010,
            "target": 64640
          }
        ]
      },
      {
        "address": 64644,
        "name": "ram_FC84",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 0,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [],
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        "first_access": null,
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        "xrefs": [
          {
            "source": "pointer_table",
            "address": 33010,
            "target": 64644
          }
        ]
      },
      {
        "address": 64738,
        "name": "ram_FCE2",
        "region": "on_chip_ram",
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        "read_count": 0,
        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [],
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        "first_access": null,
        "last_access": null,
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        "xrefs": [
          {
            "source": "pointer_table",
            "address": 25326,
            "target": 64738
          }
        ]
      },
      {
        "address": 64766,
        "name": "ram_FCFE",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 0,
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        "unknown_count": 0,
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        "xrefs": [
          {
            "source": "pointer_table",
            "address": 53384,
            "target": 64766
          }
        ]
      },
      {
        "address": 65022,
        "name": "ram_FDFE",
        "region": "on_chip_ram",
        "kind": "ram",
        "access_count": 0,
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        "write_count": 0,
        "unknown_count": 0,
        "width_hints": [],
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          {
            "source": "pointer_table",
            "address": 6686,
            "target": 65022
          }
        ]
      },
      {
        "address": 65063,
        "name": "ram_FE27",
        "region": "on_chip_ram",
        "kind": "ram",
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        "read_count": 0,
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        "unknown_count": 0,
        "width_hints": [],
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        "xref_count": 1,
        "xrefs": [
          {
            "source": "pointer_table",
            "address": 13788,
            "target": 65063
          }
        ]
      }
    ],
    "by_address": {
      "4113": "mem_1011",
      "4347": "mem_10FB",
      "4449": "mem_1161",
      "4464": "mem_1170",
      "4473": "mem_1179",
      "4488": "mem_1188",
      "4503": "mem_1197",
      "4512": "mem_11A0",
      "4521": "mem_11A9",
      "4572": "mem_11DC",
      "4614": "mem_1206",
      "4629": "mem_1215",
      "4776": "mem_12A8",
      "4884": "mem_1314",
      "5655": "mem_1617",
      "5671": "mem_1627",
      "5680": "mem_1630",
      "5703": "mem_1647",
      "5732": "mem_1664",
      "5762": "mem_1682",
      "5888": "mem_1700",
      "6169": "mem_1819",
      "6656": "mem_1A00",
      "6904": "mem_1AF8",
      "10261": "mem_2815",
      "11430": "mem_2CA6",
      "17437": "mem_441D",
      "17564": "mem_449C",
      "17566": "mem_449E",
      "17568": "mem_44A0",
      "57344": "mem_E000",
      "57348": "mem_E004",
      "57350": "mem_E006",
      "57414": "mem_E046",
      "57472": "mem_E080",
      "57602": "mem_E102",
      "57636": "mem_E124",
      "57638": "mem_E126",
      "57678": "mem_E14E",
      "57710": "mem_E16E",
      "57714": "mem_E172",
      "57836": "mem_E1EC",
      "57888": "mem_E220",
      "59392": "mem_E800",
      "59398": "mem_E806",
      "59520": "mem_E880",
      "59650": "mem_E902",
      "59684": "mem_E924",
      "59884": "mem_E9EC",
      "61440": "mem_F000",
      "61441": "mem_F001",
      "61442": "mem_F002",
      "61443": "mem_F003",
      "61444": "mem_F004",
      "61445": "mem_F005",
      "61446": "mem_F006",
      "61447": "mem_F007",
      "61448": "mem_F008",
      "61449": "mem_F009",
      "61450": "mem_F00A",
      "61451": "mem_F00B",
      "61452": "mem_F00C",
      "61453": "mem_F00D",
      "61454": "mem_F00E",
      "61455": "mem_F00F",
      "61696": "mem_F100",
      "61697": "mem_F101",
      "61698": "mem_F102",
      "61699": "mem_F103",
      "61700": "mem_F104",
      "61701": "mem_F105",
      "61702": "mem_F106",
      "61703": "mem_F107",
      "61704": "mem_F108",
      "61705": "mem_F109",
      "61706": "mem_F10A",
      "61707": "mem_F10B",
      "61708": "mem_F10C",
      "61709": "mem_F10D",
      "61710": "mem_F10E",
      "61711": "mem_F10F",
      "61952": "mem_F200",
      "61953": "mem_F201",
      "62466": "mem_F402",
      "62468": "mem_F404",
      "62634": "mem_F4AA",
      "62805": "mem_F555",
      "63112": "ram_F688",
      "63113": "ram_F689",
      "63114": "ram_F68A",
      "63115": "ram_F68B",
      "63116": "ram_F68C",
      "63118": "ram_F68E",
      "63120": "ram_F690",
      "63122": "ram_F692",
      "63124": "ram_F694",
      "63126": "ram_F696",
      "63128": "ram_F698",
      "63130": "ram_F69A",
      "63132": "ram_F69C",
      "63134": "ram_F69E",
      "63136": "ram_F6A0",
      "63138": "ram_F6A2",
      "63140": "ram_F6A4",
      "63142": "ram_F6A6",
      "63144": "ram_F6A8",
      "63146": "ram_F6AA",
      "63148": "ram_F6AC",
      "63150": "ram_F6AE",
      "63154": "ram_F6B2",
      "63156": "ram_F6B4",
      "63158": "ram_F6B6",
      "63162": "ram_F6BA",
      "63164": "ram_F6BC",
      "63166": "ram_F6BE",
      "63170": "ram_F6C2",
      "63172": "ram_F6C4",
      "63174": "ram_F6C6",
      "63176": "ram_F6C8",
      "63178": "ram_F6CA",
      "63180": "ram_F6CC",
      "63182": "ram_F6CE",
      "63184": "ram_F6D0",
      "63185": "ram_F6D1",
      "63186": "ram_F6D2",
      "63187": "ram_F6D3",
      "63188": "ram_F6D4",
      "63189": "ram_F6D5",
      "63190": "ram_F6D6",
      "63191": "ram_F6D7",
      "63192": "ram_F6D8",
      "63193": "ram_F6D9",
      "63194": "ram_F6DA",
      "63195": "ram_F6DB",
      "63196": "ram_F6DC",
      "63197": "ram_F6DD",
      "63198": "ram_F6DE",
      "63199": "ram_F6DF",
      "63200": "ram_F6E0",
      "63201": "ram_F6E1",
      "63202": "ram_F6E2",
      "63203": "ram_F6E3",
      "63204": "ram_F6E4",
      "63205": "ram_F6E5",
      "63206": "ram_F6E6",
      "63207": "ram_F6E7",
      "63211": "ram_F6EB",
      "63212": "ram_F6EC",
      "63216": "ram_F6F0",
      "63217": "ram_F6F1",
      "63218": "ram_F6F2",
      "63219": "ram_F6F3",
      "63220": "ram_F6F4",
      "63222": "ram_F6F6",
      "63223": "ram_F6F7",
      "63224": "ram_F6F8",
      "63225": "ram_F6F9",
      "63232": "ram_F700",
      "63233": "ram_F701",
      "63234": "ram_F702",
      "63235": "ram_F703",
      "63236": "ram_F704",
      "63237": "ram_F705",
      "63238": "ram_F706",
      "63239": "ram_F707",
      "63240": "ram_F708",
      "63241": "ram_F709",
      "63242": "ram_F70A",
      "63243": "ram_F70B",
      "63248": "ram_F710",
      "63249": "ram_F711",
      "63250": "ram_F712",
      "63251": "ram_F713",
      "63252": "ram_F714",
      "63253": "ram_F715",
      "63254": "ram_F716",
      "63255": "ram_F717",
      "63256": "ram_F718",
      "63257": "ram_F719",
      "63258": "ram_F71A",
      "63259": "ram_F71B",
      "63260": "ram_F71C",
      "63261": "ram_F71D",
      "63262": "ram_F71E",
      "63263": "ram_F71F",
      "63264": "ram_F720",
      "63265": "ram_F721",
      "63266": "ram_F722",
      "63267": "ram_F723",
      "63268": "ram_F724",
      "63270": "ram_F726",
      "63271": "ram_F727",
      "63280": "ram_F730",
      "63281": "ram_F731",
      "63282": "ram_F732",
      "63283": "ram_F733",
      "63284": "ram_F734",
      "63286": "ram_F736",
      "63288": "ram_F738",
      "63290": "ram_F73A",
      "63292": "ram_F73C",
      "63294": "ram_F73E",
      "63296": "ram_F740",
      "63298": "ram_F742",
      "63308": "ram_F74C",
      "63312": "ram_F750",
      "63314": "ram_F752",
      "63316": "ram_F754",
      "63318": "ram_F756",
      "63319": "ram_F757",
      "63320": "ram_F758",
      "63321": "ram_F759",
      "63323": "ram_F75B",
      "63324": "ram_F75C",
      "63337": "ram_F769",
      "63338": "ram_F76A",
      "63340": "ram_F76C",
      "63341": "ram_F76D",
      "63342": "ram_F76E",
      "63344": "ram_F770",
      "63346": "ram_F772",
      "63376": "ram_F790",
      "63377": "ram_F791",
      "63380": "ram_F794",
      "63381": "ram_F795",
      "63383": "ram_F797",
      "63384": "ram_F798",
      "63552": "ram_F840",
      "63553": "ram_F841",
      "63568": "ram_F850",
      "63569": "ram_F851",
      "63570": "ram_F852",
      "63571": "ram_F853",
      "63572": "ram_F854",
      "63576": "ram_F858",
      "63577": "ram_F859",
      "63578": "ram_F85A",
      "63579": "ram_F85B",
      "63580": "ram_F85C",
      "63581": "ram_F85D",
      "63584": "ram_F860",
      "63585": "ram_F861",
      "63586": "ram_F862",
      "63587": "ram_F863",
      "63588": "ram_F864",
      "63589": "ram_F865",
      "63592": "ram_F868",
      "63594": "ram_F86A",
      "63596": "ram_F86C",
      "63920": "ram_F9B0",
      "63924": "ram_F9B4",
      "63925": "ram_F9B5",
      "63929": "ram_F9B9",
      "63936": "ram_F9C0",
      "63937": "ram_F9C1",
      "63938": "ram_F9C2",
      "63939": "ram_F9C3",
      "63940": "ram_F9C4",
      "63941": "ram_F9C5",
      "63942": "ram_F9C6",
      "63944": "ram_F9C8",
      "63995": "ram_F9FB",
      "64132": "ram_FA84",
      "64162": "ram_FAA2",
      "64163": "ram_FAA3",
      "64164": "ram_FAA4",
      "64165": "ram_FAA5",
      "64166": "ram_FAA6",
      "64240": "ram_FAF0",
      "64242": "ram_FAF2",
      "64244": "ram_FAF4",
      "64246": "ram_FAF6",
      "64248": "ram_FAF8",
      "64250": "ram_FAFA",
      "64252": "ram_FAFC",
      "64254": "ram_FAFE",
      "64256": "ram_FB00",
      "64258": "ram_FB02",
      "64259": "ram_FB03",
      "64610": "ram_FC62",
      "64640": "ram_FC80",
      "64644": "ram_FC84",
      "64738": "ram_FCE2",
      "64766": "ram_FCFE",
      "65022": "ram_FDFE",
      "65063": "ram_FE27"
    }
  },
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        "address": 16816,
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        "text": "  01020304050607080910111213141516X",
        "trimmed": "01020304050607080910111213141516X",
        "kind": "printable_run",
        "score": 1.0,
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        "segments": [
          {
            "width": 10,
            "chunks": [
              "  01020304",
              "0506070809",
              "1011121314",
              "1516X"
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          },
          {
            "width": 16,
            "chunks": [
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              "0809101112131415",
              "16X"
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          }
        ]
      },
      {
        "address": 23381,
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        "text": "0123456789",
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        "kind": "printable_run",
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      {
        "address": 24822,
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        "kind": "printable_run",
        "score": 1.15,
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      },
      {
        "address": 25559,
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        "text": "OPERATION ",
        "trimmed": "OPERATION",
        "kind": "ff_terminated",
        "score": 1.47,
        "confidence": "high",
        "ff_terminators": 3,
        "xrefs": [
          {
            "address": 25572,
            "kind": "raw_mov_iw",
            "target": 25556,
            "delta": -3,
            "register": "R0",
            "instruction": "MOV:I.W #H'63D4, R0",
            "following_bsr": {
              "address": 25575,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
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        "address": 25589,
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        "text": "  PAINT   ",
        "trimmed": "PAINT",
        "kind": "ff_terminated",
        "score": 1.47,
        "confidence": "high",
        "ff_terminators": 3,
        "xrefs": [
          {
            "address": 25602,
            "kind": "raw_mov_iw",
            "target": 25586,
            "delta": -3,
            "register": "R0",
            "instruction": "MOV:I.W #H'63F2, R0",
            "following_bsr": {
              "address": 25605,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
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        "xref_count": 1
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      {
        "address": 25667,
        "length": 10,
        "text": "OPERATION ",
        "trimmed": "OPERATION",
        "kind": "ff_terminated",
        "score": 1.47,
        "confidence": "high",
        "ff_terminators": 3,
        "xrefs": [
          {
            "address": 25680,
            "kind": "raw_mov_iw",
            "target": 25664,
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            "register": "R0",
            "instruction": "MOV:I.W #H'6440, R0",
            "following_bsr": {
              "address": 25683,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
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        "address": 25697,
        "length": 10,
        "text": "IRIS/M.BLK",
        "trimmed": "IRIS/M.BLK",
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        "score": 1.41,
        "confidence": "high",
        "ff_terminators": 3,
        "xrefs": [
          {
            "address": 25710,
            "kind": "raw_mov_iw",
            "target": 25694,
            "delta": -3,
            "register": "R0",
            "instruction": "MOV:I.W #H'645E, R0",
            "following_bsr": {
              "address": 25713,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
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        "xref_count": 1
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        "address": 25744,
        "length": 10,
        "text": "OPERATION ",
        "trimmed": "OPERATION",
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        "score": 1.47,
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        "ff_terminators": 3,
        "xrefs": [
          {
            "address": 25757,
            "kind": "raw_mov_iw",
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            "register": "R0",
            "instruction": "MOV:I.W #H'648D, R0",
            "following_bsr": {
              "address": 25760,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
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      {
        "address": 25774,
        "length": 10,
        "text": "   LOCK   ",
        "trimmed": "LOCK",
        "kind": "ff_terminated",
        "score": 1.47,
        "confidence": "high",
        "ff_terminators": 3,
        "xrefs": [
          {
            "address": 25787,
            "kind": "raw_mov_iw",
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            "register": "R0",
            "instruction": "MOV:I.W #H'64AB, R0",
            "following_bsr": {
              "address": 25790,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 25903,
        "length": 19,
        "text": " DYNA LATITUDE  Xe/",
        "trimmed": "DYNA LATITUDE  Xe/",
        "kind": "printable_run",
        "score": 1.064,
        "confidence": "high",
        "xrefs": [
          {
            "address": 25919,
            "kind": "raw_mov_iw",
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            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'652F, R0",
            "following_bsr": {
              "address": 25922,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
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        "address": 25937,
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        "text": "HIGH       LOW~XeP",
        "trimmed": "HIGH       LOW~XeP",
        "kind": "printable_run",
        "score": 0.981,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 25952,
            "kind": "raw_mov_iw",
            "target": 25936,
            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'6550, R0",
            "following_bsr": {
              "address": 25955,
              "target": 23432,
              "instruction": "BSR H'5B88"
            }
          }
        ],
        "xref_count": 1
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      {
        "address": 26057,
        "length": 18,
        "text": "   BLACK STR    Xe",
        "trimmed": "BLACK STR    Xe",
        "kind": "printable_run",
        "score": 1.04,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 26073,
            "kind": "raw_mov_iw",
            "target": 26057,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'65C9, R0",
            "following_bsr": {
              "address": 26076,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
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      {
        "address": 26180,
        "length": 19,
        "text": "   BLACK STR    XfD",
        "trimmed": "BLACK STR    XfD",
        "kind": "printable_run",
        "score": 1.047,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 26196,
            "kind": "raw_mov_iw",
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            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'6644, R0",
            "following_bsr": {
              "address": 26199,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
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      {
        "address": 26213,
        "length": 19,
        "text": " STRETCH LEVEL  Xfe",
        "trimmed": "STRETCH LEVEL  Xfe",
        "kind": "printable_run",
        "score": 1.044,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 26229,
            "kind": "raw_mov_iw",
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            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'6665, R0",
            "following_bsr": {
              "address": 26232,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        ],
        "xref_count": 1
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      {
        "address": 26243,
        "length": 18,
        "text": "POINT1    POINT2Xf",
        "trimmed": "POINT1    POINT2Xf",
        "kind": "printable_run",
        "score": 1.069,
        "confidence": "high",
        "xrefs": [
          {
            "address": 26259,
            "kind": "raw_mov_iw",
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            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'6683, R0",
            "following_bsr": {
              "address": 26262,
              "target": 24100,
              "instruction": "BSR H'5E24"
            }
          }
        ],
        "xref_count": 1
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      {
        "address": 26374,
        "length": 18,
        "text": "   BLACK STR    Xg",
        "trimmed": "BLACK STR    Xg",
        "kind": "printable_run",
        "score": 1.04,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 26390,
            "kind": "raw_mov_iw",
            "target": 26374,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'6706, R0",
            "following_bsr": {
              "address": 26393,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 26407,
        "length": 19,
        "text": " COMPRESS LEVEL Xg'",
        "trimmed": "COMPRESS LEVEL Xg'",
        "kind": "printable_run",
        "score": 1.036,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 26423,
            "kind": "raw_mov_iw",
            "target": 26407,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'6727, R0",
            "following_bsr": {
              "address": 26426,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
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      {
        "address": 26437,
        "length": 19,
        "text": "POINT1    POINT2XgE",
        "trimmed": "POINT1    POINT2XgE",
        "kind": "printable_run",
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        "confidence": "high",
        "xrefs": [
          {
            "address": 26453,
            "kind": "raw_mov_iw",
            "target": 26437,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'6745, R0",
            "following_bsr": {
              "address": 26456,
              "target": 24100,
              "instruction": "BSR H'5E24"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 26592,
        "length": 18,
        "text": "      TLCS      Xg",
        "trimmed": "TLCS      Xg",
        "kind": "printable_run",
        "score": 0.996,
        "confidence": "medium",
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          {
            "address": 26608,
            "kind": "raw_mov_iw",
            "target": 26592,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'67E0, R0",
            "following_bsr": {
              "address": 26611,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 26655,
        "length": 18,
        "text": " AGC  GAIN  AE  Xh",
        "trimmed": "AGC  GAIN  AE  Xh",
        "kind": "printable_run",
        "score": 1.041,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 26671,
            "kind": "raw_mov_iw",
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            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'681F, R0",
            "following_bsr": {
              "address": 26674,
              "target": 24301,
              "instruction": "BSR H'5EED"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 26939,
        "length": 19,
        "text": "   AUTO FUNC    Xi;",
        "trimmed": "AUTO FUNC    Xi;",
        "kind": "printable_run",
        "score": 0.984,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 26955,
            "kind": "raw_mov_iw",
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            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'693B, R0",
            "following_bsr": {
              "address": 26958,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 27215,
        "length": 19,
        "text": "   AUTO FUNC    XjO",
        "trimmed": "AUTO FUNC    XjO",
        "kind": "printable_run",
        "score": 1.047,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 27231,
            "kind": "raw_mov_iw",
            "target": 27215,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'6A4F, R0",
            "following_bsr": {
              "address": 27234,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 27278,
        "length": 18,
        "text": "  A.IRIS MODE   Xj",
        "trimmed": "A.IRIS MODE   Xj",
        "kind": "printable_run",
        "score": 1.041,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 27294,
            "kind": "raw_mov_iw",
            "target": 27278,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'6A8E, R0",
            "following_bsr": {
              "address": 27297,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 27309,
        "length": 17,
        "text": "AI      BACK.L~Xj",
        "trimmed": "AI      BACK.L~Xj",
        "kind": "printable_run",
        "score": 0.965,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 27324,
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            "instruction": "MOV:I.W #H'6AAC, R0",
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              "address": 27327,
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              "instruction": "BSR H'5C91"
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        "address": 27453,
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        "text": "   AUTO FUNC    Xk=",
        "trimmed": "AUTO FUNC    Xk=",
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        "score": 0.984,
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        "text": "   AUTO FOCUS   Xk^",
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        "address": 27631,
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        "address": 27670,
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        "text": "   DIAG DATA    Xl",
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        "address": 27701,
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        "text": "RESET      REQ~Xl4",
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        "address": 28590,
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            "address": 28606,
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        "address": 28783,
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            "address": 28798,
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        "address": 28831,
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        "address": 28864,
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        "address": 28996,
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        "address": 29129,
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            "address": 29145,
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        "address": 29177,
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            "address": 29193,
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        "address": 29203,
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            "address": 29219,
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              "instruction": "BSR H'5A91"
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        "address": 29349,
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            "address": 29365,
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              "instruction": "BSR H'5A91"
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        "address": 29383,
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        "text": "CAM       BARS~Xr",
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            "address": 29398,
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              "address": 29401,
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              "instruction": "BSR H'5B88"
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          {
            "address": 29428,
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              "instruction": "BSR H'5A91"
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      {
        "address": 29545,
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        "text": "    OTHERS      Xsi",
        "trimmed": "OTHERS      Xsi",
        "kind": "printable_run",
        "score": 0.983,
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          {
            "address": 29561,
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            "instruction": "MOV:I.W #H'7369, R0",
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              "address": 29564,
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              "instruction": "BSR H'5A91"
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        ],
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      {
        "address": 29587,
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        "text": " CENTER MARKER  Xs",
        "trimmed": "CENTER MARKER  Xs",
        "kind": "printable_run",
        "score": 1.076,
        "confidence": "high",
        "xrefs": [
          {
            "address": 29603,
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            "register": "R0",
            "instruction": "MOV:I.W #H'7393, R0",
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              "address": 29606,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
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      {
        "address": 29733,
        "length": 19,
        "text": "    OTHERS      Xt%",
        "trimmed": "OTHERS      Xt%",
        "kind": "printable_run",
        "score": 1.007,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 29749,
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            "register": "R0",
            "instruction": "MOV:I.W #H'7425, R0",
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              "address": 29752,
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              "instruction": "BSR H'5A91"
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        ],
        "xref_count": 1
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      {
        "address": 29796,
        "length": 19,
        "text": "  SAFETY ZONE   Xtd",
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        "kind": "printable_run",
        "score": 1.026,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 29812,
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            "register": "R0",
            "instruction": "MOV:I.W #H'7464, R0",
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              "address": 29815,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
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      {
        "address": 30074,
        "length": 19,
        "text": "   BARS TYPE    Xuz",
        "trimmed": "BARS TYPE    Xuz",
        "kind": "printable_run",
        "score": 1.006,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 30090,
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            "register": "R0",
            "instruction": "MOV:I.W #H'757A, R0",
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              "address": 30093,
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              "instruction": "BSR H'5A91"
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          }
        ],
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      {
        "address": 30116,
        "length": 18,
        "text": "     SMPTE      Xu",
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        "score": 1.008,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 30132,
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            "instruction": "MOV:I.W #H'75A4, R0"
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        ],
        "xref_count": 1
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      {
        "address": 30140,
        "length": 18,
        "text": "     SPLIT      Xu",
        "trimmed": "SPLIT      Xu",
        "kind": "printable_run",
        "score": 1.008,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 30156,
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            "instruction": "MOV:I.W #H'75BC, R0"
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        ],
        "xref_count": 1
      },
      {
        "address": 30176,
        "length": 18,
        "text": " FULLFIELD 75%  Xu",
        "trimmed": "FULLFIELD 75%  Xu",
        "kind": "printable_run",
        "score": 1.059,
        "confidence": "high",
        "xrefs": [
          {
            "address": 30192,
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            "instruction": "MOV:I.W #H'75E0, R0"
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        ],
        "xref_count": 1
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      {
        "address": 30199,
        "length": 18,
        "text": "    EBU 75%     Xu",
        "trimmed": "EBU 75%     Xu",
        "kind": "printable_run",
        "score": 0.996,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 30215,
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            "instruction": "MOV:I.W #H'75F7, R0"
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        ],
        "xref_count": 1
      },
      {
        "address": 30234,
        "length": 18,
        "text": " FULLFIELD100%  Xv",
        "trimmed": "FULLFIELD100%  Xv",
        "kind": "printable_run",
        "score": 1.071,
        "confidence": "high",
        "xrefs": [
          {
            "address": 30250,
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            "instruction": "MOV:I.W #H'761A, R0"
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        ],
        "xref_count": 1
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      {
        "address": 30257,
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        "text": "    EBU 100%    Xv1 ",
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        "kind": "printable_run",
        "score": 1.02,
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        "xrefs": [
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            "address": 30273,
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            "instruction": "MOV:I.W #H'7631, R0"
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        ],
        "xref_count": 1
      },
      {
        "address": 30280,
        "length": 20,
        "text": "      SNG       XvH ",
        "trimmed": "SNG       XvH",
        "kind": "printable_run",
        "score": 0.992,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 30296,
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            "instruction": "MOV:I.W #H'7648, R0"
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        ],
        "xref_count": 1
      },
      {
        "address": 30362,
        "length": 18,
        "text": "    OTHERS      Xv",
        "trimmed": "OTHERS      Xv",
        "kind": "printable_run",
        "score": 1.018,
        "confidence": "medium",
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          {
            "address": 30378,
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            "instruction": "MOV:I.W #H'769A, R0",
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              "address": 30381,
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              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
      },
      {
        "address": 30404,
        "length": 18,
        "text": "  SCREEN MODE   Xv",
        "trimmed": "SCREEN MODE   Xv",
        "kind": "printable_run",
        "score": 1.059,
        "confidence": "high",
        "xrefs": [
          {
            "address": 30420,
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            "instruction": "MOV:I.W #H'76C4, R0",
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              "address": 30423,
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              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
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      {
        "address": 30529,
        "length": 19,
        "text": "       4:3      XwA",
        "trimmed": "4:3      XwA",
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        "score": 0.971,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 30545,
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            "instruction": "MOV:I.W #H'7741, R0",
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              "address": 30548,
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              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
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      {
        "address": 30666,
        "length": 18,
        "text": "    OTHERS      Xw",
        "trimmed": "OTHERS      Xw",
        "kind": "printable_run",
        "score": 1.018,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 30682,
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            "register": "R0",
            "instruction": "MOV:I.W #H'77CA, R0",
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              "address": 30685,
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              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
      },
      {
        "address": 30708,
        "length": 18,
        "text": "COMM LINK ITEM-1Xw",
        "trimmed": "COMM LINK ITEM-1Xw",
        "kind": "printable_run",
        "score": 1.075,
        "confidence": "high",
        "xrefs": [
          {
            "address": 30724,
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            "instruction": "MOV:I.W #H'77F4, R0",
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              "address": 30727,
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              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
      },
      {
        "address": 30739,
        "length": 17,
        "text": "GAIN   SHUTTER~Xx",
        "trimmed": "GAIN   SHUTTER~Xx",
        "kind": "printable_run",
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        "confidence": "medium",
        "xrefs": [
          {
            "address": 30754,
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            "instruction": "MOV:I.W #H'7812, R0",
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              "instruction": "BSR H'5A91"
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        "address": 30901,
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        "text": "WHITE    BLACK~Xx",
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        "address": 33578,
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        "address": 33729,
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        "address": 33762,
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            "address": 33778,
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        "address": 33913,
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            "address": 33929,
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              "instruction": "BSR H'5A91"
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        "address": 33946,
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            "address": 33962,
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              "instruction": "BSR H'5A91"
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        "address": 33976,
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            "address": 33992,
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              "instruction": "BSR H'5EED"
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        "address": 34097,
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            "address": 34113,
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              "instruction": "BSR H'5A91"
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          }
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        "xref_count": 1
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      {
        "address": 34130,
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        "text": "  BLACK V SAW   X",
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        "score": 1.083,
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            "address": 34146,
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              "instruction": "BSR H'5A91"
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      {
        "address": 34160,
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        "trimmed": "RED GREEN BLUE X",
        "kind": "printable_run",
        "score": 1.113,
        "confidence": "high",
        "xrefs": [
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            "address": 34176,
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              "instruction": "BSR H'5EED"
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        "address": 34281,
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            "address": 34297,
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              "instruction": "BSR H'5A91"
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        "xref_count": 1
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      {
        "address": 34314,
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        "text": "  BLACK V PARA  X",
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        "confidence": "high",
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            "address": 34330,
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              "instruction": "BSR H'5A91"
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      {
        "address": 34344,
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        "trimmed": "RED GREEN BLUE X",
        "kind": "printable_run",
        "score": 1.113,
        "confidence": "high",
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            "address": 34360,
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            "instruction": "MOV:I.W #H'8628, R0",
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              "address": 34363,
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              "instruction": "BSR H'5EED"
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          }
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      {
        "address": 34465,
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          {
            "address": 34481,
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              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
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      {
        "address": 34498,
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        "text": "  BLACK H SAW   X",
        "trimmed": "BLACK H SAW   X",
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        "score": 1.083,
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          {
            "address": 34514,
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              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
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      {
        "address": 34528,
        "length": 17,
        "text": " RED GREEN BLUE X",
        "trimmed": "RED GREEN BLUE X",
        "kind": "printable_run",
        "score": 1.113,
        "confidence": "high",
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          {
            "address": 34544,
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              "instruction": "BSR H'5EED"
            }
          }
        ],
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      {
        "address": 34649,
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        "text": "    SHADING     X",
        "trimmed": "SHADING     X",
        "kind": "printable_run",
        "score": 1.073,
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          {
            "address": 34665,
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            "instruction": "MOV:I.W #H'8759, R0",
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              "address": 34668,
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              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 34682,
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        "text": "  BLACK H PARA  X",
        "trimmed": "BLACK H PARA  X",
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        "score": 1.097,
        "confidence": "high",
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          {
            "address": 34698,
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              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
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      {
        "address": 34712,
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        "trimmed": "RED GREEN BLUE X",
        "kind": "printable_run",
        "score": 1.113,
        "confidence": "high",
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          {
            "address": 34728,
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            "instruction": "MOV:I.W #H'8798, R0",
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              "address": 34731,
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              "instruction": "BSR H'5EED"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 34877,
        "length": 17,
        "text": "     MATRIX     X",
        "trimmed": "MATRIX     X",
        "kind": "printable_run",
        "score": 1.067,
        "confidence": "high",
        "xrefs": [
          {
            "address": 34893,
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            "instruction": "MOV:I.W #H'883D, R0",
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              "address": 34896,
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              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 34911,
        "length": 16,
        "text": "STD         FL~X",
        "trimmed": "STD         FL~X",
        "kind": "printable_run",
        "score": 0.975,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 34926,
            "kind": "raw_mov_iw",
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            "instruction": "MOV:I.W #H'885E, R0",
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              "address": 34929,
              "target": 23432,
              "instruction": "BSR H'5B88"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 34940,
        "length": 17,
        "text": " PRESET MATRIX  X",
        "trimmed": "PRESET MATRIX  X",
        "kind": "printable_run",
        "score": 1.113,
        "confidence": "high",
        "xrefs": [
          {
            "address": 34956,
            "kind": "raw_mov_iw",
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            "register": "R0",
            "instruction": "MOV:I.W #H'887C, R0",
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              "address": 34959,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "address": 34971,
        "length": 16,
        "text": "H.SAT     SPCL~X",
        "trimmed": "H.SAT     SPCL~X",
        "kind": "printable_run",
        "score": 1.006,
        "confidence": "medium",
        "xrefs": [
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            "instruction": "MOV:I.W #H'889A, R0",
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              "address": 34989,
              "target": 23697,
              "instruction": "BSR H'5C91"
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        "address": 35081,
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        "text": "     MATRIX     X",
        "trimmed": "MATRIX     X",
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        "score": 1.067,
        "confidence": "high",
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          {
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              "instruction": "BSR H'5A91"
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        "address": 35115,
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        "text": "ON         OFF~X",
        "trimmed": "ON         OFF~X",
        "kind": "printable_run",
        "score": 0.975,
        "confidence": "medium",
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              "address": 35133,
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              "instruction": "BSR H'5B88"
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        "address": 35144,
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        "text": " SAT        HUE X",
        "trimmed": "SAT        HUE X",
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        "score": 1.038,
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              "address": 35163,
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              "instruction": "BSR H'5E24"
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        "score": 1.067,
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              "instruction": "BSR H'5A91"
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        "address": 35374,
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        "score": 1.025,
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            "address": 35389,
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              "address": 35392,
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              "instruction": "BSR H'5A91"
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        "address": 35403,
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              "address": 35422,
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              "instruction": "BSR H'5E24"
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        "address": 35535,
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        "score": 1.067,
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            "address": 35551,
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            "instruction": "MOV:I.W #H'8ACF, R0",
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              "address": 35554,
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              "instruction": "BSR H'5A91"
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        "address": 35577,
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        "text": " R-G  R-B   G-R X",
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        "score": 1.019,
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            "instruction": "MOV:I.W #H'8AF9, R0",
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              "address": 35596,
              "target": 24301,
              "instruction": "BSR H'5EED"
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        "address": 35697,
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        "score": 1.067,
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            "instruction": "MOV:I.W #H'8B71, R0",
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              "address": 35716,
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              "instruction": "BSR H'5A91"
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        "address": 35739,
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        "text": " G-B  B-R   B-G X",
        "trimmed": "G-B  B-R   B-G X",
        "kind": "printable_run",
        "score": 1.019,
        "confidence": "medium",
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            "address": 35755,
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            "instruction": "MOV:I.W #H'8B9B, R0",
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              "address": 35758,
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              "instruction": "BSR H'5EED"
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        "trimmed": "FILTER     X",
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          {
            "address": 36039,
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            "instruction": "MOV:I.W #H'8CB7, R0",
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              "address": 36042,
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              "instruction": "BSR H'5A91"
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        "address": 36076,
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        "text": "   1  2  3  4   X",
        "trimmed": "1  2  3  4   X",
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        "xrefs": [
          {
            "address": 36092,
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            "instruction": "MOV:I.W #H'8CEC, R0",
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              "address": 36095,
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              "instruction": "BSR H'5A91"
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        "address": 36231,
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        "text": "   A  B  C  D   X",
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        "xrefs": [
          {
            "address": 36247,
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            "instruction": "MOV:I.W #H'8D87, R0",
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              "address": 36250,
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              "instruction": "BSR H'5A91"
            }
          }
        ],
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      {
        "address": 36439,
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        "text": "      LENS      X",
        "trimmed": "LENS      X",
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        "score": 1.041,
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          {
            "address": 36455,
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            "instruction": "MOV:I.W #H'8E57, R0",
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              "address": 36458,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "xref_count": 1
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        "address": 36473,
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        "text": "ON  CONT1  OFF~X",
        "trimmed": "ON  CONT1  OFF~X",
        "kind": "printable_run",
        "score": 1.037,
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        "xrefs": [
          {
            "address": 36488,
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            "register": "R0",
            "instruction": "MOV:I.W #H'8E78, R0",
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              "address": 36491,
              "target": 23432,
              "instruction": "BSR H'5B88"
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          }
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        "address": 36502,
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        "text": "FOCUS      ZOOM X",
        "trimmed": "FOCUS      ZOOM X",
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        "score": 1.068,
        "confidence": "high",
        "xrefs": [
          {
            "address": 36518,
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            "register": "R0",
            "instruction": "MOV:I.W #H'8E96, R0",
            "following_bsr": {
              "address": 36521,
              "target": 24100,
              "instruction": "BSR H'5E24"
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          }
        ],
        "xref_count": 1
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        "address": 36659,
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        "text": "    PAN/TILT    X",
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        "score": 1.065,
        "confidence": "high",
        "xrefs": [
          {
            "address": 36675,
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            "register": "R0",
            "instruction": "MOV:I.W #H'8F33, R0",
            "following_bsr": {
              "address": 36678,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "xref_count": 1
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      {
        "address": 36693,
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        "text": "ON  CONT2  OFF~X",
        "trimmed": "ON  CONT2  OFF~X",
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        "score": 1.037,
        "confidence": "medium",
        "xrefs": [
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            "address": 36708,
            "kind": "raw_mov_iw",
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            "register": "R0",
            "instruction": "MOV:I.W #H'8F54, R0",
            "following_bsr": {
              "address": 36711,
              "target": 23432,
              "instruction": "BSR H'5B88"
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          }
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        "xref_count": 1
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      {
        "address": 36722,
        "length": 17,
        "text": " PAN       TILT X",
        "trimmed": "PAN       TILT X",
        "kind": "printable_run",
        "score": 1.05,
        "confidence": "high",
        "xrefs": [
          {
            "address": 36738,
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            "register": "R0",
            "instruction": "MOV:I.W #H'8F72, R0",
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              "address": 36741,
              "target": 24100,
              "instruction": "BSR H'5E24"
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        ],
        "xref_count": 1
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      {
        "address": 36912,
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        "text": "   SKIN GATE    X",
        "trimmed": "SKIN GATE    X",
        "kind": "printable_run",
        "score": 1.079,
        "confidence": "high",
        "xrefs": [
          {
            "address": 36928,
            "kind": "raw_mov_iw",
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            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'9030, R0",
            "following_bsr": {
              "address": 36931,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
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      {
        "address": 36946,
        "length": 16,
        "text": "ON   IND   OFF~X",
        "trimmed": "ON   IND   OFF~X",
        "kind": "printable_run",
        "score": 1.012,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 36961,
            "kind": "raw_mov_iw",
            "target": 36945,
            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'9051, R0",
            "following_bsr": {
              "address": 36964,
              "target": 23432,
              "instruction": "BSR H'5B88"
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          },
          {
            "address": 47692,
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            "delta": -2,
            "register": "R4",
            "instruction": "MOV:I.W #H'9050, R4"
          }
        ],
        "xref_count": 2
      },
      {
        "address": 36975,
        "length": 17,
        "text": "   GATE SIZE    X",
        "trimmed": "GATE SIZE    X",
        "kind": "printable_run",
        "score": 1.079,
        "confidence": "high",
        "xrefs": [
          {
            "address": 36991,
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            "register": "R0",
            "instruction": "MOV:I.W #H'906F, R0",
            "following_bsr": {
              "address": 36994,
              "target": 23962,
              "instruction": "BSR H'5D9A"
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        ],
        "xref_count": 1
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      {
        "address": 37078,
        "length": 17,
        "text": "   SKIN GATE    X",
        "trimmed": "SKIN GATE    X",
        "kind": "printable_run",
        "score": 1.079,
        "confidence": "high",
        "xrefs": [
          {
            "address": 37094,
            "kind": "raw_mov_iw",
            "target": 37078,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'90D6, R0",
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              "address": 37097,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
      },
      {
        "address": 37111,
        "length": 17,
        "text": "      SIZE      X",
        "trimmed": "SIZE      X",
        "kind": "printable_run",
        "score": 1.041,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 37127,
            "kind": "raw_mov_iw",
            "target": 37111,
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            "register": "R0",
            "instruction": "MOV:I.W #H'90F7, R0",
            "following_bsr": {
              "address": 37130,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
      },
      {
        "address": 37141,
        "length": 17,
        "text": " R-Y        B-Y X",
        "trimmed": "R-Y        B-Y X",
        "kind": "printable_run",
        "score": 1.0,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 37157,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9115, R0",
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              "address": 37160,
              "target": 24100,
              "instruction": "BSR H'5E24"
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          }
        ],
        "xref_count": 1
      },
      {
        "address": 37272,
        "length": 17,
        "text": "   SKIN GATE    X",
        "trimmed": "SKIN GATE    X",
        "kind": "printable_run",
        "score": 1.079,
        "confidence": "high",
        "xrefs": [
          {
            "address": 37288,
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            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'9198, R0",
            "following_bsr": {
              "address": 37291,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 37305,
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        "text": "      POSI      X",
        "trimmed": "POSI      X",
        "kind": "printable_run",
        "score": 1.041,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 37321,
            "kind": "raw_mov_iw",
            "target": 37305,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'91B9, R0",
            "following_bsr": {
              "address": 37324,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 37335,
        "length": 17,
        "text": " R-Y        B-Y X",
        "trimmed": "R-Y        B-Y X",
        "kind": "printable_run",
        "score": 1.0,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 37351,
            "kind": "raw_mov_iw",
            "target": 37335,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'91D7, R0",
            "following_bsr": {
              "address": 37354,
              "target": 24100,
              "instruction": "BSR H'5E24"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 37477,
        "length": 17,
        "text": "  SKIN DETAIL   X",
        "trimmed": "SKIN DETAIL   X",
        "kind": "printable_run",
        "score": 1.097,
        "confidence": "high",
        "xrefs": [
          {
            "address": 37493,
            "kind": "raw_mov_iw",
            "target": 37477,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'9265, R0",
            "following_bsr": {
              "address": 37496,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 37548,
        "length": 17,
        "text": "      OFF       X",
        "trimmed": "OFF       X",
        "kind": "printable_run",
        "score": 1.023,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 37564,
            "kind": "raw_mov_iw",
            "target": 37548,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'92AC, R0",
            "following_bsr": {
              "address": 37567,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 37916,
        "length": 14,
        "text": "     ITEM     ",
        "trimmed": "ITEM",
        "kind": "printable_run",
        "score": 1.0,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 37931,
            "kind": "raw_mov_iw",
            "target": 37915,
            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'941B, R0",
            "following_bsr": {
              "address": 37934,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 37945,
        "length": 14,
        "text": "NOT AVAILABLE ",
        "trimmed": "NOT AVAILABLE",
        "kind": "printable_run",
        "score": 0.985,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 37960,
            "kind": "raw_mov_iw",
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            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'9438, R0",
            "following_bsr": {
              "address": 37963,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 38028,
        "length": 14,
        "text": "     TLCS     ",
        "trimmed": "TLCS",
        "kind": "printable_run",
        "score": 1.0,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 38043,
            "kind": "raw_mov_iw",
            "target": 38027,
            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'948B, R0",
            "following_bsr": {
              "address": 38046,
              "target": 23185,
              "instruction": "BSR H'5A91"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 38057,
        "length": 14,
        "text": "      ON      ",
        "trimmed": "ON",
        "kind": "printable_run",
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            "instruction": "MOV:I.W #H'94A8, R0",
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              "address": 38075,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "address": 38140,
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        "text": "    FILTER    ",
        "trimmed": "FILTER",
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            "address": 38155,
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        "address": 38396,
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        "text": "     KNEE     ",
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            "address": 38411,
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              "instruction": "BSR H'5A91"
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            "address": 38452,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9624, R0"
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            "address": 38475,
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              "instruction": "BSR H'5A91"
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        "address": 38566,
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        "text": "    FLARE     ",
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            "address": 38581,
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        "address": 38595,
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            "address": 38610,
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              "instruction": "BSR H'5A91"
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        "address": 38678,
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        "text": "     ATW      ",
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            "address": 38693,
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            "register": "R0",
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              "instruction": "BSR H'5A91"
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            "address": 38722,
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              "instruction": "BSR H'5A91"
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            "instruction": "MOV:I.W #H'9785, R0",
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              "address": 38808,
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              "instruction": "BSR H'5A91"
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            "address": 38834,
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              "instruction": "BSR H'5A91"
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            "address": 38917,
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            "register": "R0",
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              "instruction": "BSR H'5A91"
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            "address": 38946,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9812, R0",
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              "address": 38949,
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              "instruction": "BSR H'5A91"
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        "address": 39011,
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            "address": 39027,
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            "register": "R0",
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              "instruction": "BSR H'5A91"
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        "address": 39061,
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        "text": "START:PUSH AGAINX",
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        "confidence": "high",
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            "address": 39077,
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            "instruction": "MOV:I.W #H'9895, R0",
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              "instruction": "BSR H'5A91"
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        "address": 39120,
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        "text": "WHT/BLK BALANCE X",
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        "xrefs": [
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            "address": 39136,
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            "register": "R0",
            "instruction": "MOV:I.W #H'98D0, R0",
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              "address": 39139,
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              "instruction": "BSR H'5A91"
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        "address": 39150,
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            "address": 39166,
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            "register": "R0",
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              "instruction": "BSR H'5A91"
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        "address": 39307,
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        "confidence": "high",
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            "address": 39323,
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            "register": "R0",
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              "address": 39326,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "address": 39340,
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        "confidence": "high",
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            "address": 39356,
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            "register": "R0",
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              "instruction": "BSR H'5A91"
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        "address": 39370,
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            "address": 39386,
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            "register": "R0",
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              "address": 39389,
              "target": 23962,
              "instruction": "BSR H'5D9A"
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        "address": 39499,
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        "confidence": "high",
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            "address": 39515,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9A4B, R0",
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              "address": 39518,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "address": 39533,
        "length": 16,
        "text": "ON  WINDOW OFF~X",
        "trimmed": "ON  WINDOW OFF~X",
        "kind": "printable_run",
        "score": 1.05,
        "confidence": "high",
        "xrefs": [
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            "address": 39548,
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            "target": 39532,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9A6C, R0",
            "following_bsr": {
              "address": 39551,
              "target": 23432,
              "instruction": "BSR H'5B88"
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        "xref_count": 1
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      {
        "address": 39562,
        "length": 17,
        "text": "H-POSI    V-POSIX",
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        "kind": "printable_run",
        "score": 1.068,
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        "xrefs": [
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            "address": 39578,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9A8A, R0",
            "following_bsr": {
              "address": 39581,
              "target": 24100,
              "instruction": "BSR H'5E24"
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        "address": 39719,
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        "trimmed": "AUTO SKIN    X",
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        "confidence": "high",
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            "address": 39735,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9B27, R0",
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              "address": 39738,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "address": 39753,
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        "text": "ON  WINDOW OFF~X",
        "trimmed": "ON  WINDOW OFF~X",
        "kind": "printable_run",
        "score": 1.05,
        "confidence": "high",
        "xrefs": [
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            "address": 39768,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9B48, R0",
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              "address": 39771,
              "target": 23432,
              "instruction": "BSR H'5B88"
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        "xref_count": 1
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        "address": 39782,
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        "text": "WIDTH     HEIGHTX",
        "trimmed": "WIDTH     HEIGHTX",
        "kind": "printable_run",
        "score": 1.091,
        "confidence": "high",
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          {
            "address": 39798,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9B66, R0",
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              "address": 39801,
              "target": 24100,
              "instruction": "BSR H'5E24"
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        "address": 39909,
        "length": 9,
        "text": "AUTO SKIN",
        "trimmed": "AUTO SKIN",
        "kind": "printable_run",
        "score": 0.978,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 39922,
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            "target": 39906,
            "delta": -3,
            "register": "R0",
            "instruction": "MOV:I.W #H'9BE2, R0",
            "following_bsr": {
              "address": 39925,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "xref_count": 1
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      {
        "address": 40313,
        "length": 13,
        "text": "WHITE SHADING",
        "trimmed": "WHITE SHADING",
        "kind": "printable_run",
        "score": 0.985,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 40328,
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            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'9D78, R0",
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              "address": 40331,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "xref_count": 1
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      {
        "address": 40342,
        "length": 14,
        "text": "    AUTO SET  ",
        "trimmed": "AUTO SET",
        "kind": "printable_run",
        "score": 0.975,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 40357,
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            "target": 40341,
            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'9D95, R0",
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              "address": 40360,
              "target": 23185,
              "instruction": "BSR H'5A91"
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      {
        "address": 40447,
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        "text": "BLACK SHADING",
        "trimmed": "BLACK SHADING",
        "kind": "printable_run",
        "score": 0.985,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 40462,
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            "register": "R0",
            "instruction": "MOV:I.W #H'9DFE, R0",
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              "address": 40465,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "address": 40476,
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        "text": "    AUTO SET  ",
        "trimmed": "AUTO SET",
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        "score": 0.975,
        "confidence": "medium",
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          {
            "address": 40491,
            "kind": "raw_mov_iw",
            "target": 40475,
            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'9E1B, R0",
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              "address": 40494,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "xref_count": 1
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        "address": 40856,
        "length": 14,
        "text": "     COPY     ",
        "trimmed": "COPY",
        "kind": "printable_run",
        "score": 1.0,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 40871,
            "kind": "raw_mov_iw",
            "target": 40855,
            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'9F97, R0",
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              "address": 40874,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "xref_count": 1
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      {
        "address": 40885,
        "length": 14,
        "text": " IN PROGRESS  ",
        "trimmed": "IN PROGRESS",
        "kind": "printable_run",
        "score": 0.982,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 40900,
            "kind": "raw_mov_iw",
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            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'9FB4, R0",
            "following_bsr": {
              "address": 40903,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "xref_count": 1
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        "address": 40968,
        "length": 14,
        "text": "     COPY     ",
        "trimmed": "COPY",
        "kind": "printable_run",
        "score": 1.0,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 40983,
            "kind": "raw_mov_iw",
            "target": 40967,
            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'A007, R0",
            "following_bsr": {
              "address": 40986,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        ],
        "xref_count": 1
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      {
        "address": 40997,
        "length": 14,
        "text": "  COMPLETED   ",
        "trimmed": "COMPLETED",
        "kind": "printable_run",
        "score": 1.0,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 41012,
            "kind": "raw_mov_iw",
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            "delta": -1,
            "register": "R0",
            "instruction": "MOV:I.W #H'A024, R0",
            "following_bsr": {
              "address": 41015,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "xref_count": 1
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      {
        "address": 41372,
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              "address": 41434,
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              "instruction": "BSR H'5A91"
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            "address": 42741,
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              "address": 43500,
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              "instruction": "BSR H'5C91"
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            "address": 43585,
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              "instruction": "BSR H'5A91"
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            "register": "R0",
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              "address": 43621,
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              "instruction": "BSR H'5EED"
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        "address": 43632,
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            "address": 43648,
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              "address": 43651,
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              "instruction": "BSR H'5EED"
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        "address": 43750,
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            "instruction": "MOV:I.W #H'AAE6, R0",
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              "instruction": "BSR H'5A91"
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            "address": 43799,
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            "register": "R0",
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              "address": 43802,
              "target": 24100,
              "instruction": "BSR H'5E24"
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        "address": 43813,
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        "score": 1.079,
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            "address": 43829,
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            "register": "R0",
            "instruction": "MOV:I.W #H'AB25, R0",
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              "address": 43832,
              "target": 24100,
              "instruction": "BSR H'5E24"
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        "address": 43968,
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        "text": "     DETAIL     X",
        "trimmed": "DETAIL     X",
        "kind": "printable_run",
        "score": 1.067,
        "confidence": "high",
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          {
            "address": 43984,
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            "register": "R0",
            "instruction": "MOV:I.W #H'ABC0, R0",
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              "address": 43987,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "address": 44001,
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        "score": 1.088,
        "confidence": "high",
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          {
            "address": 44017,
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            "target": 44001,
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            "register": "R0",
            "instruction": "MOV:I.W #H'ABE1, R0",
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              "address": 44020,
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              "instruction": "BSR H'5A91"
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        "address": 44031,
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        "trimmed": "LEVEL      X",
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        "confidence": "high",
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          {
            "address": 44047,
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            "register": "R0",
            "instruction": "MOV:I.W #H'ABFF, R0",
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              "address": 44050,
              "target": 23962,
              "instruction": "BSR H'5D9A"
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        "address": 44062,
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        "trimmed": "ON         OFF~X",
        "kind": "printable_run",
        "score": 0.975,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 44077,
            "kind": "raw_mov_iw",
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            "register": "R0",
            "instruction": "MOV:I.W #H'AC1D, R0",
            "following_bsr": {
              "address": 44080,
              "target": 23697,
              "instruction": "BSR H'5C91"
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        "address": 44178,
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        "text": "     DETAIL     X",
        "trimmed": "DETAIL     X",
        "kind": "printable_run",
        "score": 1.067,
        "confidence": "high",
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          {
            "address": 44194,
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            "register": "R0",
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              "address": 44197,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
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        "xref_count": 1
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      {
        "address": 44211,
        "length": 17,
        "text": " KNEE APERTURE  X",
        "trimmed": "KNEE APERTURE  X",
        "kind": "printable_run",
        "score": 1.113,
        "confidence": "high",
        "xrefs": [
          {
            "address": 44227,
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            "target": 44211,
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            "register": "R0",
            "instruction": "MOV:I.W #H'ACB3, R0",
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              "target": 23185,
              "instruction": "BSR H'5A91"
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        "address": 44241,
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        "trimmed": "LEVEL      X",
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        "score": 1.05,
        "confidence": "high",
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          {
            "address": 44257,
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            "instruction": "MOV:I.W #H'ACD1, R0",
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              "address": 44260,
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              "instruction": "BSR H'5D9A"
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        "address": 44272,
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        "trimmed": "ON         OFF~X",
        "kind": "printable_run",
        "score": 0.975,
        "confidence": "medium",
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          {
            "address": 44287,
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            "register": "R0",
            "instruction": "MOV:I.W #H'ACEF, R0",
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              "address": 44290,
              "target": 23697,
              "instruction": "BSR H'5C91"
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        "address": 44363,
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        "text": "     DETAIL     X",
        "trimmed": "DETAIL     X",
        "kind": "printable_run",
        "score": 1.067,
        "confidence": "high",
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          {
            "address": 44379,
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            "register": "R0",
            "instruction": "MOV:I.W #H'AD4B, R0",
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              "address": 44382,
              "target": 23185,
              "instruction": "BSR H'5A91"
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      {
        "address": 44396,
        "length": 17,
        "text": "  CROSS COLOR   X",
        "trimmed": "CROSS COLOR   X",
        "kind": "printable_run",
        "score": 1.097,
        "confidence": "high",
        "xrefs": [
          {
            "address": 44412,
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            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'AD6C, R0",
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              "address": 44415,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
      },
      {
        "address": 44426,
        "length": 17,
        "text": "    SUPPRESS    X",
        "trimmed": "SUPPRESS    X",
        "kind": "printable_run",
        "score": 1.088,
        "confidence": "high",
        "xrefs": [
          {
            "address": 44442,
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            "register": "R0",
            "instruction": "MOV:I.W #H'AD8A, R0",
            "following_bsr": {
              "address": 44445,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
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      {
        "address": 44574,
        "length": 17,
        "text": "     DETAIL     X",
        "trimmed": "DETAIL     X",
        "kind": "printable_run",
        "score": 1.067,
        "confidence": "high",
        "xrefs": [
          {
            "address": 44590,
            "kind": "raw_mov_iw",
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            "register": "R0",
            "instruction": "MOV:I.W #H'AE1E, R0",
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              "address": 44593,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        ],
        "xref_count": 1
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      {
        "address": 44608,
        "length": 16,
        "text": "ON   RED   OFF~X",
        "trimmed": "ON   RED   OFF~X",
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        "confidence": "medium",
        "xrefs": [
          {
            "address": 44623,
            "kind": "raw_mov_iw",
            "target": 44607,
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            "register": "R0",
            "instruction": "MOV:I.W #H'AE3F, R0",
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              "address": 44626,
              "target": 23432,
              "instruction": "BSR H'5B88"
            }
          }
        ],
        "xref_count": 1
      },
      {
        "address": 44637,
        "length": 17,
        "text": "  COMB FILTER   X",
        "trimmed": "COMB FILTER   X",
        "kind": "printable_run",
        "score": 1.097,
        "confidence": "high",
        "xrefs": [
          {
            "address": 44653,
            "kind": "raw_mov_iw",
            "target": 44637,
            "delta": 0,
            "register": "R0",
            "instruction": "MOV:I.W #H'AE5D, R0",
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              "address": 44656,
              "target": 23185,
              "instruction": "BSR H'5A91"
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          }
        ],
        "xref_count": 1
      },
      {
        "address": 44668,
        "length": 16,
        "text": "ON   GRN   OFF~X",
        "trimmed": "ON   GRN   OFF~X",
        "kind": "printable_run",
        "score": 1.012,
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        "xrefs": [
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            "instruction": "MOV:I.W #H'AE7B, R0",
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              "address": 44686,
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              "instruction": "BSR H'5C91"
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        "address": 44782,
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        "text": "     GAMMA      X",
        "trimmed": "GAMMA      X",
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        "score": 1.05,
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              "address": 44801,
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              "instruction": "BSR H'5A91"
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        "address": 44816,
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        "text": "ON         OFF~X",
        "trimmed": "ON         OFF~X",
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        "score": 0.975,
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              "address": 44834,
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              "instruction": "BSR H'5B88"
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        "text": " RED  MAST BLUE X",
        "trimmed": "RED  MAST BLUE X",
        "kind": "printable_run",
        "score": 1.1,
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              "address": 44864,
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              "instruction": "BSR H'5EED"
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              "address": 45016,
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              "instruction": "BSR H'5A91"
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              "instruction": "BSR H'5A91"
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        "trimmed": "PRESET         X",
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              "instruction": "BSR H'5A91"
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              "instruction": "BSR H'5A91"
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            "instruction": "MOV:I.W #H'B160, R0",
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              "instruction": "BSR H'5A91"
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              "address": 45533,
              "target": 24100,
              "instruction": "BSR H'5E24"
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            "address": 45653,
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            "instruction": "MOV:I.W #H'B245, R0",
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              "instruction": "BSR H'5A91"
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            "instruction": "MOV:I.W #H'B29B, R0",
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              "instruction": "BSR H'5A91"
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        "address": 45808,
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        "trimmed": "DL       X",
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            "address": 45824,
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            "register": "R0",
            "instruction": "MOV:I.W #H'B2F0, R0",
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              "address": 45827,
              "target": 23185,
              "instruction": "BSR H'5A91"
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        "address": 45927,
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        "trimmed": "KNEE      X",
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            "address": 45943,
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            "instruction": "MOV:I.W #H'B367, R0",
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              "address": 45946,
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              "instruction": "BSR H'5A91"
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        "address": 45960,
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        "text": "   WHITE CLIP   X",
        "trimmed": "WHITE CLIP   X",
        "kind": "printable_run",
        "score": 1.093,
        "confidence": "high",
        "xrefs": [
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            "address": 45976,
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            "instruction": "MOV:I.W #H'B388, R0",
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              "instruction": "BSR H'5A91"
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        "address": 45990,
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        "text": "     LEVEL      X",
        "trimmed": "LEVEL      X",
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        "score": 1.05,
        "confidence": "high",
        "xrefs": [
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            "address": 46006,
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            "target": 45990,
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            "register": "R0",
            "instruction": "MOV:I.W #H'B3A6, R0",
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              "address": 46009,
              "target": 23962,
              "instruction": "BSR H'5D9A"
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        "address": 46021,
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        "trimmed": "ON         OFF~X",
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        "score": 0.975,
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            "address": 46036,
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            "instruction": "MOV:I.W #H'B3C4, R0",
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              "address": 46039,
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              "instruction": "BSR H'5C91"
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        "address": 46144,
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        "text": "     FLARE      X",
        "trimmed": "FLARE      X",
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        "confidence": "high",
        "xrefs": [
          {
            "address": 46160,
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            "instruction": "MOV:I.W #H'B440, R0",
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              "address": 46163,
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              "instruction": "BSR H'5A91"
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        "address": 46178,
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        "trimmed": "ON         OFF~X",
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            "address": 46193,
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            "instruction": "MOV:I.W #H'B461, R0",
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              "address": 46196,
              "target": 23432,
              "instruction": "BSR H'5B88"
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        "address": 46207,
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        "trimmed": "RED GREEN BLUE X",
        "kind": "printable_run",
        "score": 1.113,
        "confidence": "high",
        "xrefs": [
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            "address": 46223,
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            "instruction": "MOV:I.W #H'B47F, R0",
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              "address": 46226,
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              "instruction": "BSR H'5EED"
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        "address": 46391,
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        "trimmed": "RECALL     X",
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        "score": 1.067,
        "confidence": "high",
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          {
            "address": 46407,
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              "instruction": "BSR H'5A91"
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        "address": 46424,
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        "text": "SCENE F. RECALL~X",
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            "address": 46440,
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              "instruction": "BSR H'5A91"
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        "address": 46457,
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        "text": "      SEL       X",
        "trimmed": "SEL       X",
        "kind": "printable_run",
        "score": 1.023,
        "confidence": "medium",
        "xrefs": [
          {
            "address": 46473,
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            "register": "R0",
            "instruction": "MOV:I.W #H'B579, R0",
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              "instruction": "BSR H'5A91"
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        "address": 46632,
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        "trimmed": "RECALL     X",
        "kind": "printable_run",
        "score": 1.067,
        "confidence": "high",
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          {
            "address": 46648,
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              "instruction": "BSR H'5A91"
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        "address": 46665,
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        "text": "SETUP F. RECALL~X",
        "trimmed": "SETUP F. RECALL~X",
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        "score": 1.05,
        "confidence": "high",
        "xrefs": [
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            "address": 46681,
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            "register": "R0",
            "instruction": "MOV:I.W #H'B649, R0",
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              "instruction": "BSR H'5A91"
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      {
        "address": 46698,
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        "text": "      SEL       X",
        "trimmed": "SEL       X",
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        "confidence": "medium",
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          {
            "address": 46714,
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            "instruction": "MOV:I.W #H'B66A, R0",
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              "instruction": "BSR H'5A91"
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        "address": 46875,
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        "text": "     STORE      X",
        "trimmed": "STORE      X",
        "kind": "printable_run",
        "score": 1.05,
        "confidence": "high",
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          {
            "address": 46891,
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            "instruction": "MOV:I.W #H'B71B, R0",
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              "instruction": "BSR H'5A91"
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        "address": 46908,
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        "text": " SCENE F. STORE~X",
        "trimmed": "SCENE F. STORE~X",
        "kind": "printable_run",
        "score": 1.044,
        "confidence": "medium",
        "xrefs": [
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            "address": 46924,
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            "register": "R0",
            "instruction": "MOV:I.W #H'B73C, R0",
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              "instruction": "BSR H'5A91"
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        "xref_count": 1
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        "address": 46941,
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        "text": " CUR  SEL   CHR X",
        "trimmed": "CUR  SEL   CHR X",
        "kind": "printable_run",
        "score": 1.075,
        "confidence": "high",
        "xrefs": [
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            "address": 46957,
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            "instruction": "MOV:I.W #H'B75D, R0",
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        "address": 47139,
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        "text": "     STORE      X",
        "trimmed": "STORE      X",
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        "score": 1.05,
        "confidence": "high",
        "xrefs": [
          {
            "address": 47155,
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            "instruction": "MOV:I.W #H'B823, R0",
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              "instruction": "BSR H'5A91"
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        "address": 47172,
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        "text": " SETUP F. STORE~X",
        "trimmed": "SETUP F. STORE~X",
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        "xrefs": [
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            "instruction": "MOV:I.W #H'B844, R0",
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              "instruction": "BSR H'5A91"
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        "address": 47204,
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        "text": " CUR  SEL   CHR X",
        "trimmed": "CUR  SEL   CHR X",
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        "confidence": "high",
        "xrefs": [
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            "address": 47220,
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              "instruction": "BSR H'5A91"
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        "address": 47506,
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        "address": 52953,
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        "trimmed": "1234",
        "kind": "printable_run",
        "score": 1.0,
        "confidence": "medium"
      },
      {
        "address": 52958,
        "length": 8,
        "text": "8965.,-(",
        "trimmed": "8965.,-(",
        "kind": "printable_run",
        "score": 1.0,
        "confidence": "medium"
      }
    ],
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      {
        "start": 25559,
        "end": 26456,
        "count": 15,
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          "PAINT",
          "OPERATION",
          "IRIS/M.BLK",
          "OPERATION",
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          "HIGH       LOW~XeP"
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        "start": 26592,
        "end": 26673,
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        "samples": [
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          "DIAG      Xk",
          "DIAG DATA    Xl",
          "RESET      REQ~Xl4"
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        "start": 28548,
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          "SHUTTER     Xo"
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        "start": 28754,
        "end": 29815,
        "count": 15,
        "samples": [
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          "OTHERS      Xp",
          "COPY TO SLAVES~Xp",
          "CAM ID SET~XqD",
          "OTHERS      Xq",
          "CAM ID IND   Xq",
          "TITLE IND    Xr"
        ]
      },
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        "count": 14,
        "samples": [
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          "SMPTE      Xu",
          "SPLIT      Xu",
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          "SNG       XvH"
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          "WHITE V SAW   X",
          "RED GREEN BLUE X",
          "SHADING     X"
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          "SAT        HUE X"
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        "samples": [
          "MATRIX     X",
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          "MATRIX     X",
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          "PAN       TILT X"
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        "samples": [
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          "GATE SIZE    X",
          "SKIN GATE    X",
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          "SKIN GATE    X",
          "POSI      X"
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        "count": 5,
        "samples": [
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          "FILTER"
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        "start": 38396,
        "end": 39167,
        "count": 16,
        "samples": [
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          "OFF",
          "ATW",
          "ON"
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          "H-POSI    V-POSIX"
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        "start": 40313,
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        "count": 4,
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          "BLACK SHADING",
          "AUTO SET"
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        "start": 40856,
        "end": 41011,
        "count": 4,
        "samples": [
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          "COPY",
          "COMPLETED"
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        "start": 41372,
        "end": 41561,
        "count": 5,
        "samples": [
          "WHITE",
          "AUTO",
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          "OK:UNDER1700K",
          "OK:OVER10000K"
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      },
      {
        "start": 41949,
        "end": 41995,
        "count": 2,
        "samples": [
          "OPERATION",
          "PRESET"
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      },
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        "start": 42178,
        "end": 42278,
        "count": 3,
        "samples": [
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        "start": 42701,
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        "count": 2,
        "samples": [
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        "start": 43169,
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          "DETAIL     X",
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          "DETAIL     X",
          "KNEE APERTURE  X",
          "LEVEL      X",
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        "count": 7,
        "samples": [
          "DETAIL     X",
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          "GAMMA      X",
          "ON         OFF~X",
          "RED  MAST BLUE X"
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        "start": 44997,
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        "count": 3,
        "samples": [
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      },
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        "start": 45249,
        "end": 46224,
        "count": 16,
        "samples": [
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          "PRESET         X",
          "MANUAL KNEE   X",
          "VARIABLE       X",
          "KNEE      X",
          "POINT      SLOPEX",
          "PRESET     X",
          "AUTO      X"
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      },
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        "start": 46391,
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        "count": 3,
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          "SEL       X"
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        "count": 3,
        "samples": [
          "RECALL     X",
          "SETUP F. RECALL~X",
          "SEL       X"
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        "start": 46875,
        "end": 46958,
        "count": 3,
        "samples": [
          "STORE      X",
          "SCENE F. STORE~X",
          "CUR  SEL   CHR X"
        ]
      },
      {
        "start": 47139,
        "end": 47221,
        "count": 3,
        "samples": [
          "STORE      X",
          "SETUP F. STORE~X",
          "CUR  SEL   CHR X"
        ]
      },
      {
        "start": 52953,
        "end": 52966,
        "count": 2,
        "samples": [
          "1234",
          "8965.,-("
        ]
      }
    ],
    "searches": [
      {
        "term": "CONNECT",
        "literal_hits": [],
        "candidate_hits": [],
        "near_matches": [
          {
            "address": 40997,
            "text": "  COMPLETED   ",
            "trimmed": "COMPLETED",
            "score": 0.5
          },
          {
            "address": 36473,
            "text": "ON  CONT1  OFF~X",
            "trimmed": "ON  CONT1  OFF~X",
            "score": 0.444
          },
          {
            "address": 36693,
            "text": "ON  CONT2  OFF~X",
            "trimmed": "ON  CONT2  OFF~X",
            "score": 0.444
          },
          {
            "address": 38057,
            "text": "      ON      ",
            "trimmed": "ON",
            "score": 0.444
          },
          {
            "address": 38707,
            "text": "      ON      ",
            "trimmed": "ON",
            "score": 0.444
          },
          {
            "address": 40342,
            "text": "    AUTO SET  ",
            "trimmed": "AUTO SET",
            "score": 0.429
          },
          {
            "address": 40476,
            "text": "    AUTO SET  ",
            "trimmed": "AUTO SET",
            "score": 0.429
          },
          {
            "address": 46908,
            "text": " SCENE F. STORE~X",
            "trimmed": "SCENE F. STORE~X",
            "score": 0.421
          },
          {
            "address": 29733,
            "text": "    OTHERS      Xt%",
            "trimmed": "OTHERS      Xt%",
            "score": 0.4
          },
          {
            "address": 29796,
            "text": "  SAFETY ZONE   Xtd",
            "trimmed": "SAFETY ZONE   Xtd",
            "score": 0.4
          },
          {
            "address": 46424,
            "text": "SCENE F. RECALL~X",
            "trimmed": "SCENE F. RECALL~X",
            "score": 0.4
          },
          {
            "address": 26243,
            "text": "POINT1    POINT2Xf",
            "trimmed": "POINT1    POINT2Xf",
            "score": 0.381
          }
        ],
        "status": "not_found"
      }
    ],
    "notes": [
      "LCD text scan is byte-oriented and conservative; strings may be inline script fields.",
      "Raw xrefs include MOV:I.W immediates to the string address and nearby record prefixes."
    ]
  },
  "lcd_driver": {
    "addresses": [
      {
        "address": 61952,
        "name": "lcd_status_control",
        "role": "status/control register inferred from busy polling and command writes"
      },
      {
        "address": 61953,
        "name": "lcd_data",
        "role": "data register inferred from paired data reads/writes"
      }
    ],
    "accesses": [
      {
        "address": 16202,
        "instruction": "MOVFPE.B @H'F200, R0",
        "lcd_address": 61952,
        "lcd_name": "lcd_status_control",
        "direction": "read",
        "role": "lcd_status_read",
        "register": "R0",
        "summary": "LCD status read from E-clock H'F200"
      },
      {
        "address": 16219,
        "instruction": "MOVTPE.B R4, @H'F200",
        "lcd_address": 61952,
        "lcd_name": "lcd_status_control",
        "direction": "write",
        "role": "lcd_command_or_address_write",
        "register": "R4",
        "summary": "LCD command/address write to E-clock H'F200"
      },
      {
        "address": 16226,
        "instruction": "MOVTPE.B R4, @H'F201",
        "lcd_address": 61953,
        "lcd_name": "lcd_data",
        "direction": "write",
        "role": "lcd_data_write",
        "register": "R4",
        "summary": "LCD data write to E-clock H'F201"
      },
      {
        "address": 16237,
        "instruction": "MOVFPE.B @H'F201, R4",
        "lcd_address": 61953,
        "lcd_name": "lcd_data",
        "direction": "read",
        "role": "lcd_data_read",
        "register": "R4",
        "summary": "LCD data read from E-clock H'F201"
      }
    ],
    "polling_loops": [
      {
        "read_address": 16202,
        "test_address": 16207,
        "branch_address": 16209,
        "register": "R0",
        "bit": 7,
        "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear"
      }
    ],
    "routines": [
      {
        "start": 16192,
        "end": 16244,
        "accesses": [
          {
            "address": 16202,
            "instruction": "MOVFPE.B @H'F200, R0",
            "lcd_address": 61952,
            "lcd_name": "lcd_status_control",
            "direction": "read",
            "role": "lcd_status_read",
            "register": "R0",
            "summary": "LCD status read from E-clock H'F200"
          },
          {
            "address": 16219,
            "instruction": "MOVTPE.B R4, @H'F200",
            "lcd_address": 61952,
            "lcd_name": "lcd_status_control",
            "direction": "write",
            "role": "lcd_command_or_address_write",
            "register": "R4",
            "summary": "LCD command/address write to E-clock H'F200"
          },
          {
            "address": 16226,
            "instruction": "MOVTPE.B R4, @H'F201",
            "lcd_address": 61953,
            "lcd_name": "lcd_data",
            "direction": "write",
            "role": "lcd_data_write",
            "register": "R4",
            "summary": "LCD data write to E-clock H'F201"
          },
          {
            "address": 16237,
            "instruction": "MOVFPE.B @H'F201, R4",
            "lcd_address": 61953,
            "lcd_name": "lcd_data",
            "direction": "read",
            "role": "lcd_data_read",
            "register": "R4",
            "summary": "LCD data read from E-clock H'F201"
          }
        ],
        "roles": [
          "lcd_command_or_address_write",
          "lcd_data_read",
          "lcd_data_write",
          "lcd_status_read"
        ],
        "role_hint": "lcd_wait_and_transfer"
      }
    ],
    "instructions": {
      "16202": [
        {
          "address": 16202,
          "instruction": "MOVFPE.B @H'F200, R0",
          "lcd_address": 61952,
          "lcd_name": "lcd_status_control",
          "direction": "read",
          "role": "lcd_status_read",
          "register": "R0",
          "summary": "LCD status read from E-clock H'F200"
        },
        {
          "address": 16202,
          "kind": "lcd_busy_status_read",
          "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear",
          "loop_start": 16202
        }
      ],
      "16219": [
        {
          "address": 16219,
          "instruction": "MOVTPE.B R4, @H'F200",
          "lcd_address": 61952,
          "lcd_name": "lcd_status_control",
          "direction": "write",
          "role": "lcd_command_or_address_write",
          "register": "R4",
          "summary": "LCD command/address write to E-clock H'F200"
        }
      ],
      "16226": [
        {
          "address": 16226,
          "instruction": "MOVTPE.B R4, @H'F201",
          "lcd_address": 61953,
          "lcd_name": "lcd_data",
          "direction": "write",
          "role": "lcd_data_write",
          "register": "R4",
          "summary": "LCD data write to E-clock H'F201"
        }
      ],
      "16237": [
        {
          "address": 16237,
          "instruction": "MOVFPE.B @H'F201, R4",
          "lcd_address": 61953,
          "lcd_name": "lcd_data",
          "direction": "read",
          "role": "lcd_data_read",
          "register": "R4",
          "summary": "LCD data read from E-clock H'F201"
        }
      ],
      "16207": [
        {
          "address": 16207,
          "kind": "lcd_busy_flag_test",
          "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear",
          "loop_start": 16202
        }
      ],
      "16209": [
        {
          "address": 16209,
          "kind": "lcd_busy_wait_branch",
          "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear",
          "loop_start": 16202
        }
      ]
    }
  },
  "instructions": [
    {
      "address": 4096,
      "address_region": "program_or_external",
      "bytes": "5FFE80",
      "text": "MOV:I.W #H'FE80, R7",
      "mnemonic": "MOV:I.W",
      "operands": "#H'FE80, R7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R7 = 0xFE80"
        ],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          }
        }
      }
    },
    {
      "address": 4099,
      "address_region": "program_or_external",
      "bytes": "0C070088",
      "text": "LDC.W #H'0700, SR",
      "mnemonic": "LDC.W",
      "operands": "#H'0700, SR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        ],
        "notes": [
          "SR = 0x0700"
        ],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4103,
      "address_region": "program_or_external",
      "bytes": "15FE8006FF",
      "text": "MOV:G.B #H'FF, @P1DDR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @P1DDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65152,
          "name": "P1DDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P1DDR = H'FF",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4108,
      "address_region": "program_or_external",
      "bytes": "15FE820600",
      "text": "MOV:G.B #H'00, @P1DR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'00, @P1DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65154,
          "name": "P1DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P1DR = H'00",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4113,
      "address_region": "program_or_external",
      "bytes": "15FE8906F9",
      "text": "MOV:G.B #H'F9, @P6DDR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'F9, @P6DDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65161,
          "name": "P6DDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P6DDR = H'F9",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4118,
      "address_region": "program_or_external",
      "bytes": "15FE8B06F1",
      "text": "MOV:G.B #H'F1, @P6DR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'F1, @P6DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65163,
          "name": "P6DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P6DR = H'F1",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4123,
      "address_region": "program_or_external",
      "bytes": "15FE8C0600",
      "text": "MOV:G.B #H'00, @P7DDR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'00, @P7DDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65164,
          "name": "P7DDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P7DDR = H'00",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4128,
      "address_region": "program_or_external",
      "bytes": "15FE8E0600",
      "text": "MOV:G.B #H'00, @P7DR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'00, @P7DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65166,
          "name": "P7DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P7DR = H'00",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4133,
      "address_region": "program_or_external",
      "bytes": "15FEFE0693",
      "text": "MOV:G.B #H'93, @P9DDR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'93, @P9DDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65278,
          "name": "P9DDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P9DDR = H'93",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4138,
      "address_region": "program_or_external",
      "bytes": "15FEFF0600",
      "text": "MOV:G.B #H'00, @P9DR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'00, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P9DR = H'00",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4143,
      "address_region": "program_or_external",
      "bytes": "15FEFC0687",
      "text": "MOV:G.B #H'87, @SYSCR1",
      "mnemonic": "MOV:G.B",
      "operands": "#H'87, @SYSCR1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65276,
          "name": "SYSCR1",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SYSCR1 = H'87 (IRQ1E=0 IRQ0E=0 NMIEG=0 BRLE=0; P12/P13 are I/O, IRQ0 disabled, IRQ1 disabled)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4148,
      "address_region": "program_or_external",
      "bytes": "15FEFD0684",
      "text": "MOV:G.B #H'84, @SYSCR2",
      "mnemonic": "MOV:G.B",
      "operands": "#H'84, @SYSCR2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65277,
          "name": "SYSCR2",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SYSCR2 = H'84 (IRQ5E=0 IRQ4E=0 IRQ3E=0 IRQ2E=0 P6PWME=1 P9PWME=0 P9SCI2E=0; enabled P6 PWM)",
      "valid": true,
      "board_profile": {
        "accesses": [
          {
            "address": 4148,
            "instruction": "MOV:G.B #H'84, @SYSCR2",
            "register": "SYSCR2",
            "register_address": 65277,
            "access": "write",
            "p9sci2e": false,
            "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96",
            "value": 132,
            "value_hex": "H'84"
          }
        ],
        "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96"
      },
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4153,
      "address_region": "program_or_external",
      "bytes": "15FE900602",
      "text": "MOV:G.B #H'02, @FRT1_TCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'02, @FRT1_TCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65168,
          "name": "FRT1_TCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT1_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4158,
      "address_region": "program_or_external",
      "bytes": "15FE910601",
      "text": "MOV:G.B #H'01, @FRT1_TCSR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'01, @FRT1_TCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65169,
          "name": "FRT1_TCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT1_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4163,
      "address_region": "program_or_external",
      "bytes": "1DFE920600",
      "text": "MOV:G.W #H'00, @FRT1_FRC_H",
      "mnemonic": "MOV:G.W",
      "operands": "#H'00, @FRT1_FRC_H",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65170,
          "name": "FRT1_FRC_H",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT1_FRC_H = H'00",
      "valid": true,
      "peripheral_access": [
        {
          "address": 4163,
          "instruction": "MOV:G.W #H'00, @FRT1_FRC_H",
          "register": "FRT1_FRC",
          "high_address": 65170,
          "low_address": 65171,
          "referenced_address": 65170,
          "referenced_address_hex": "H'FE92",
          "byte": "high",
          "size": "W",
          "direction": "write"
        }
      ],
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4168,
      "address_region": "program_or_external",
      "bytes": "1DFE9407009C",
      "text": "MOV:G.W #H'009C, @FRT1_OCRA_H",
      "mnemonic": "MOV:G.W",
      "operands": "#H'009C, @FRT1_OCRA_H",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65172,
          "name": "FRT1_OCRA_H",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT1_OCRA_H = H'9C",
      "valid": true,
      "peripheral_access": [
        {
          "address": 4168,
          "instruction": "MOV:G.W #H'009C, @FRT1_OCRA_H",
          "register": "FRT1_OCRA",
          "high_address": 65172,
          "low_address": 65173,
          "referenced_address": 65172,
          "referenced_address_hex": "H'FE94",
          "byte": "high",
          "size": "W",
          "direction": "write"
        }
      ],
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4174,
      "address_region": "program_or_external",
      "bytes": "15FEA00602",
      "text": "MOV:G.B #H'02, @FRT2_TCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'02, @FRT2_TCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65184,
          "name": "FRT2_TCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT2_TCR = H'02 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=1 CKS0=0)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4179,
      "address_region": "program_or_external",
      "bytes": "15FEA10601",
      "text": "MOV:G.B #H'01, @FRT2_TCSR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'01, @FRT2_TCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65185,
          "name": "FRT2_TCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT2_TCSR = H'01 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=1)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4184,
      "address_region": "program_or_external",
      "bytes": "1DFEA20600",
      "text": "MOV:G.W #H'00, @FRT2_FRC_H",
      "mnemonic": "MOV:G.W",
      "operands": "#H'00, @FRT2_FRC_H",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65186,
          "name": "FRT2_FRC_H",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT2_FRC_H = H'00",
      "valid": true,
      "peripheral_access": [
        {
          "address": 4184,
          "instruction": "MOV:G.W #H'00, @FRT2_FRC_H",
          "register": "FRT2_FRC",
          "high_address": 65186,
          "low_address": 65187,
          "referenced_address": 65186,
          "referenced_address_hex": "H'FEA2",
          "byte": "high",
          "size": "W",
          "direction": "write"
        }
      ],
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4189,
      "address_region": "program_or_external",
      "bytes": "1DFEA4077A12",
      "text": "MOV:G.W #H'7A12, @FRT2_OCRA_H",
      "mnemonic": "MOV:G.W",
      "operands": "#H'7A12, @FRT2_OCRA_H",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65188,
          "name": "FRT2_OCRA_H",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT2_OCRA_H = H'7A12",
      "valid": true,
      "peripheral_access": [
        {
          "address": 4189,
          "instruction": "MOV:G.W #H'7A12, @FRT2_OCRA_H",
          "register": "FRT2_OCRA",
          "high_address": 65188,
          "low_address": 65189,
          "referenced_address": 65188,
          "referenced_address_hex": "H'FEA4",
          "byte": "high",
          "size": "W",
          "direction": "write"
        }
      ],
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4195,
      "address_region": "program_or_external",
      "bytes": "15FEB00600",
      "text": "MOV:G.B #H'00, @FRT3_TCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'00, @FRT3_TCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65200,
          "name": "FRT3_TCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT3_TCR = H'00 (ICIE=0 OCIEB=0 OCIEA=0 OVIE=0 OEB=0 OEA=0 CKS1=0 CKS0=0)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4200,
      "address_region": "program_or_external",
      "bytes": "15FEB10600",
      "text": "MOV:G.B #H'00, @FRT3_TCSR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'00, @FRT3_TCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65201,
          "name": "FRT3_TCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "FRT3_TCSR = H'00 (ICF=0 OCFB=0 OCFA=0 OVF=0 OLVLB=0 OLVLA=0 IEDG=0 CCLRA=0)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4205,
      "address_region": "program_or_external",
      "bytes": "15FED00600",
      "text": "MOV:G.B #H'00, @TMR_TCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'00, @TMR_TCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65232,
          "name": "TMR_TCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "TMR_TCR = H'00 (CMIEB=0 CMIEA=0 OVIE=0 CCLR1=0 CCLR0=0 CKS2=0 CKS1=0 CKS0=0)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4210,
      "address_region": "program_or_external",
      "bytes": "15FED10610",
      "text": "MOV:G.B #H'10, @TMR_TCSR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'10, @TMR_TCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65233,
          "name": "TMR_TCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "TMR_TCSR = H'10 (CMFB=0 CMFA=0 OVF=0 OS3=0 OS2=0 OS1=0 OS0=0)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4215,
      "address_region": "program_or_external",
      "bytes": "15FEC00638",
      "text": "MOV:G.B #H'38, @PWM1_TCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'38, @PWM1_TCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65216,
          "name": "PWM1_TCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "PWM1_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4220,
      "address_region": "program_or_external",
      "bytes": "15FEC106FF",
      "text": "MOV:G.B #H'FF, @PWM1_DTR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @PWM1_DTR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65217,
          "name": "PWM1_DTR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "PWM1_DTR = H'FF",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4225,
      "address_region": "program_or_external",
      "bytes": "15FEC40638",
      "text": "MOV:G.B #H'38, @PWM2_TCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'38, @PWM2_TCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65220,
          "name": "PWM2_TCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "PWM2_TCR = H'38 (OE=0 OS=0 CKS2=0 CKS1=0 CKS0=0)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4230,
      "address_region": "program_or_external",
      "bytes": "15FEC506FF",
      "text": "MOV:G.B #H'FF, @PWM2_DTR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @PWM2_DTR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65221,
          "name": "PWM2_DTR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "PWM2_DTR = H'FF",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4235,
      "address_region": "program_or_external",
      "bytes": "15FEC8063B",
      "text": "MOV:G.B #H'3B, @PWM3_TCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'3B, @PWM3_TCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65224,
          "name": "PWM3_TCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "PWM3_TCR = H'3B (OE=0 OS=0 CKS2=0 CKS1=1 CKS0=1)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4240,
      "address_region": "program_or_external",
      "bytes": "15FEC9067D",
      "text": "MOV:G.B #H'7D, @PWM3_DTR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'7D, @PWM3_DTR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65225,
          "name": "PWM3_DTR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "PWM3_DTR = H'7D",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4245,
      "address_region": "program_or_external",
      "bytes": "15FED80624",
      "text": "MOV:G.B #H'24, @SCI1_SMR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'24, @SCI1_SMR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65240,
          "name": "SCI1_SMR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SCI1_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 4245,
            "instruction": "MOV:G.B #H'24, @SCI1_SMR",
            "channel": "SCI1",
            "register": "SMR",
            "register_address": 65240,
            "operation": "MOV:G",
            "value": 36,
            "value_hex": "H'24"
          }
        ]
      },
      "board_profile": {
        "accesses": [
          {
            "address": 4245,
            "instruction": "MOV:G.B #H'24, @SCI1_SMR",
            "channel": "SCI1",
            "register": "SMR",
            "register_address": 65240,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)",
            "value": 36,
            "value_hex": "H'24"
          }
        ],
        "comment": "SCI1 SMR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)"
      },
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4250,
      "address_region": "program_or_external",
      "bytes": "15FEDA063C",
      "text": "MOV:G.B #H'3C, @SCI1_SCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'3C, @SCI1_SCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65242,
          "name": "SCI1_SCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SCI1_SCR = H'3C (TIE=0 RIE=0 TE=1 RE=1 CKE1=0 CKE0=0; SCI enables TX,RX, internal clock)",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 4250,
            "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "MOV:G",
            "value": 60,
            "value_hex": "H'3C"
          }
        ]
      },
      "sci_protocol": [
        {
          "address": 4250,
          "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
          "action": "disable_tx_interrupt",
          "channel": "SCI1",
          "register": "SCR",
          "register_address": 65242,
          "register_address_hex": "H'FEDA",
          "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 7,
          "bit_name": "TIE",
          "enabled": false,
          "interrupt_source": "TXI",
          "value": 60
        },
        {
          "address": 4250,
          "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
          "action": "disable_rx_eri_interrupts",
          "channel": "SCI1",
          "register": "SCR",
          "register_address": 65242,
          "register_address_hex": "H'FEDA",
          "comment": "disable SCI1 receive and receive-error interrupts (RIE)",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 6,
          "bit_name": "RIE",
          "enabled": false,
          "interrupt_source": "RXI and ERI",
          "value": 60
        },
        {
          "address": 4250,
          "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
          "action": "enable_transmitter",
          "channel": "SCI1",
          "register": "SCR",
          "register_address": 65242,
          "register_address_hex": "H'FEDA",
          "comment": "enable SCI1 transmitter (TE)",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 5,
          "bit_name": "TE",
          "enabled": true,
          "interrupt_source": "TXD output",
          "value": 60
        },
        {
          "address": 4250,
          "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
          "action": "enable_receiver",
          "channel": "SCI1",
          "register": "SCR",
          "register_address": 65242,
          "register_address_hex": "H'FEDA",
          "comment": "enable SCI1 receiver (RE)",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 4,
          "bit_name": "RE",
          "enabled": true,
          "interrupt_source": "RXD input",
          "value": 60
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 4250,
            "instruction": "MOV:G.B #H'3C, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 60,
            "value_hex": "H'3C",
            "scr": {
              "value": 60,
              "value_hex": "H'3C",
              "tie": false,
              "rie": false,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4255,
      "address_region": "program_or_external",
      "bytes": "15FED90607",
      "text": "MOV:G.B #H'07, @SCI1_BRR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'07, @SCI1_BRR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65241,
          "name": "SCI1_BRR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SCI1_BRR = H'07",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 4255,
            "instruction": "MOV:G.B #H'07, @SCI1_BRR",
            "channel": "SCI1",
            "register": "BRR",
            "register_address": 65241,
            "operation": "MOV:G",
            "value": 7,
            "value_hex": "H'07"
          }
        ],
        "inferences": [
          {
            "channel": "SCI1",
            "mode": "async",
            "mode_summary": "async 8-bit even parity 1 stop",
            "smr": 36,
            "smr_hex": "H'24",
            "brr": 7,
            "brr_hex": "H'07",
            "scr": 60,
            "scr_hex": "H'3C",
            "cks_n": 0,
            "cks_divisor": 1,
            "denominator": 512,
            "clock_source": "internal",
            "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
            "baud_bps": null,
            "confidence": "partial",
            "reason": "clock_hz_missing",
            "comment": "SCI1 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz",
            "address": 4255,
            "instruction": "MOV:G.B #H'07, @SCI1_BRR"
          }
        ]
      },
      "board_profile": {
        "accesses": [
          {
            "address": 4255,
            "instruction": "MOV:G.B #H'07, @SCI1_BRR",
            "channel": "SCI1",
            "register": "BRR",
            "register_address": 65241,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)",
            "value": 7,
            "value_hex": "H'07"
          }
        ],
        "comment": "SCI1 BRR serial init for traced RS232/MAX202 path (H8 pin 66 P95/TXD to MAX202 pin 11; MAX202 pin 12 to H8 pin 67 P96/RXD)"
      },
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4260,
      "address_region": "program_or_external",
      "bytes": "15FEF00624",
      "text": "MOV:G.B #H'24, @SCI2_SMR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'24, @SCI2_SMR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65264,
          "name": "SCI2_SMR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SCI2_SMR = H'24 (C/A=0 CHR=0 PE=1 O/E=0 STOP=0 CKS1=0 CKS0=0; SCI async, 8-bit, even parity, 1 stop, clock phi)",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 4260,
            "instruction": "MOV:G.B #H'24, @SCI2_SMR",
            "channel": "SCI2",
            "register": "SMR",
            "register_address": 65264,
            "operation": "MOV:G",
            "value": 36,
            "value_hex": "H'24"
          }
        ]
      },
      "board_profile": {
        "accesses": [
          {
            "address": 4260,
            "instruction": "MOV:G.B #H'24, @SCI2_SMR",
            "channel": "SCI2",
            "register": "SMR",
            "register_address": 65264,
            "access": "write",
            "traced_to_max202": false,
            "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96",
            "value": 36,
            "value_hex": "H'24",
            "p9sci2e": false
          }
        ],
        "comment": "SCI2 SMR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96"
      },
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4265,
      "address_region": "program_or_external",
      "bytes": "15FEF2060C",
      "text": "MOV:G.B #H'0C, @SCI2_SCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'0C, @SCI2_SCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65266,
          "name": "SCI2_SCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SCI2_SCR = H'0C (TIE=0 RIE=0 TE=0 RE=0 CKE1=0 CKE0=0; SCI enables none, internal clock)",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 4265,
            "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
            "channel": "SCI2",
            "register": "SCR",
            "register_address": 65266,
            "operation": "MOV:G",
            "value": 12,
            "value_hex": "H'0C"
          }
        ]
      },
      "sci_protocol": [
        {
          "address": 4265,
          "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
          "action": "disable_tx_interrupt",
          "channel": "SCI2",
          "register": "SCR",
          "register_address": 65266,
          "register_address_hex": "H'FEF2",
          "comment": "disable SCI2 TX interrupt (TIE); gates TXI when hardware sets TDRE",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 7,
          "bit_name": "TIE",
          "enabled": false,
          "interrupt_source": "TXI",
          "value": 12
        },
        {
          "address": 4265,
          "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
          "action": "disable_rx_eri_interrupts",
          "channel": "SCI2",
          "register": "SCR",
          "register_address": 65266,
          "register_address_hex": "H'FEF2",
          "comment": "disable SCI2 receive and receive-error interrupts (RIE)",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 6,
          "bit_name": "RIE",
          "enabled": false,
          "interrupt_source": "RXI and ERI",
          "value": 12
        },
        {
          "address": 4265,
          "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
          "action": "disable_transmitter",
          "channel": "SCI2",
          "register": "SCR",
          "register_address": 65266,
          "register_address_hex": "H'FEF2",
          "comment": "disable SCI2 transmitter (TE)",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 5,
          "bit_name": "TE",
          "enabled": false,
          "interrupt_source": "TXD output",
          "value": 12
        },
        {
          "address": 4265,
          "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
          "action": "disable_receiver",
          "channel": "SCI2",
          "register": "SCR",
          "register_address": 65266,
          "register_address_hex": "H'FEF2",
          "comment": "disable SCI2 receiver (RE)",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 4,
          "bit_name": "RE",
          "enabled": false,
          "interrupt_source": "RXD input",
          "value": 12
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 4265,
            "instruction": "MOV:G.B #H'0C, @SCI2_SCR",
            "channel": "SCI2",
            "register": "SCR",
            "register_address": 65266,
            "access": "write",
            "traced_to_max202": false,
            "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96",
            "value": 12,
            "value_hex": "H'0C",
            "scr": {
              "value": 12,
              "value_hex": "H'0C",
              "tie": false,
              "rie": false,
              "tx_enabled": false,
              "rx_enabled": false
            },
            "p9sci2e": false
          }
        ],
        "comment": "SCI2 SCR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96"
      },
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4270,
      "address_region": "program_or_external",
      "bytes": "15FEF10607",
      "text": "MOV:G.B #H'07, @SCI2_BRR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'07, @SCI2_BRR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65265,
          "name": "SCI2_BRR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SCI2_BRR = H'07",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 4270,
            "instruction": "MOV:G.B #H'07, @SCI2_BRR",
            "channel": "SCI2",
            "register": "BRR",
            "register_address": 65265,
            "operation": "MOV:G",
            "value": 7,
            "value_hex": "H'07"
          }
        ],
        "inferences": [
          {
            "channel": "SCI2",
            "mode": "async",
            "mode_summary": "async 8-bit even parity 1 stop",
            "smr": 36,
            "smr_hex": "H'24",
            "brr": 7,
            "brr_hex": "H'07",
            "scr": 12,
            "scr_hex": "H'0C",
            "cks_n": 0,
            "cks_divisor": 1,
            "denominator": 512,
            "clock_source": "internal",
            "formula": "B = clock_hz / (64 * 2^(2n) * (N + 1))",
            "baud_bps": null,
            "confidence": "partial",
            "reason": "clock_hz_missing",
            "comment": "SCI2 async 8-bit even parity 1 stop BRR N=7 CKS n=0; baud needs --clock-hz",
            "address": 4270,
            "instruction": "MOV:G.B #H'07, @SCI2_BRR"
          }
        ]
      },
      "board_profile": {
        "accesses": [
          {
            "address": 4270,
            "instruction": "MOV:G.B #H'07, @SCI2_BRR",
            "channel": "SCI2",
            "register": "BRR",
            "register_address": 65265,
            "access": "write",
            "traced_to_max202": false,
            "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96",
            "value": 7,
            "value_hex": "H'07",
            "p9sci2e": false
          }
        ],
        "comment": "SCI2 BRR write; not the traced MAX202 path; P9SCI2E=0 disables SCI2 pins P92/P93/P94, while the board trace is SCI1 P95/P96"
      },
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4275,
      "address_region": "program_or_external",
      "bytes": "15FEE80619",
      "text": "MOV:G.B #H'19, @ADCSR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'19, @ADCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65256,
          "name": "ADCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "ADCSR = H'19 (ADF=0 ADIE=0 ADST=0 SCAN=1 CKS=1 CH2=0 CH1=0 CH0=1; A/D halt, scan AN0-AN1, 138-state max, ADI disabled)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4280,
      "address_region": "program_or_external",
      "bytes": "15FEE9067F",
      "text": "MOV:G.B #H'7F, @H'FEE9",
      "mnemonic": "MOV:G.B",
      "operands": "#H'7F, @H'FEE9",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65257,
          "name": null,
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4285,
      "address_region": "program_or_external",
      "bytes": "15FF1006F0",
      "text": "MOV:G.B #H'F0, @WCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'F0, @WCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65296,
          "name": "WCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "WCR = H'F0 (WMS1=0 WMS0=0 WC1=0 WC0=0; programmable wait, 0 waits)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4290,
      "address_region": "program_or_external",
      "bytes": "15FF1106FF",
      "text": "MOV:G.B #H'FF, @RAMCR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @RAMCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65297,
          "name": "RAMCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "RAMCR = H'FF (RAME=1; on-chip RAM enabled)",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4295,
      "address_region": "program_or_external",
      "bytes": "15FE82D7",
      "text": "BCLR.B #7, @P1DR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @P1DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65154,
          "name": "P1DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 7 of P1DR",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4299,
      "address_region": "program_or_external",
      "bytes": "302EA8",
      "text": "BRA loc_3F76",
      "mnemonic": "BRA",
      "operands": "loc_3F76",
      "kind": "jump",
      "targets": [
        16246
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4096,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R7": {
              "known": true,
              "value": 65152,
              "hex": "0xFE80",
              "width": 16,
              "source": "MOV:I.W #H'FE80, R7"
            }
          },
          "control": {
            "SR": {
              "known": true,
              "value": 1792,
              "hex": "0x0700",
              "width": 16,
              "source": "LDC.W #H'0700, SR"
            }
          }
        }
      }
    },
    {
      "address": 4302,
      "address_region": "program_or_external",
      "bytes": "5C0040",
      "text": "MOV:I.W #H'0040, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0040, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 64,
              "hex": "0x0040",
              "width": 16,
              "source": "MOV:I.W #H'0040, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0040"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 64,
              "hex": "0x0040",
              "width": 16,
              "source": "MOV:I.W #H'0040, R4"
            }
          }
        }
      }
    },
    {
      "address": 4305,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 64,
              "hex": "0x0040",
              "width": 16,
              "source": "MOV:I.W #H'0040, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4308,
      "address_region": "program_or_external",
      "bytes": "1E2DF5",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 64,
              "hex": "0x0040",
              "width": 16,
              "source": "MOV:I.W #H'0040, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4311,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4314,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4317,
      "address_region": "program_or_external",
      "bytes": "1E2DEC",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4320,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4323,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4326,
      "address_region": "program_or_external",
      "bytes": "1E2DE3",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4329,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4332,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4335,
      "address_region": "program_or_external",
      "bytes": "1E2DDA",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4338,
      "address_region": "program_or_external",
      "bytes": "5C0207",
      "text": "MOV:I.W #H'0207, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0207, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 519,
              "hex": "0x0207",
              "width": 16,
              "source": "MOV:I.W #H'0207, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0207"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 519,
              "hex": "0x0207",
              "width": 16,
              "source": "MOV:I.W #H'0207, R4"
            }
          }
        }
      }
    },
    {
      "address": 4341,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 519,
              "hex": "0x0207",
              "width": 16,
              "source": "MOV:I.W #H'0207, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4344,
      "address_region": "program_or_external",
      "bytes": "1E2DD1",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 519,
              "hex": "0x0207",
              "width": 16,
              "source": "MOV:I.W #H'0207, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4347,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4350,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4353,
      "address_region": "program_or_external",
      "bytes": "1E2DC8",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4356,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4359,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4362,
      "address_region": "program_or_external",
      "bytes": "1E2DBF",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4365,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4368,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4371,
      "address_region": "program_or_external",
      "bytes": "1E2DB6",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4374,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4377,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4380,
      "address_region": "program_or_external",
      "bytes": "1E2DAD",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4383,
      "address_region": "program_or_external",
      "bytes": "5C0048",
      "text": "MOV:I.W #H'0048, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0048, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 72,
              "hex": "0x0048",
              "width": 16,
              "source": "MOV:I.W #H'0048, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0048"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 72,
              "hex": "0x0048",
              "width": 16,
              "source": "MOV:I.W #H'0048, R4"
            }
          }
        }
      }
    },
    {
      "address": 4386,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 72,
              "hex": "0x0048",
              "width": 16,
              "source": "MOV:I.W #H'0048, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4389,
      "address_region": "program_or_external",
      "bytes": "1E2DA4",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 72,
              "hex": "0x0048",
              "width": 16,
              "source": "MOV:I.W #H'0048, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4392,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4395,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4398,
      "address_region": "program_or_external",
      "bytes": "1E2D9B",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4401,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4404,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4407,
      "address_region": "program_or_external",
      "bytes": "1E2D92",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4410,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4413,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4416,
      "address_region": "program_or_external",
      "bytes": "1E2D89",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4419,
      "address_region": "program_or_external",
      "bytes": "5C021B",
      "text": "MOV:I.W #H'021B, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'021B, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 539,
              "hex": "0x021B",
              "width": 16,
              "source": "MOV:I.W #H'021B, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x021B"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 539,
              "hex": "0x021B",
              "width": 16,
              "source": "MOV:I.W #H'021B, R4"
            }
          }
        }
      }
    },
    {
      "address": 4422,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 539,
              "hex": "0x021B",
              "width": 16,
              "source": "MOV:I.W #H'021B, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4425,
      "address_region": "program_or_external",
      "bytes": "1E2D80",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 539,
              "hex": "0x021B",
              "width": 16,
              "source": "MOV:I.W #H'021B, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4428,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4431,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4434,
      "address_region": "program_or_external",
      "bytes": "1E2D77",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4437,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4440,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4443,
      "address_region": "program_or_external",
      "bytes": "1E2D6E",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4446,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4449,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4452,
      "address_region": "program_or_external",
      "bytes": "1E2D65",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4455,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4458,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4461,
      "address_region": "program_or_external",
      "bytes": "1E2D5C",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4464,
      "address_region": "program_or_external",
      "bytes": "5C0050",
      "text": "MOV:I.W #H'0050, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0050, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 80,
              "hex": "0x0050",
              "width": 16,
              "source": "MOV:I.W #H'0050, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0050"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 80,
              "hex": "0x0050",
              "width": 16,
              "source": "MOV:I.W #H'0050, R4"
            }
          }
        }
      }
    },
    {
      "address": 4467,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 80,
              "hex": "0x0050",
              "width": 16,
              "source": "MOV:I.W #H'0050, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4470,
      "address_region": "program_or_external",
      "bytes": "1E2D53",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 80,
              "hex": "0x0050",
              "width": 16,
              "source": "MOV:I.W #H'0050, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4473,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4476,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4479,
      "address_region": "program_or_external",
      "bytes": "1E2D4A",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4482,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4485,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4488,
      "address_region": "program_or_external",
      "bytes": "1E2D41",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4491,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4494,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4497,
      "address_region": "program_or_external",
      "bytes": "1E2D38",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4500,
      "address_region": "program_or_external",
      "bytes": "5C021C",
      "text": "MOV:I.W #H'021C, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'021C, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 540,
              "hex": "0x021C",
              "width": 16,
              "source": "MOV:I.W #H'021C, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x021C"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 540,
              "hex": "0x021C",
              "width": 16,
              "source": "MOV:I.W #H'021C, R4"
            }
          }
        }
      }
    },
    {
      "address": 4503,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 540,
              "hex": "0x021C",
              "width": 16,
              "source": "MOV:I.W #H'021C, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4506,
      "address_region": "program_or_external",
      "bytes": "1E2D2F",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 540,
              "hex": "0x021C",
              "width": 16,
              "source": "MOV:I.W #H'021C, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4509,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4512,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4515,
      "address_region": "program_or_external",
      "bytes": "1E2D26",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4518,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4521,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4524,
      "address_region": "program_or_external",
      "bytes": "1E2D1D",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4527,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4530,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4533,
      "address_region": "program_or_external",
      "bytes": "1E2D14",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4536,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4539,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4542,
      "address_region": "program_or_external",
      "bytes": "1E2D0B",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4545,
      "address_region": "program_or_external",
      "bytes": "5C0058",
      "text": "MOV:I.W #H'0058, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0058, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 88,
              "hex": "0x0058",
              "width": 16,
              "source": "MOV:I.W #H'0058, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0058"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 88,
              "hex": "0x0058",
              "width": 16,
              "source": "MOV:I.W #H'0058, R4"
            }
          }
        }
      }
    },
    {
      "address": 4548,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 88,
              "hex": "0x0058",
              "width": 16,
              "source": "MOV:I.W #H'0058, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4551,
      "address_region": "program_or_external",
      "bytes": "1E2D02",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 88,
              "hex": "0x0058",
              "width": 16,
              "source": "MOV:I.W #H'0058, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4554,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4557,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4560,
      "address_region": "program_or_external",
      "bytes": "1E2CF9",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4563,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4566,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4569,
      "address_region": "program_or_external",
      "bytes": "1E2CF0",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4572,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4575,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4578,
      "address_region": "program_or_external",
      "bytes": "1E2CE7",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4581,
      "address_region": "program_or_external",
      "bytes": "5C0207",
      "text": "MOV:I.W #H'0207, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0207, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 519,
              "hex": "0x0207",
              "width": 16,
              "source": "MOV:I.W #H'0207, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0207"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 519,
              "hex": "0x0207",
              "width": 16,
              "source": "MOV:I.W #H'0207, R4"
            }
          }
        }
      }
    },
    {
      "address": 4584,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 519,
              "hex": "0x0207",
              "width": 16,
              "source": "MOV:I.W #H'0207, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4587,
      "address_region": "program_or_external",
      "bytes": "1E2CDE",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 519,
              "hex": "0x0207",
              "width": 16,
              "source": "MOV:I.W #H'0207, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4590,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4593,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4596,
      "address_region": "program_or_external",
      "bytes": "1E2CD5",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4599,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4602,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4605,
      "address_region": "program_or_external",
      "bytes": "1E2CCC",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4608,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4611,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4614,
      "address_region": "program_or_external",
      "bytes": "1E2CC3",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4617,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4620,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4623,
      "address_region": "program_or_external",
      "bytes": "1E2CBA",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4626,
      "address_region": "program_or_external",
      "bytes": "5C0060",
      "text": "MOV:I.W #H'0060, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0060, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 96,
              "hex": "0x0060",
              "width": 16,
              "source": "MOV:I.W #H'0060, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0060"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 96,
              "hex": "0x0060",
              "width": 16,
              "source": "MOV:I.W #H'0060, R4"
            }
          }
        }
      }
    },
    {
      "address": 4629,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 96,
              "hex": "0x0060",
              "width": 16,
              "source": "MOV:I.W #H'0060, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4632,
      "address_region": "program_or_external",
      "bytes": "1E2CB1",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 96,
              "hex": "0x0060",
              "width": 16,
              "source": "MOV:I.W #H'0060, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4635,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4638,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4641,
      "address_region": "program_or_external",
      "bytes": "1E2CA8",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4644,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4647,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4650,
      "address_region": "program_or_external",
      "bytes": "1E2C9F",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4653,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4656,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4659,
      "address_region": "program_or_external",
      "bytes": "1E2C96",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4662,
      "address_region": "program_or_external",
      "bytes": "5C021B",
      "text": "MOV:I.W #H'021B, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'021B, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 539,
              "hex": "0x021B",
              "width": 16,
              "source": "MOV:I.W #H'021B, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x021B"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 539,
              "hex": "0x021B",
              "width": 16,
              "source": "MOV:I.W #H'021B, R4"
            }
          }
        }
      }
    },
    {
      "address": 4665,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 539,
              "hex": "0x021B",
              "width": 16,
              "source": "MOV:I.W #H'021B, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4668,
      "address_region": "program_or_external",
      "bytes": "1E2C8D",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 539,
              "hex": "0x021B",
              "width": 16,
              "source": "MOV:I.W #H'021B, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4671,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4674,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4677,
      "address_region": "program_or_external",
      "bytes": "1E2C84",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4680,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4683,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4686,
      "address_region": "program_or_external",
      "bytes": "1E2C7B",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4689,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4692,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4695,
      "address_region": "program_or_external",
      "bytes": "1E2C72",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4698,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4701,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4704,
      "address_region": "program_or_external",
      "bytes": "1E2C69",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4707,
      "address_region": "program_or_external",
      "bytes": "5C0068",
      "text": "MOV:I.W #H'0068, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0068, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 104,
              "hex": "0x0068",
              "width": 16,
              "source": "MOV:I.W #H'0068, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0068"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 104,
              "hex": "0x0068",
              "width": 16,
              "source": "MOV:I.W #H'0068, R4"
            }
          }
        }
      }
    },
    {
      "address": 4710,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 104,
              "hex": "0x0068",
              "width": 16,
              "source": "MOV:I.W #H'0068, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4713,
      "address_region": "program_or_external",
      "bytes": "1E2C60",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 104,
              "hex": "0x0068",
              "width": 16,
              "source": "MOV:I.W #H'0068, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4716,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4719,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4722,
      "address_region": "program_or_external",
      "bytes": "1E2C57",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4725,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4728,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4731,
      "address_region": "program_or_external",
      "bytes": "1E2C4E",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4734,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4737,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4740,
      "address_region": "program_or_external",
      "bytes": "1E2C45",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4743,
      "address_region": "program_or_external",
      "bytes": "5C021C",
      "text": "MOV:I.W #H'021C, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'021C, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 540,
              "hex": "0x021C",
              "width": 16,
              "source": "MOV:I.W #H'021C, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x021C"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 540,
              "hex": "0x021C",
              "width": 16,
              "source": "MOV:I.W #H'021C, R4"
            }
          }
        }
      }
    },
    {
      "address": 4746,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 540,
              "hex": "0x021C",
              "width": 16,
              "source": "MOV:I.W #H'021C, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4749,
      "address_region": "program_or_external",
      "bytes": "1E2C3C",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 540,
              "hex": "0x021C",
              "width": 16,
              "source": "MOV:I.W #H'021C, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4752,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4755,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4758,
      "address_region": "program_or_external",
      "bytes": "1E2C33",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4761,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4764,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4767,
      "address_region": "program_or_external",
      "bytes": "1E2C2A",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4770,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4773,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4776,
      "address_region": "program_or_external",
      "bytes": "1E2C21",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4779,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4782,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4785,
      "address_region": "program_or_external",
      "bytes": "1E2C18",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4788,
      "address_region": "program_or_external",
      "bytes": "5C0070",
      "text": "MOV:I.W #H'0070, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0070, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 112,
              "hex": "0x0070",
              "width": 16,
              "source": "MOV:I.W #H'0070, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0070"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 112,
              "hex": "0x0070",
              "width": 16,
              "source": "MOV:I.W #H'0070, R4"
            }
          }
        }
      }
    },
    {
      "address": 4791,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 112,
              "hex": "0x0070",
              "width": 16,
              "source": "MOV:I.W #H'0070, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4794,
      "address_region": "program_or_external",
      "bytes": "1E2C0F",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 112,
              "hex": "0x0070",
              "width": 16,
              "source": "MOV:I.W #H'0070, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4797,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4800,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4803,
      "address_region": "program_or_external",
      "bytes": "1E2C06",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4806,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4809,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4812,
      "address_region": "program_or_external",
      "bytes": "1E2BFD",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4815,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4818,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4821,
      "address_region": "program_or_external",
      "bytes": "1E2BF4",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4824,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4827,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4830,
      "address_region": "program_or_external",
      "bytes": "1E2BEB",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4833,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4836,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4839,
      "address_region": "program_or_external",
      "bytes": "1E2BE2",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4842,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4845,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4848,
      "address_region": "program_or_external",
      "bytes": "1E2BD9",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4851,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4854,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4857,
      "address_region": "program_or_external",
      "bytes": "1E2BD0",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4860,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4863,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4866,
      "address_region": "program_or_external",
      "bytes": "1E2BC7",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4869,
      "address_region": "program_or_external",
      "bytes": "5C0078",
      "text": "MOV:I.W #H'0078, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0078, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 120,
              "hex": "0x0078",
              "width": 16,
              "source": "MOV:I.W #H'0078, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0078"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 120,
              "hex": "0x0078",
              "width": 16,
              "source": "MOV:I.W #H'0078, R4"
            }
          }
        }
      }
    },
    {
      "address": 4872,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 120,
              "hex": "0x0078",
              "width": 16,
              "source": "MOV:I.W #H'0078, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4875,
      "address_region": "program_or_external",
      "bytes": "1E2BBE",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 120,
              "hex": "0x0078",
              "width": 16,
              "source": "MOV:I.W #H'0078, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4878,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4881,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4884,
      "address_region": "program_or_external",
      "bytes": "1E2BB5",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4887,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4890,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4893,
      "address_region": "program_or_external",
      "bytes": "1E2BAC",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4896,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4899,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4902,
      "address_region": "program_or_external",
      "bytes": "1E2BA3",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4905,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4908,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4911,
      "address_region": "program_or_external",
      "bytes": "1E2B9A",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4914,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4917,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4920,
      "address_region": "program_or_external",
      "bytes": "1E2B91",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4923,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 4926,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4929,
      "address_region": "program_or_external",
      "bytes": "1E2B88",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4932,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4935,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4938,
      "address_region": "program_or_external",
      "bytes": "1E2B7F",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4941,
      "address_region": "program_or_external",
      "bytes": "5C0204",
      "text": "MOV:I.W #H'0204, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0204, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0204"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            }
          }
        }
      }
    },
    {
      "address": 4944,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 4947,
      "address_region": "program_or_external",
      "bytes": "1E2B76",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 516,
              "hex": "0x0204",
              "width": 16,
              "source": "MOV:I.W #H'0204, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 4950,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 4302,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5600,
      "address_region": "program_or_external",
      "bytes": "1E106D",
      "text": "BSR loc_2650",
      "mnemonic": "BSR",
      "operands": "loc_2650",
      "kind": "call",
      "targets": [
        9808
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5600,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5603,
      "address_region": "program_or_external",
      "bytes": "15F689D7",
      "text": "BCLR.B #7, @H'F689",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F689",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63113,
          "name": null,
          "symbol": "ram_F689",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5600,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5607,
      "address_region": "program_or_external",
      "bytes": "2710",
      "text": "BEQ loc_15F9",
      "mnemonic": "BEQ",
      "operands": "loc_15F9",
      "kind": "branch",
      "targets": [
        5625
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5600,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5609,
      "address_region": "program_or_external",
      "bytes": "1DF68E81",
      "text": "MOV:G.W @H'F68E, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F68E, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63118,
          "name": null,
          "symbol": "ram_F68E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5609,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 5613,
      "address_region": "program_or_external",
      "bytes": "1DE90291",
      "text": "MOV:G.W R1, @H'E902",
      "mnemonic": "MOV:G.W",
      "operands": "R1, @H'E902",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 59650,
          "name": null,
          "symbol": "mem_E902",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5609,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5617,
      "address_region": "program_or_external",
      "bytes": "5280",
      "text": "MOV:E.B #H'80, R2",
      "mnemonic": "MOV:E.B",
      "operands": "#H'80, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5609,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        ],
        "notes": [
          "R2 = 0x80"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        }
      }
    },
    {
      "address": 5619,
      "address_region": "program_or_external",
      "bytes": "5B0081",
      "text": "MOV:I.W #H'0081, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0081, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5609,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 129,
              "hex": "0x0081",
              "width": 16,
              "source": "MOV:I.W #H'0081, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x0081"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            },
            "R3": {
              "known": true,
              "value": 129,
              "hex": "0x0081",
              "width": 16,
              "source": "MOV:I.W #H'0081, R3"
            }
          }
        }
      }
    },
    {
      "address": 5622,
      "address_region": "program_or_external",
      "bytes": "1E285B",
      "text": "BSR loc_3E54",
      "mnemonic": "BSR",
      "operands": "loc_3E54",
      "kind": "call",
      "targets": [
        15956
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5609,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": true,
              "value": 129,
              "hex": "0x0081",
              "width": 16,
              "source": "MOV:I.W #H'0081, R3"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5625,
      "address_region": "program_or_external",
      "bytes": "15F6F016",
      "text": "TST.B @H'F6F0",
      "mnemonic": "TST.B",
      "operands": "@H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5625,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5629,
      "address_region": "program_or_external",
      "bytes": "273E",
      "text": "BEQ loc_163D",
      "mnemonic": "BEQ",
      "operands": "loc_163D",
      "kind": "branch",
      "targets": [
        5693
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5625,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5631,
      "address_region": "program_or_external",
      "bytes": "15F6F0D7",
      "text": "BCLR.B #7, @H'F6F0",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5631,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5635,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_1608",
      "mnemonic": "BEQ",
      "operands": "loc_1608",
      "kind": "branch",
      "targets": [
        5640
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5631,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5637,
      "address_region": "program_or_external",
      "bytes": "184394",
      "text": "JSR @loc_4394",
      "mnemonic": "JSR",
      "operands": "@loc_4394",
      "kind": "call",
      "targets": [
        17300
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5637,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5640,
      "address_region": "program_or_external",
      "bytes": "15F6F0D6",
      "text": "BCLR.B #6, @H'F6F0",
      "mnemonic": "BCLR.B",
      "operands": "#6, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5640,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5644,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_1611",
      "mnemonic": "BEQ",
      "operands": "loc_1611",
      "kind": "branch",
      "targets": [
        5649
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5640,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5646,
      "address_region": "program_or_external",
      "bytes": "184457",
      "text": "JSR @loc_4457",
      "mnemonic": "JSR",
      "operands": "@loc_4457",
      "kind": "call",
      "targets": [
        17495
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5646,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5649,
      "address_region": "program_or_external",
      "bytes": "15F6F0D5",
      "text": "BCLR.B #5, @H'F6F0",
      "mnemonic": "BCLR.B",
      "operands": "#5, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5649,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5653,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_161A",
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            "name": "DP",
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              "known": false,
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
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            "kind": "control",
            "name": "SR",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
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          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5689,
      "address_region": "program_or_external",
      "bytes": "15F6F0D0",
      "text": "BCLR.B #0, @H'F6F0",
      "mnemonic": "BCLR.B",
      "operands": "#0, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5689,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5693,
      "address_region": "program_or_external",
      "bytes": "15F6F116",
      "text": "TST.B @H'F6F1",
      "mnemonic": "TST.B",
      "operands": "@H'F6F1",
      "kind": "normal",
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      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5693,
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            "kind": "control",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5697,
      "address_region": "program_or_external",
      "bytes": "2743",
      "text": "BEQ loc_1686",
      "mnemonic": "BEQ",
      "operands": "loc_1686",
      "kind": "branch",
      "targets": [
        5766
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5693,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5699,
      "address_region": "program_or_external",
      "bytes": "15F6F1D7",
      "text": "BCLR.B #7, @H'F6F1",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5699,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
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              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5703,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_164C",
      "mnemonic": "BEQ",
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      ],
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        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "valid": true,
      "dataflow": {
        "block": 5699,
        "changes": [],
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      }
    },
    {
      "address": 5705,
      "address_region": "program_or_external",
      "bytes": "1817C9",
      "text": "JSR @loc_17C9",
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      "operands": "@loc_17C9",
      "kind": "call",
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      ],
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        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5705,
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            "kind": "register",
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            "kind": "register",
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            "kind": "register",
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            "kind": "register",
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              "reason": "block_entry"
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          },
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            "kind": "register",
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          },
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            "kind": "control",
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          },
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            "kind": "control",
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              "known": false,
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            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "EP",
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              "known": false,
              "reason": "block_entry"
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              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "DP",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "SR",
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              "known": false,
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              "known": false,
              "reason": "call"
            }
          }
        ],
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          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5708,
      "address_region": "program_or_external",
      "bytes": "15F6F1D6",
      "text": "BCLR.B #6, @H'F6F1",
      "mnemonic": "BCLR.B",
      "operands": "#6, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
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        "changes": [
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
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      }
    },
    {
      "address": 5712,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_1655",
      "mnemonic": "BEQ",
      "operands": "loc_1655",
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        "taken": 7,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
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        "block": 5708,
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      }
    },
    {
      "address": 5714,
      "address_region": "program_or_external",
      "bytes": "1817FB",
      "text": "JSR @loc_17FB",
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      "operands": "@loc_17FB",
      "kind": "call",
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      ],
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        "stack_adjustment": 4,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "dataflow": {
        "block": 5714,
        "changes": [
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            "kind": "register",
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            "kind": "register",
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            "kind": "register",
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          },
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          {
            "kind": "control",
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          },
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            "kind": "control",
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          },
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            "kind": "control",
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              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
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              "known": false,
              "reason": "block_entry"
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            "after": {
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          },
          {
            "kind": "control",
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              "known": false,
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              "known": false,
              "reason": "call"
            }
          }
        ],
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        ]
      }
    },
    {
      "address": 5717,
      "address_region": "program_or_external",
      "bytes": "15F6F1D5",
      "text": "BCLR.B #5, @H'F6F1",
      "mnemonic": "BCLR.B",
      "operands": "#5, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
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        "changes": [
          {
            "kind": "control",
            "name": "CCR",
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              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5721,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_165E",
      "mnemonic": "BEQ",
      "operands": "loc_165E",
      "kind": "branch",
      "targets": [
        5726
      ],
      "cycles": {
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        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5717,
        "changes": [],
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      }
    },
    {
      "address": 5723,
      "address_region": "program_or_external",
      "bytes": "18182D",
      "text": "JSR @loc_182D",
      "mnemonic": "JSR",
      "operands": "@loc_182D",
      "kind": "call",
      "targets": [
        6189
      ],
      "cycles": {
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        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5723,
        "changes": [
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            "kind": "register",
            "name": "R0",
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              "known": false,
              "reason": "block_entry"
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          },
          {
            "kind": "register",
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              "reason": "call"
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          },
          {
            "kind": "register",
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            "kind": "register",
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          },
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            "kind": "register",
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          },
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              "reason": "block_entry"
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          },
          {
            "kind": "register",
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          },
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          },
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          },
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "control",
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              "known": false,
              "reason": "block_entry"
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          },
          {
            "kind": "control",
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            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
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        ]
      }
    },
    {
      "address": 5726,
      "address_region": "program_or_external",
      "bytes": "15F6F1D4",
      "text": "BCLR.B #4, @H'F6F1",
      "mnemonic": "BCLR.B",
      "operands": "#4, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
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        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
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      "dataflow": {
        "block": 5726,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
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          }
        ],
        "notes": []
      }
    },
    {
      "address": 5730,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_1667",
      "mnemonic": "BEQ",
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      "targets": [
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        "taken": 7,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      }
    },
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      "address": 5732,
      "address_region": "program_or_external",
      "bytes": "181891",
      "text": "JSR @loc_1891",
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        "source": "manual Appendix A.4, tables A-7/A-8",
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      },
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      "bytes": "15F6F1D3",
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      "targets": [],
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        "source": "manual Appendix A.4, tables A-7/A-8",
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      },
      "references": [
        {
          "address": 63217,
          "name": null,
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      "bytes": "15F6F1D2",
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      "targets": [],
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        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
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    {
      "address": 5748,
      "address_region": "program_or_external",
      "bytes": "2703",
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        "source": "manual Appendix A.4, tables A-7/A-8",
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      },
      "references": [],
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    },
    {
      "address": 5750,
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        "assumption": "on-chip instruction fetch/operand access, no external wait states"
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      "address": 5753,
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      "operands": "#1, @H'F6F1",
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      "targets": [],
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
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        }
      ],
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            "kind": "control",
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    },
    {
      "address": 5757,
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      "bytes": "2703",
      "text": "BEQ loc_1682",
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        "source": "manual Appendix A.4, tables A-7/A-8",
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      },
      "references": [],
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    },
    {
      "address": 5759,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
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      "references": [],
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      "dataflow": {
        "block": 5759,
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          },
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              "reason": "call"
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          },
          {
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          }
        ],
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    },
    {
      "address": 5762,
      "address_region": "program_or_external",
      "bytes": "15F6F1D0",
      "text": "BCLR.B #0, @H'F6F1",
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      "references": [
        {
          "address": 63217,
          "name": null,
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      "address": 5766,
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          "address": 63218,
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      "address": 5770,
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    },
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      "bytes": "15F6F2D7",
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      "references": [
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          "address": 63218,
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      "address": 5781,
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      "bytes": "15F6F2D6",
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        "source": "manual Appendix A.4, tables A-7/A-8",
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      },
      "references": [
        {
          "address": 63218,
          "name": null,
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      "address": 5785,
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    {
      "address": 5790,
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        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
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      "dataflow": {
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        "changes": [
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            "kind": "control",
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            "after": {
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              "reason": "flags"
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    },
    {
      "address": 5794,
      "address_region": "program_or_external",
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      },
      "references": [],
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    },
    {
      "address": 5796,
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      "bytes": "181B5B",
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
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      "references": [],
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      "dataflow": {
        "block": 5796,
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            "kind": "register",
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          },
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        ],
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    },
    {
      "address": 5799,
      "address_region": "program_or_external",
      "bytes": "15F6F2D4",
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        "source": "manual Appendix A.4, tables A-7/A-8",
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      "references": [
        {
          "address": 63218,
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          }
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    },
    {
      "address": 5803,
      "address_region": "program_or_external",
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        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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    },
    {
      "address": 5805,
      "address_region": "program_or_external",
      "bytes": "181BA0",
      "text": "JSR @loc_1BA0",
      "mnemonic": "JSR",
      "operands": "@loc_1BA0",
      "kind": "call",
      "targets": [
        7072
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5805,
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            "kind": "register",
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          },
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            "kind": "control",
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              "reason": "block_entry"
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              "reason": "call"
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          },
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            "kind": "control",
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          },
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              "reason": "call"
            }
          }
        ],
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          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5808,
      "address_region": "program_or_external",
      "bytes": "15F6F2D3",
      "text": "BCLR.B #3, @H'F6F2",
      "mnemonic": "BCLR.B",
      "operands": "#3, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
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        "block": 5808,
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          {
            "kind": "control",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
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      }
    },
    {
      "address": 5812,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_16B9",
      "mnemonic": "BEQ",
      "operands": "loc_16B9",
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      ],
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        "taken": 7,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "valid": true,
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        "block": 5808,
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      }
    },
    {
      "address": 5814,
      "address_region": "program_or_external",
      "bytes": "181BB6",
      "text": "JSR @loc_1BB6",
      "mnemonic": "JSR",
      "operands": "@loc_1BB6",
      "kind": "call",
      "targets": [
        7094
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        "stack_adjustment": 4,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
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      "dataflow": {
        "block": 5814,
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            "kind": "register",
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          },
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            "kind": "register",
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            "kind": "register",
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          },
          {
            "kind": "register",
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          },
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            "kind": "register",
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            "kind": "register",
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          },
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          },
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          },
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          },
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            "kind": "control",
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          },
          {
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          },
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          },
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          }
        ],
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          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5817,
      "address_region": "program_or_external",
      "bytes": "15F6F2D2",
      "text": "BCLR.B #2, @H'F6F2",
      "mnemonic": "BCLR.B",
      "operands": "#2, @H'F6F2",
      "kind": "normal",
      "targets": [],
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        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
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          {
            "kind": "control",
            "name": "CCR",
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              "reason": "block_entry"
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            "after": {
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              "reason": "flags"
            }
          }
        ],
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      }
    },
    {
      "address": 5821,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_16C2",
      "mnemonic": "BEQ",
      "operands": "loc_16C2",
      "kind": "branch",
      "targets": [
        5826
      ],
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        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5817,
        "changes": [],
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      }
    },
    {
      "address": 5823,
      "address_region": "program_or_external",
      "bytes": "181BCC",
      "text": "JSR @loc_1BCC",
      "mnemonic": "JSR",
      "operands": "@loc_1BCC",
      "kind": "call",
      "targets": [
        7116
      ],
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        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "dataflow": {
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            "kind": "register",
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          },
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          },
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            "kind": "register",
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          },
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          },
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          },
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          },
          {
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          },
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          },
          {
            "kind": "control",
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          },
          {
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          },
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          },
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              "reason": "call"
            }
          }
        ],
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          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5826,
      "address_region": "program_or_external",
      "bytes": "15F6F2D1",
      "text": "BCLR.B #1, @H'F6F2",
      "mnemonic": "BCLR.B",
      "operands": "#1, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5826,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5830,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_16CB",
      "mnemonic": "BEQ",
      "operands": "loc_16CB",
      "kind": "branch",
      "targets": [
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        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
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      "dataflow": {
        "block": 5826,
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        "notes": []
      }
    },
    {
      "address": 5832,
      "address_region": "program_or_external",
      "bytes": "181B72",
      "text": "JSR @loc_1B72",
      "mnemonic": "JSR",
      "operands": "@loc_1B72",
      "kind": "call",
      "targets": [
        7026
      ],
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        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5832,
        "changes": [
          {
            "kind": "register",
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              "reason": "block_entry"
            },
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          },
          {
            "kind": "register",
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            }
          },
          {
            "kind": "register",
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            "kind": "register",
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          },
          {
            "kind": "register",
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          },
          {
            "kind": "register",
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              "reason": "block_entry"
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          },
          {
            "kind": "register",
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              "reason": "call"
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          },
          {
            "kind": "register",
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              "reason": "block_entry"
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          },
          {
            "kind": "control",
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              "reason": "call"
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          },
          {
            "kind": "control",
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              "reason": "block_entry"
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "control",
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              "reason": "call"
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          },
          {
            "kind": "control",
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              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
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              "reason": "call"
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          },
          {
            "kind": "control",
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              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5835,
      "address_region": "program_or_external",
      "bytes": "15F6F2D0",
      "text": "BCLR.B #0, @H'F6F2",
      "mnemonic": "BCLR.B",
      "operands": "#0, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
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      "address": 5839,
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      "address": 5841,
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        {
          "address": 63219,
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          "address": 63219,
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          "address": 63219,
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          },
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          }
        ],
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    },
    {
      "address": 5880,
      "address_region": "program_or_external",
      "bytes": "15F6F3D2",
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      "references": [
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          "address": 63219,
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        }
      ],
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            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5884,
      "address_region": "program_or_external",
      "bytes": "15F6F3D1",
      "text": "BCLR.B #1, @H'F6F3",
      "mnemonic": "BCLR.B",
      "operands": "#1, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5880,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5888,
      "address_region": "program_or_external",
      "bytes": "15F6F3D0",
      "text": "BCLR.B #0, @H'F6F3",
      "mnemonic": "BCLR.B",
      "operands": "#0, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5880,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5892,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5892,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5893,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5893,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5898,
      "address_region": "program_or_external",
      "bytes": "2238",
      "text": "BHI loc_1744",
      "mnemonic": "BHI",
      "operands": "loc_1744",
      "kind": "branch",
      "targets": [
        5956
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5893,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5900,
      "address_region": "program_or_external",
      "bytes": "1DE14EFF",
      "text": "BTST.W #15, @H'E14E",
      "mnemonic": "BTST.W",
      "operands": "#15, @H'E14E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57678,
          "name": null,
          "symbol": "mem_E14E",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5900,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5904,
      "address_region": "program_or_external",
      "bytes": "2624",
      "text": "BNE loc_1736",
      "mnemonic": "BNE",
      "operands": "loc_1736",
      "kind": "branch",
      "targets": [
        5942
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5900,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5906,
      "address_region": "program_or_external",
      "bytes": "15F730F6",
      "text": "BTST.B #6, @H'F730",
      "mnemonic": "BTST.B",
      "operands": "#6, @H'F730",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63280,
          "name": null,
          "symbol": "ram_F730",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5906,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5910,
      "address_region": "program_or_external",
      "bytes": "261E",
      "text": "BNE loc_1736",
      "mnemonic": "BNE",
      "operands": "loc_1736",
      "kind": "branch",
      "targets": [
        5942
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5906,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5912,
      "address_region": "program_or_external",
      "bytes": "15FB03C7",
      "text": "BSET.B #7, @H'FB03",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'FB03",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
          "name": null,
          "symbol": "ram_FB03",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5912,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5916,
      "address_region": "program_or_external",
      "bytes": "2608",
      "text": "BNE loc_1726",
      "mnemonic": "BNE",
      "operands": "loc_1726",
      "kind": "branch",
      "targets": [
        5926
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5912,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5918,
      "address_region": "program_or_external",
      "bytes": "1DF73281",
      "text": "MOV:G.W @H'F732, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F732, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5918,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 5922,
      "address_region": "program_or_external",
      "bytes": "1DF73491",
      "text": "MOV:G.W R1, @H'F734",
      "mnemonic": "MOV:G.W",
      "operands": "R1, @H'F734",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63284,
          "name": null,
          "symbol": "ram_F734",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5918,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5926,
      "address_region": "program_or_external",
      "bytes": "1DF732071C07",
      "text": "MOV:G.W #H'1C07, @H'F732",
      "mnemonic": "MOV:G.W",
      "operands": "#H'1C07, @H'F732",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5926,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5932,
      "address_region": "program_or_external",
      "bytes": "15FB020614",
      "text": "MOV:G.B #H'14, @H'FB02",
      "mnemonic": "MOV:G.B",
      "operands": "#H'14, @H'FB02",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64258,
          "name": null,
          "symbol": "ram_FB02",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5926,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5937,
      "address_region": "program_or_external",
      "bytes": "1E31C6",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5926,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5940,
      "address_region": "program_or_external",
      "bytes": "200E",
      "text": "BRA loc_1744",
      "mnemonic": "BRA",
      "operands": "loc_1744",
      "kind": "jump",
      "targets": [
        5956
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5926,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5942,
      "address_region": "program_or_external",
      "bytes": "1DF69684",
      "text": "MOV:G.W @H'F696, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F696, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63126,
          "name": null,
          "symbol": "ram_F696",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5942,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 5946,
      "address_region": "program_or_external",
      "bytes": "1DF6B634",
      "text": "SUB.W @H'F6B6, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6B6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63158,
          "name": null,
          "symbol": "ram_F6B6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5942,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 5950,
      "address_region": "program_or_external",
      "bytes": "5B00A9",
      "text": "MOV:I.W #H'00A9, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00A9, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5942,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 169,
              "hex": "0x00A9",
              "width": 16,
              "source": "MOV:I.W #H'00A9, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00A9"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 169,
              "hex": "0x00A9",
              "width": 16,
              "source": "MOV:I.W #H'00A9, R3"
            }
          }
        }
      }
    },
    {
      "address": 5953,
      "address_region": "program_or_external",
      "bytes": "1E025E",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5942,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": true,
              "value": 169,
              "hex": "0x00A9",
              "width": 16,
              "source": "MOV:I.W #H'00A9, R3"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 5956,
      "address_region": "program_or_external",
      "bytes": "1DF69684",
      "text": "MOV:G.W @H'F696, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F696, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63126,
          "name": null,
          "symbol": "ram_F696",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5956,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 5960,
      "address_region": "program_or_external",
      "bytes": "1DF6B694",
      "text": "MOV:G.W R4, @H'F6B6",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6B6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63158,
          "name": null,
          "symbol": "ram_F6B6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5956,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5964,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5956,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5965,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5965,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5970,
      "address_region": "program_or_external",
      "bytes": "2238",
      "text": "BHI loc_178C",
      "mnemonic": "BHI",
      "operands": "loc_178C",
      "kind": "branch",
      "targets": [
        6028
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5965,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5972,
      "address_region": "program_or_external",
      "bytes": "15F730F7",
      "text": "BTST.B #7, @H'F730",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F730",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63280,
          "name": null,
          "symbol": "ram_F730",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5972,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5976,
      "address_region": "program_or_external",
      "bytes": "2732",
      "text": "BEQ loc_178C",
      "mnemonic": "BEQ",
      "operands": "loc_178C",
      "kind": "branch",
      "targets": [
        6028
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5972,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5978,
      "address_region": "program_or_external",
      "bytes": "1DE16EFD",
      "text": "BTST.W #13, @H'E16E",
      "mnemonic": "BTST.W",
      "operands": "#13, @H'E16E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57710,
          "name": null,
          "symbol": "mem_E16E",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5978,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5982,
      "address_region": "program_or_external",
      "bytes": "261E",
      "text": "BNE loc_177E",
      "mnemonic": "BNE",
      "operands": "loc_177E",
      "kind": "branch",
      "targets": [
        6014
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5978,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5984,
      "address_region": "program_or_external",
      "bytes": "15FB03C7",
      "text": "BSET.B #7, @H'FB03",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'FB03",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
          "name": null,
          "symbol": "ram_FB03",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5984,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 5988,
      "address_region": "program_or_external",
      "bytes": "2608",
      "text": "BNE loc_176E",
      "mnemonic": "BNE",
      "operands": "loc_176E",
      "kind": "branch",
      "targets": [
        5998
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5984,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5990,
      "address_region": "program_or_external",
      "bytes": "1DF73281",
      "text": "MOV:G.W @H'F732, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F732, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5990,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 5994,
      "address_region": "program_or_external",
      "bytes": "1DF73491",
      "text": "MOV:G.W R1, @H'F734",
      "mnemonic": "MOV:G.W",
      "operands": "R1, @H'F734",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63284,
          "name": null,
          "symbol": "ram_F734",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5990,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 5998,
      "address_region": "program_or_external",
      "bytes": "1DF732071C06",
      "text": "MOV:G.W #H'1C06, @H'F732",
      "mnemonic": "MOV:G.W",
      "operands": "#H'1C06, @H'F732",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5998,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6004,
      "address_region": "program_or_external",
      "bytes": "15FB020614",
      "text": "MOV:G.B #H'14, @H'FB02",
      "mnemonic": "MOV:G.B",
      "operands": "#H'14, @H'FB02",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64258,
          "name": null,
          "symbol": "ram_FB02",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5998,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6009,
      "address_region": "program_or_external",
      "bytes": "1E317E",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5998,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6012,
      "address_region": "program_or_external",
      "bytes": "200E",
      "text": "BRA loc_178C",
      "mnemonic": "BRA",
      "operands": "loc_178C",
      "kind": "jump",
      "targets": [
        6028
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 5998,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6014,
      "address_region": "program_or_external",
      "bytes": "1DF69484",
      "text": "MOV:G.W @H'F694, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F694, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63124,
          "name": null,
          "symbol": "ram_F694",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6014,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6018,
      "address_region": "program_or_external",
      "bytes": "1DF6B434",
      "text": "SUB.W @H'F6B4, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6B4, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63156,
          "name": null,
          "symbol": "ram_F6B4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6014,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6022,
      "address_region": "program_or_external",
      "bytes": "5B00C5",
      "text": "MOV:I.W #H'00C5, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00C5, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6014,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 197,
              "hex": "0x00C5",
              "width": 16,
              "source": "MOV:I.W #H'00C5, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00C5"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 197,
              "hex": "0x00C5",
              "width": 16,
              "source": "MOV:I.W #H'00C5, R3"
            }
          }
        }
      }
    },
    {
      "address": 6025,
      "address_region": "program_or_external",
      "bytes": "1E0216",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6014,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": true,
              "value": 197,
              "hex": "0x00C5",
              "width": 16,
              "source": "MOV:I.W #H'00C5, R3"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6028,
      "address_region": "program_or_external",
      "bytes": "1DF69484",
      "text": "MOV:G.W @H'F694, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F694, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63124,
          "name": null,
          "symbol": "ram_F694",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6028,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6032,
      "address_region": "program_or_external",
      "bytes": "1DF6B494",
      "text": "MOV:G.W R4, @H'F6B4",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6B4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63156,
          "name": null,
          "symbol": "ram_F6B4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6028,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6036,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6028,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6037,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6037,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6042,
      "address_region": "program_or_external",
      "bytes": "2224",
      "text": "BHI loc_17C0",
      "mnemonic": "BHI",
      "operands": "loc_17C0",
      "kind": "branch",
      "targets": [
        6080
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6037,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6044,
      "address_region": "program_or_external",
      "bytes": "1DE172FD",
      "text": "BTST.W #13, @H'E172",
      "mnemonic": "BTST.W",
      "operands": "#13, @H'E172",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57714,
          "name": null,
          "symbol": "mem_E172",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6044,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6048,
      "address_region": "program_or_external",
      "bytes": "2605",
      "text": "BNE loc_17A7",
      "mnemonic": "BNE",
      "operands": "loc_17A7",
      "kind": "branch",
      "targets": [
        6055
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6044,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6050,
      "address_region": "program_or_external",
      "bytes": "1E0982",
      "text": "BSR loc_2127",
      "mnemonic": "BSR",
      "operands": "loc_2127",
      "kind": "call",
      "targets": [
        8487
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6050,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6053,
      "address_region": "program_or_external",
      "bytes": "2019",
      "text": "BRA loc_17C0",
      "mnemonic": "BRA",
      "operands": "loc_17C0",
      "kind": "jump",
      "targets": [
        6080
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6050,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6055,
      "address_region": "program_or_external",
      "bytes": "1DE220FF",
      "text": "BTST.W #15, @H'E220",
      "mnemonic": "BTST.W",
      "operands": "#15, @H'E220",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57888,
          "name": null,
          "symbol": "mem_E220",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6055,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6059,
      "address_region": "program_or_external",
      "bytes": "2705",
      "text": "BEQ loc_17B2",
      "mnemonic": "BEQ",
      "operands": "loc_17B2",
      "kind": "branch",
      "targets": [
        6066
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6055,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6061,
      "address_region": "program_or_external",
      "bytes": "1E0977",
      "text": "BSR loc_2127",
      "mnemonic": "BSR",
      "operands": "loc_2127",
      "kind": "call",
      "targets": [
        8487
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6061,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6064,
      "address_region": "program_or_external",
      "bytes": "200E",
      "text": "BRA loc_17C0",
      "mnemonic": "BRA",
      "operands": "loc_17C0",
      "kind": "jump",
      "targets": [
        6080
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6061,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6066,
      "address_region": "program_or_external",
      "bytes": "1DF69284",
      "text": "MOV:G.W @H'F692, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F692, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63122,
          "name": null,
          "symbol": "ram_F692",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6066,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6070,
      "address_region": "program_or_external",
      "bytes": "1DF6B234",
      "text": "SUB.W @H'F6B2, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6B2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63154,
          "name": null,
          "symbol": "ram_F6B2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6066,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6074,
      "address_region": "program_or_external",
      "bytes": "5B00BC",
      "text": "MOV:I.W #H'00BC, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00BC, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6066,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 188,
              "hex": "0x00BC",
              "width": 16,
              "source": "MOV:I.W #H'00BC, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00BC"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 188,
              "hex": "0x00BC",
              "width": 16,
              "source": "MOV:I.W #H'00BC, R3"
            }
          }
        }
      }
    },
    {
      "address": 6077,
      "address_region": "program_or_external",
      "bytes": "1E01E2",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6066,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": true,
              "value": 188,
              "hex": "0x00BC",
              "width": 16,
              "source": "MOV:I.W #H'00BC, R3"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6080,
      "address_region": "program_or_external",
      "bytes": "1DF69284",
      "text": "MOV:G.W @H'F692, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F692, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63122,
          "name": null,
          "symbol": "ram_F692",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6080,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6084,
      "address_region": "program_or_external",
      "bytes": "1DF6B294",
      "text": "MOV:G.W R4, @H'F6B2",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6B2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63154,
          "name": null,
          "symbol": "ram_F6B2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6080,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6088,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6080,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6089,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6089,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6094,
      "address_region": "program_or_external",
      "bytes": "2222",
      "text": "BHI loc_17F2",
      "mnemonic": "BHI",
      "operands": "loc_17F2",
      "kind": "branch",
      "targets": [
        6130
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6089,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6096,
      "address_region": "program_or_external",
      "bytes": "1DE126FC",
      "text": "BTST.W #12, @H'E126",
      "mnemonic": "BTST.W",
      "operands": "#12, @H'E126",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57638,
          "name": null,
          "symbol": "mem_E126",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6096,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6100,
      "address_region": "program_or_external",
      "bytes": "271C",
      "text": "BEQ loc_17F2",
      "mnemonic": "BEQ",
      "operands": "loc_17F2",
      "kind": "branch",
      "targets": [
        6130
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6096,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6102,
      "address_region": "program_or_external",
      "bytes": "1DF6AE84",
      "text": "MOV:G.W @H'F6AE, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6AE, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63150,
          "name": null,
          "symbol": "ram_F6AE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6102,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6106,
      "address_region": "program_or_external",
      "bytes": "1DF6CE34",
      "text": "SUB.W @H'F6CE, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6CE, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63182,
          "name": null,
          "symbol": "ram_F6CE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6102,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6110,
      "address_region": "program_or_external",
      "bytes": "5B00A3",
      "text": "MOV:I.W #H'00A3, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00A3, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6102,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 163,
              "hex": "0x00A3",
              "width": 16,
              "source": "MOV:I.W #H'00A3, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00A3"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 163,
              "hex": "0x00A3",
              "width": 16,
              "source": "MOV:I.W #H'00A3, R3"
            }
          }
        }
      }
    },
    {
      "address": 6113,
      "address_region": "program_or_external",
      "bytes": "15F791F7",
      "text": "BTST.B #7, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6102,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 163,
              "hex": "0x00A3",
              "width": 16,
              "source": "MOV:I.W #H'00A3, R3"
            }
          }
        }
      }
    },
    {
      "address": 6117,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_17EF",
      "mnemonic": "BEQ",
      "operands": "loc_17EF",
      "kind": "branch",
      "targets": [
        6127
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6102,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 163,
              "hex": "0x00A3",
              "width": 16,
              "source": "MOV:I.W #H'00A3, R3"
            }
          }
        }
      }
    },
    {
      "address": 6119,
      "address_region": "program_or_external",
      "bytes": "15F404F3",
      "text": "BTST.B #3, @H'F404",
      "mnemonic": "BTST.B",
      "operands": "#3, @H'F404",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62468,
          "name": null,
          "symbol": "mem_F404",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6119,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6123,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_17EF",
      "mnemonic": "BEQ",
      "operands": "loc_17EF",
      "kind": "branch",
      "targets": [
        6127
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6119,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6125,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6125,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6127,
      "address_region": "program_or_external",
      "bytes": "1E01B0",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6127,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6130,
      "address_region": "program_or_external",
      "bytes": "1DF6AE84",
      "text": "MOV:G.W @H'F6AE, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6AE, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63150,
          "name": null,
          "symbol": "ram_F6AE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6130,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6134,
      "address_region": "program_or_external",
      "bytes": "1DF6CE94",
      "text": "MOV:G.W R4, @H'F6CE",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6CE",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63182,
          "name": null,
          "symbol": "ram_F6CE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6130,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6138,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6130,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6139,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6139,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6144,
      "address_region": "program_or_external",
      "bytes": "2222",
      "text": "BHI loc_1824",
      "mnemonic": "BHI",
      "operands": "loc_1824",
      "kind": "branch",
      "targets": [
        6180
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6139,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6146,
      "address_region": "program_or_external",
      "bytes": "1DE126FC",
      "text": "BTST.W #12, @H'E126",
      "mnemonic": "BTST.W",
      "operands": "#12, @H'E126",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57638,
          "name": null,
          "symbol": "mem_E126",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6146,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6150,
      "address_region": "program_or_external",
      "bytes": "271C",
      "text": "BEQ loc_1824",
      "mnemonic": "BEQ",
      "operands": "loc_1824",
      "kind": "branch",
      "targets": [
        6180
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6146,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6152,
      "address_region": "program_or_external",
      "bytes": "1DF6AC84",
      "text": "MOV:G.W @H'F6AC, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6AC, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63148,
          "name": null,
          "symbol": "ram_F6AC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6152,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6156,
      "address_region": "program_or_external",
      "bytes": "1DF6CC34",
      "text": "SUB.W @H'F6CC, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6CC, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63180,
          "name": null,
          "symbol": "ram_F6CC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6152,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6160,
      "address_region": "program_or_external",
      "bytes": "5B00A4",
      "text": "MOV:I.W #H'00A4, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00A4, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6152,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 164,
              "hex": "0x00A4",
              "width": 16,
              "source": "MOV:I.W #H'00A4, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00A4"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 164,
              "hex": "0x00A4",
              "width": 16,
              "source": "MOV:I.W #H'00A4, R3"
            }
          }
        }
      }
    },
    {
      "address": 6163,
      "address_region": "program_or_external",
      "bytes": "15F791F7",
      "text": "BTST.B #7, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6152,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 164,
              "hex": "0x00A4",
              "width": 16,
              "source": "MOV:I.W #H'00A4, R3"
            }
          }
        }
      }
    },
    {
      "address": 6167,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_1821",
      "mnemonic": "BEQ",
      "operands": "loc_1821",
      "kind": "branch",
      "targets": [
        6177
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6152,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 164,
              "hex": "0x00A4",
              "width": 16,
              "source": "MOV:I.W #H'00A4, R3"
            }
          }
        }
      }
    },
    {
      "address": 6169,
      "address_region": "program_or_external",
      "bytes": "15F404F3",
      "text": "BTST.B #3, @H'F404",
      "mnemonic": "BTST.B",
      "operands": "#3, @H'F404",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62468,
          "name": null,
          "symbol": "mem_F404",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6169,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6173,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_1821",
      "mnemonic": "BEQ",
      "operands": "loc_1821",
      "kind": "branch",
      "targets": [
        6177
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6169,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6175,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6175,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6177,
      "address_region": "program_or_external",
      "bytes": "1E017E",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6177,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6180,
      "address_region": "program_or_external",
      "bytes": "1DF6AC84",
      "text": "MOV:G.W @H'F6AC, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6AC, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63148,
          "name": null,
          "symbol": "ram_F6AC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6180,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6184,
      "address_region": "program_or_external",
      "bytes": "1DF6CC94",
      "text": "MOV:G.W R4, @H'F6CC",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6CC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63180,
          "name": null,
          "symbol": "ram_F6CC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6180,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6188,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6180,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6189,
      "address_region": "program_or_external",
      "bytes": "15F717F2",
      "text": "BTST.B #2, @H'F717",
      "mnemonic": "BTST.B",
      "operands": "#2, @H'F717",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63255,
          "name": null,
          "symbol": "ram_F717",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6189,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6193,
      "address_region": "program_or_external",
      "bytes": "2632",
      "text": "BNE loc_1865",
      "mnemonic": "BNE",
      "operands": "loc_1865",
      "kind": "branch",
      "targets": [
        6245
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6189,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6195,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6195,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6200,
      "address_region": "program_or_external",
      "bytes": "2222",
      "text": "BHI loc_185C",
      "mnemonic": "BHI",
      "operands": "loc_185C",
      "kind": "branch",
      "targets": [
        6236
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6195,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6202,
      "address_region": "program_or_external",
      "bytes": "1DE126F5",
      "text": "BTST.W #5, @H'E126",
      "mnemonic": "BTST.W",
      "operands": "#5, @H'E126",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57638,
          "name": null,
          "symbol": "mem_E126",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6202,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6206,
      "address_region": "program_or_external",
      "bytes": "271C",
      "text": "BEQ loc_185C",
      "mnemonic": "BEQ",
      "operands": "loc_185C",
      "kind": "branch",
      "targets": [
        6236
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6202,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6208,
      "address_region": "program_or_external",
      "bytes": "1DF6AA84",
      "text": "MOV:G.W @H'F6AA, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6AA, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63146,
          "name": null,
          "symbol": "ram_F6AA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6208,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6212,
      "address_region": "program_or_external",
      "bytes": "1DF6CA34",
      "text": "SUB.W @H'F6CA, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6CA, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63178,
          "name": null,
          "symbol": "ram_F6CA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6208,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6216,
      "address_region": "program_or_external",
      "bytes": "5B00A5",
      "text": "MOV:I.W #H'00A5, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00A5, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6208,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 165,
              "hex": "0x00A5",
              "width": 16,
              "source": "MOV:I.W #H'00A5, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00A5"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 165,
              "hex": "0x00A5",
              "width": 16,
              "source": "MOV:I.W #H'00A5, R3"
            }
          }
        }
      }
    },
    {
      "address": 6219,
      "address_region": "program_or_external",
      "bytes": "15F791F7",
      "text": "BTST.B #7, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6208,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 165,
              "hex": "0x00A5",
              "width": 16,
              "source": "MOV:I.W #H'00A5, R3"
            }
          }
        }
      }
    },
    {
      "address": 6223,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_1859",
      "mnemonic": "BEQ",
      "operands": "loc_1859",
      "kind": "branch",
      "targets": [
        6233
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6208,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 165,
              "hex": "0x00A5",
              "width": 16,
              "source": "MOV:I.W #H'00A5, R3"
            }
          }
        }
      }
    },
    {
      "address": 6225,
      "address_region": "program_or_external",
      "bytes": "15F404F2",
      "text": "BTST.B #2, @H'F404",
      "mnemonic": "BTST.B",
      "operands": "#2, @H'F404",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62468,
          "name": null,
          "symbol": "mem_F404",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6225,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6229,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_1859",
      "mnemonic": "BEQ",
      "operands": "loc_1859",
      "kind": "branch",
      "targets": [
        6233
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6225,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6231,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6231,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6233,
      "address_region": "program_or_external",
      "bytes": "1E0146",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6233,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6236,
      "address_region": "program_or_external",
      "bytes": "1DF6AA84",
      "text": "MOV:G.W @H'F6AA, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6AA, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63146,
          "name": null,
          "symbol": "ram_F6AA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6236,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6240,
      "address_region": "program_or_external",
      "bytes": "1DF6CA94",
      "text": "MOV:G.W R4, @H'F6CA",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6CA",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63178,
          "name": null,
          "symbol": "ram_F6CA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6236,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6244,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6236,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6245,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6245,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6250,
      "address_region": "program_or_external",
      "bytes": "221C",
      "text": "BHI loc_1888",
      "mnemonic": "BHI",
      "operands": "loc_1888",
      "kind": "branch",
      "targets": [
        6280
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6245,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6252,
      "address_region": "program_or_external",
      "bytes": "1DF6AA84",
      "text": "MOV:G.W @H'F6AA, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6AA, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63146,
          "name": null,
          "symbol": "ram_F6AA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6252,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6256,
      "address_region": "program_or_external",
      "bytes": "1DF6CA34",
      "text": "SUB.W @H'F6CA, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6CA, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63178,
          "name": null,
          "symbol": "ram_F6CA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6252,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6260,
      "address_region": "program_or_external",
      "bytes": "5B00D8",
      "text": "MOV:I.W #H'00D8, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00D8, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6252,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 216,
              "hex": "0x00D8",
              "width": 16,
              "source": "MOV:I.W #H'00D8, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00D8"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 216,
              "hex": "0x00D8",
              "width": 16,
              "source": "MOV:I.W #H'00D8, R3"
            }
          }
        }
      }
    },
    {
      "address": 6263,
      "address_region": "program_or_external",
      "bytes": "15F791F7",
      "text": "BTST.B #7, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6252,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 216,
              "hex": "0x00D8",
              "width": 16,
              "source": "MOV:I.W #H'00D8, R3"
            }
          }
        }
      }
    },
    {
      "address": 6267,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_1885",
      "mnemonic": "BEQ",
      "operands": "loc_1885",
      "kind": "branch",
      "targets": [
        6277
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6252,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 216,
              "hex": "0x00D8",
              "width": 16,
              "source": "MOV:I.W #H'00D8, R3"
            }
          }
        }
      }
    },
    {
      "address": 6269,
      "address_region": "program_or_external",
      "bytes": "15F404F1",
      "text": "BTST.B #1, @H'F404",
      "mnemonic": "BTST.B",
      "operands": "#1, @H'F404",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62468,
          "name": null,
          "symbol": "mem_F404",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6269,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6273,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_1885",
      "mnemonic": "BEQ",
      "operands": "loc_1885",
      "kind": "branch",
      "targets": [
        6277
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6269,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6275,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6275,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6277,
      "address_region": "program_or_external",
      "bytes": "1E011A",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6277,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6280,
      "address_region": "program_or_external",
      "bytes": "1DF6AA84",
      "text": "MOV:G.W @H'F6AA, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6AA, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63146,
          "name": null,
          "symbol": "ram_F6AA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6280,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6284,
      "address_region": "program_or_external",
      "bytes": "1DF6CA94",
      "text": "MOV:G.W R4, @H'F6CA",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6CA",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63178,
          "name": null,
          "symbol": "ram_F6CA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6280,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6288,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6280,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6289,
      "address_region": "program_or_external",
      "bytes": "15F717F2",
      "text": "BTST.B #2, @H'F717",
      "mnemonic": "BTST.B",
      "operands": "#2, @H'F717",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63255,
          "name": null,
          "symbol": "ram_F717",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6289,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6293,
      "address_region": "program_or_external",
      "bytes": "2624",
      "text": "BNE loc_18BB",
      "mnemonic": "BNE",
      "operands": "loc_18BB",
      "kind": "branch",
      "targets": [
        6331
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6289,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6295,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6295,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6300,
      "address_region": "program_or_external",
      "bytes": "2214",
      "text": "BHI loc_18B2",
      "mnemonic": "BHI",
      "operands": "loc_18B2",
      "kind": "branch",
      "targets": [
        6322
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6295,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6302,
      "address_region": "program_or_external",
      "bytes": "1DE126F5",
      "text": "BTST.W #5, @H'E126",
      "mnemonic": "BTST.W",
      "operands": "#5, @H'E126",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57638,
          "name": null,
          "symbol": "mem_E126",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6302,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6306,
      "address_region": "program_or_external",
      "bytes": "270E",
      "text": "BEQ loc_18B2",
      "mnemonic": "BEQ",
      "operands": "loc_18B2",
      "kind": "branch",
      "targets": [
        6322
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6302,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6308,
      "address_region": "program_or_external",
      "bytes": "1DF6A884",
      "text": "MOV:G.W @H'F6A8, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A8, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63144,
          "name": null,
          "symbol": "ram_F6A8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6308,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6312,
      "address_region": "program_or_external",
      "bytes": "1DF6C834",
      "text": "SUB.W @H'F6C8, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6C8, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63176,
          "name": null,
          "symbol": "ram_F6C8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6308,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6316,
      "address_region": "program_or_external",
      "bytes": "5B0080",
      "text": "MOV:I.W #H'0080, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0080, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6308,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x0080"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R3"
            }
          }
        }
      }
    },
    {
      "address": 6319,
      "address_region": "program_or_external",
      "bytes": "1E00F0",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6308,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R3"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6322,
      "address_region": "program_or_external",
      "bytes": "1DF6A884",
      "text": "MOV:G.W @H'F6A8, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A8, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63144,
          "name": null,
          "symbol": "ram_F6A8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6322,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6326,
      "address_region": "program_or_external",
      "bytes": "1DF6C894",
      "text": "MOV:G.W R4, @H'F6C8",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6C8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63176,
          "name": null,
          "symbol": "ram_F6C8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6322,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6330,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6322,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6331,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6331,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6336,
      "address_region": "program_or_external",
      "bytes": "221C",
      "text": "BHI loc_18DE",
      "mnemonic": "BHI",
      "operands": "loc_18DE",
      "kind": "branch",
      "targets": [
        6366
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6331,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6338,
      "address_region": "program_or_external",
      "bytes": "1DF6A884",
      "text": "MOV:G.W @H'F6A8, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A8, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63144,
          "name": null,
          "symbol": "ram_F6A8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6338,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6342,
      "address_region": "program_or_external",
      "bytes": "1DF6C834",
      "text": "SUB.W @H'F6C8, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6C8, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63176,
          "name": null,
          "symbol": "ram_F6C8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6338,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6346,
      "address_region": "program_or_external",
      "bytes": "5B00D9",
      "text": "MOV:I.W #H'00D9, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00D9, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6338,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 217,
              "hex": "0x00D9",
              "width": 16,
              "source": "MOV:I.W #H'00D9, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00D9"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 217,
              "hex": "0x00D9",
              "width": 16,
              "source": "MOV:I.W #H'00D9, R3"
            }
          }
        }
      }
    },
    {
      "address": 6349,
      "address_region": "program_or_external",
      "bytes": "15F791F7",
      "text": "BTST.B #7, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6338,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 217,
              "hex": "0x00D9",
              "width": 16,
              "source": "MOV:I.W #H'00D9, R3"
            }
          }
        }
      }
    },
    {
      "address": 6353,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_18DB",
      "mnemonic": "BEQ",
      "operands": "loc_18DB",
      "kind": "branch",
      "targets": [
        6363
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6338,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 217,
              "hex": "0x00D9",
              "width": 16,
              "source": "MOV:I.W #H'00D9, R3"
            }
          }
        }
      }
    },
    {
      "address": 6355,
      "address_region": "program_or_external",
      "bytes": "15F404F1",
      "text": "BTST.B #1, @H'F404",
      "mnemonic": "BTST.B",
      "operands": "#1, @H'F404",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62468,
          "name": null,
          "symbol": "mem_F404",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6355,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6359,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_18DB",
      "mnemonic": "BEQ",
      "operands": "loc_18DB",
      "kind": "branch",
      "targets": [
        6363
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6355,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6361,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6361,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6363,
      "address_region": "program_or_external",
      "bytes": "1E00C4",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6363,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6366,
      "address_region": "program_or_external",
      "bytes": "1DF6A884",
      "text": "MOV:G.W @H'F6A8, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A8, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63144,
          "name": null,
          "symbol": "ram_F6A8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6366,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6370,
      "address_region": "program_or_external",
      "bytes": "1DF6C894",
      "text": "MOV:G.W R4, @H'F6C8",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6C8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63176,
          "name": null,
          "symbol": "ram_F6C8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6366,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6374,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6366,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6375,
      "address_region": "program_or_external",
      "bytes": "15F717F2",
      "text": "BTST.B #2, @H'F717",
      "mnemonic": "BTST.B",
      "operands": "#2, @H'F717",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63255,
          "name": null,
          "symbol": "ram_F717",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6375,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6379,
      "address_region": "program_or_external",
      "bytes": "2632",
      "text": "BNE loc_191F",
      "mnemonic": "BNE",
      "operands": "loc_191F",
      "kind": "branch",
      "targets": [
        6431
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6375,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6381,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6381,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6386,
      "address_region": "program_or_external",
      "bytes": "2222",
      "text": "BHI loc_1916",
      "mnemonic": "BHI",
      "operands": "loc_1916",
      "kind": "branch",
      "targets": [
        6422
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6381,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6388,
      "address_region": "program_or_external",
      "bytes": "1DE126F5",
      "text": "BTST.W #5, @H'E126",
      "mnemonic": "BTST.W",
      "operands": "#5, @H'E126",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57638,
          "name": null,
          "symbol": "mem_E126",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6388,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6392,
      "address_region": "program_or_external",
      "bytes": "271C",
      "text": "BEQ loc_1916",
      "mnemonic": "BEQ",
      "operands": "loc_1916",
      "kind": "branch",
      "targets": [
        6422
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6388,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6394,
      "address_region": "program_or_external",
      "bytes": "1DF6A684",
      "text": "MOV:G.W @H'F6A6, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63142,
          "name": null,
          "symbol": "ram_F6A6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6394,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6398,
      "address_region": "program_or_external",
      "bytes": "1DF6C634",
      "text": "SUB.W @H'F6C6, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6C6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63174,
          "name": null,
          "symbol": "ram_F6C6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6394,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6402,
      "address_region": "program_or_external",
      "bytes": "5B00A6",
      "text": "MOV:I.W #H'00A6, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00A6, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6394,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 166,
              "hex": "0x00A6",
              "width": 16,
              "source": "MOV:I.W #H'00A6, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00A6"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 166,
              "hex": "0x00A6",
              "width": 16,
              "source": "MOV:I.W #H'00A6, R3"
            }
          }
        }
      }
    },
    {
      "address": 6405,
      "address_region": "program_or_external",
      "bytes": "15F791F7",
      "text": "BTST.B #7, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6394,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 166,
              "hex": "0x00A6",
              "width": 16,
              "source": "MOV:I.W #H'00A6, R3"
            }
          }
        }
      }
    },
    {
      "address": 6409,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_1913",
      "mnemonic": "BEQ",
      "operands": "loc_1913",
      "kind": "branch",
      "targets": [
        6419
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6394,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 166,
              "hex": "0x00A6",
              "width": 16,
              "source": "MOV:I.W #H'00A6, R3"
            }
          }
        }
      }
    },
    {
      "address": 6411,
      "address_region": "program_or_external",
      "bytes": "15F404F2",
      "text": "BTST.B #2, @H'F404",
      "mnemonic": "BTST.B",
      "operands": "#2, @H'F404",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62468,
          "name": null,
          "symbol": "mem_F404",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6411,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6415,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_1913",
      "mnemonic": "BEQ",
      "operands": "loc_1913",
      "kind": "branch",
      "targets": [
        6419
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6411,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6417,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6417,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6419,
      "address_region": "program_or_external",
      "bytes": "1E008C",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6419,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6422,
      "address_region": "program_or_external",
      "bytes": "1DF6A684",
      "text": "MOV:G.W @H'F6A6, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63142,
          "name": null,
          "symbol": "ram_F6A6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6422,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6426,
      "address_region": "program_or_external",
      "bytes": "1DF6C694",
      "text": "MOV:G.W R4, @H'F6C6",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6C6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63174,
          "name": null,
          "symbol": "ram_F6C6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6422,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6430,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6422,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6431,
      "address_region": "program_or_external",
      "bytes": "15F7310402",
      "text": "CMP:G.B #H'02, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6431,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6436,
      "address_region": "program_or_external",
      "bytes": "221B",
      "text": "BHI loc_1941",
      "mnemonic": "BHI",
      "operands": "loc_1941",
      "kind": "branch",
      "targets": [
        6465
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6431,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6438,
      "address_region": "program_or_external",
      "bytes": "1DF6A684",
      "text": "MOV:G.W @H'F6A6, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63142,
          "name": null,
          "symbol": "ram_F6A6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6438,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6442,
      "address_region": "program_or_external",
      "bytes": "1DF6C634",
      "text": "SUB.W @H'F6C6, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6C6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63174,
          "name": null,
          "symbol": "ram_F6C6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6438,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6446,
      "address_region": "program_or_external",
      "bytes": "5B00DA",
      "text": "MOV:I.W #H'00DA, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00DA, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6438,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 218,
              "hex": "0x00DA",
              "width": 16,
              "source": "MOV:I.W #H'00DA, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00DA"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 218,
              "hex": "0x00DA",
              "width": 16,
              "source": "MOV:I.W #H'00DA, R3"
            }
          }
        }
      }
    },
    {
      "address": 6449,
      "address_region": "program_or_external",
      "bytes": "15F791F7",
      "text": "BTST.B #7, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6438,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 218,
              "hex": "0x00DA",
              "width": 16,
              "source": "MOV:I.W #H'00DA, R3"
            }
          }
        }
      }
    },
    {
      "address": 6453,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_193F",
      "mnemonic": "BEQ",
      "operands": "loc_193F",
      "kind": "branch",
      "targets": [
        6463
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6438,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 218,
              "hex": "0x00DA",
              "width": 16,
              "source": "MOV:I.W #H'00DA, R3"
            }
          }
        }
      }
    },
    {
      "address": 6455,
      "address_region": "program_or_external",
      "bytes": "15F404F1",
      "text": "BTST.B #1, @H'F404",
      "mnemonic": "BTST.B",
      "operands": "#1, @H'F404",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62468,
          "name": null,
          "symbol": "mem_F404",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6455,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6459,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_193F",
      "mnemonic": "BEQ",
      "operands": "loc_193F",
      "kind": "branch",
      "targets": [
        6463
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6455,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6461,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6461,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6463,
      "address_region": "program_or_external",
      "bytes": "0E61",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6463,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6465,
      "address_region": "program_or_external",
      "bytes": "1DF6A684",
      "text": "MOV:G.W @H'F6A6, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63142,
          "name": null,
          "symbol": "ram_F6A6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6465,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6469,
      "address_region": "program_or_external",
      "bytes": "1DF6C694",
      "text": "MOV:G.W R4, @H'F6C6",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6C6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63174,
          "name": null,
          "symbol": "ram_F6C6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6465,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6473,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6465,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6474,
      "address_region": "program_or_external",
      "bytes": "15F7310403",
      "text": "CMP:G.B #H'03, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'03, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6474,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6479,
      "address_region": "program_or_external",
      "bytes": "221F",
      "text": "BHI loc_1970",
      "mnemonic": "BHI",
      "operands": "loc_1970",
      "kind": "branch",
      "targets": [
        6512
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6474,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6481,
      "address_region": "program_or_external",
      "bytes": "1DF6A484",
      "text": "MOV:G.W @H'F6A4, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A4, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63140,
          "name": null,
          "symbol": "ram_F6A4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6481,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6485,
      "address_region": "program_or_external",
      "bytes": "1DF6C434",
      "text": "SUB.W @H'F6C4, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6C4, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63172,
          "name": null,
          "symbol": "ram_F6C4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6481,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6489,
      "address_region": "program_or_external",
      "bytes": "15FE8EF4",
      "text": "BTST.B #4, @P7DR",
      "mnemonic": "BTST.B",
      "operands": "#4, @P7DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65166,
          "name": "P7DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6481,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6493,
      "address_region": "program_or_external",
      "bytes": "2600",
      "text": "BNE loc_195F",
      "mnemonic": "BNE",
      "operands": "loc_195F",
      "kind": "branch",
      "targets": [
        6495
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6481,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6495,
      "address_region": "program_or_external",
      "bytes": "5B0080",
      "text": "MOV:I.W #H'0080, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0080, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6495,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R3"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R3 = 0x0080"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R3"
            }
          }
        }
      }
    },
    {
      "address": 6498,
      "address_region": "program_or_external",
      "bytes": "15F791F5",
      "text": "BTST.B #5, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#5, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6495,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R3"
            }
          }
        }
      }
    },
    {
      "address": 6502,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_196A",
      "mnemonic": "BEQ",
      "operands": "loc_196A",
      "kind": "branch",
      "targets": [
        6506
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6495,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R3"
            }
          }
        }
      }
    },
    {
      "address": 6504,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6504,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6506,
      "address_region": "program_or_external",
      "bytes": "0E36",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6506,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6508,
      "address_region": "program_or_external",
      "bytes": "15F76DC7",
      "text": "BSET.B #7, @H'F76D",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'F76D",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63341,
          "name": null,
          "symbol": "ram_F76D",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6506,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6512,
      "address_region": "program_or_external",
      "bytes": "1DF6A484",
      "text": "MOV:G.W @H'F6A4, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A4, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63140,
          "name": null,
          "symbol": "ram_F6A4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6512,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6516,
      "address_region": "program_or_external",
      "bytes": "1DF6C494",
      "text": "MOV:G.W R4, @H'F6C4",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6C4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63172,
          "name": null,
          "symbol": "ram_F6C4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6512,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6520,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6512,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6521,
      "address_region": "program_or_external",
      "bytes": "15F7310403",
      "text": "CMP:G.B #H'03, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'03, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6521,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6526,
      "address_region": "program_or_external",
      "bytes": "2219",
      "text": "BHI loc_1999",
      "mnemonic": "BHI",
      "operands": "loc_1999",
      "kind": "branch",
      "targets": [
        6553
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6521,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6528,
      "address_region": "program_or_external",
      "bytes": "1DF6A280",
      "text": "MOV:G.W @H'F6A2, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63138,
          "name": null,
          "symbol": "ram_F6A2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6528,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 6532,
      "address_region": "program_or_external",
      "bytes": "1DF6C230",
      "text": "SUB.W @H'F6C2, R0",
      "mnemonic": "SUB.W",
      "operands": "@H'F6C2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63170,
          "name": null,
          "symbol": "ram_F6C2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6528,
        "changes": [],
        "notes": [
          "R0 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 6536,
      "address_region": "program_or_external",
      "bytes": "1DF68CA8",
      "text": "MULXU.W @H'F68C, R0",
      "mnemonic": "MULXU.W",
      "operands": "@H'F68C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 26,
        "base_cycles": 25,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63116,
          "name": null,
          "symbol": "ram_F68C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6528,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:MULXU.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6540,
      "address_region": "program_or_external",
      "bytes": "5B0081",
      "text": "MOV:I.W #H'0081, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0081, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6528,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 129,
              "hex": "0x0081",
              "width": 16,
              "source": "MOV:I.W #H'0081, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x0081"
        ],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 129,
              "hex": "0x0081",
              "width": 16,
              "source": "MOV:I.W #H'0081, R3"
            }
          }
        }
      }
    },
    {
      "address": 6543,
      "address_region": "program_or_external",
      "bytes": "15F791F5",
      "text": "BTST.B #5, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#5, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6528,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 129,
              "hex": "0x0081",
              "width": 16,
              "source": "MOV:I.W #H'0081, R3"
            }
          }
        }
      }
    },
    {
      "address": 6547,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_1997",
      "mnemonic": "BEQ",
      "operands": "loc_1997",
      "kind": "branch",
      "targets": [
        6551
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6528,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R3": {
              "known": true,
              "value": 129,
              "hex": "0x0081",
              "width": 16,
              "source": "MOV:I.W #H'0081, R3"
            }
          }
        }
      }
    },
    {
      "address": 6549,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6549,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6551,
      "address_region": "program_or_external",
      "bytes": "0E42",
      "text": "BSR loc_19DB",
      "mnemonic": "BSR",
      "operands": "loc_19DB",
      "kind": "call",
      "targets": [
        6619
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6551,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6553,
      "address_region": "program_or_external",
      "bytes": "1DF6A284",
      "text": "MOV:G.W @H'F6A2, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F6A2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63138,
          "name": null,
          "symbol": "ram_F6A2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6553,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6557,
      "address_region": "program_or_external",
      "bytes": "1DF6C294",
      "text": "MOV:G.W R4, @H'F6C2",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6C2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63170,
          "name": null,
          "symbol": "ram_F6C2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6553,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6561,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6553,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6562,
      "address_region": "program_or_external",
      "bytes": "AB85",
      "text": "MOV:G.W R3, R5",
      "mnemonic": "MOV:G.W",
      "operands": "R3, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6562,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 unknown after MOV source"
        ]
      }
    },
    {
      "address": 6564,
      "address_region": "program_or_external",
      "bytes": "0C01FF53",
      "text": "AND.W #H'01FF, R3",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6562,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6568,
      "address_region": "program_or_external",
      "bytes": "AB1A",
      "text": "SHLL.W R3",
      "mnemonic": "SHLL.W",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6562,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:AND.W"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6570,
      "address_region": "program_or_external",
      "bytes": "FBE40080",
      "text": "MOV:G.W @(-H'1C00,R3), R0",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'1C00,R3), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6562,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 6574,
      "address_region": "program_or_external",
      "bytes": "48FC00",
      "text": "CMP:I #H'FC00, R0",
      "mnemonic": "CMP:I",
      "operands": "#H'FC00, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6562,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6577,
      "address_region": "program_or_external",
      "bytes": "2203",
      "text": "BHI loc_19B6",
      "mnemonic": "BHI",
      "operands": "loc_19B6",
      "kind": "branch",
      "targets": [
        6582
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6562,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6579,
      "address_region": "program_or_external",
      "bytes": "58FE00",
      "text": "MOV:I.W #H'FE00, R0",
      "mnemonic": "MOV:I.W",
      "operands": "#H'FE00, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6579,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 65024,
              "hex": "0xFE00",
              "width": 16,
              "source": "MOV:I.W #H'FE00, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0xFE00"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 65024,
              "hex": "0xFE00",
              "width": 16,
              "source": "MOV:I.W #H'FE00, R0"
            }
          }
        }
      }
    },
    {
      "address": 6582,
      "address_region": "program_or_external",
      "bytes": "A815",
      "text": "NOT.W R0",
      "mnemonic": "NOT.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6582,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:NOT.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6584,
      "address_region": "program_or_external",
      "bytes": "A808",
      "text": "ADD:Q.W #1, R0",
      "mnemonic": "ADD:Q.W",
      "operands": "#1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6582,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:NOT.W"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6586,
      "address_region": "program_or_external",
      "bytes": "4C000F",
      "text": "CMP:I #H'000F, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'000F, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6582,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6589,
      "address_region": "program_or_external",
      "bytes": "2314",
      "text": "BLS loc_19D3",
      "mnemonic": "BLS",
      "operands": "loc_19D3",
      "kind": "branch",
      "targets": [
        6611
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6582,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6591,
      "address_region": "program_or_external",
      "bytes": "4CFFF0",
      "text": "CMP:I #H'FFF0, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'FFF0, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6591,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6594,
      "address_region": "program_or_external",
      "bytes": "240F",
      "text": "BCC loc_19D3",
      "mnemonic": "BCC",
      "operands": "loc_19D3",
      "kind": "branch",
      "targets": [
        6611
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6591,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6596,
      "address_region": "program_or_external",
      "bytes": "4C8000",
      "text": "CMP:I #H'8000, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'8000, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6596,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6599,
      "address_region": "program_or_external",
      "bytes": "2405",
      "text": "BCC loc_19CE",
      "mnemonic": "BCC",
      "operands": "loc_19CE",
      "kind": "branch",
      "targets": [
        6606
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6596,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6601,
      "address_region": "program_or_external",
      "bytes": "5C001A",
      "text": "MOV:I.W #H'001A, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'001A, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6601,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 26,
              "hex": "0x001A",
              "width": 16,
              "source": "MOV:I.W #H'001A, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x001A"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 26,
              "hex": "0x001A",
              "width": 16,
              "source": "MOV:I.W #H'001A, R4"
            }
          }
        }
      }
    },
    {
      "address": 6604,
      "address_region": "program_or_external",
      "bytes": "2009",
      "text": "BRA loc_19D7",
      "mnemonic": "BRA",
      "operands": "loc_19D7",
      "kind": "jump",
      "targets": [
        6615
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6601,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 26,
              "hex": "0x001A",
              "width": 16,
              "source": "MOV:I.W #H'001A, R4"
            }
          }
        }
      }
    },
    {
      "address": 6606,
      "address_region": "program_or_external",
      "bytes": "5CFF1C",
      "text": "MOV:I.W #H'FF1C, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'FF1C, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6606,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 65308,
              "hex": "0xFF1C",
              "width": 16,
              "source": "MOV:I.W #H'FF1C, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0xFF1C"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 65308,
              "hex": "0xFF1C",
              "width": 16,
              "source": "MOV:I.W #H'FF1C, R4"
            }
          }
        }
      }
    },
    {
      "address": 6609,
      "address_region": "program_or_external",
      "bytes": "2004",
      "text": "BRA loc_19D7",
      "mnemonic": "BRA",
      "operands": "loc_19D7",
      "kind": "jump",
      "targets": [
        6615
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6606,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 65308,
              "hex": "0xFF1C",
              "width": 16,
              "source": "MOV:I.W #H'FF1C, R4"
            }
          }
        }
      }
    },
    {
      "address": 6611,
      "address_region": "program_or_external",
      "bytes": "F41A2584",
      "text": "MOV:G.B @(H'1A25,R4), R4",
      "mnemonic": "MOV:G.B",
      "operands": "@(H'1A25,R4), R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6611,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6615,
      "address_region": "program_or_external",
      "bytes": "ACA8",
      "text": "MULXU.W R4, R0",
      "mnemonic": "MULXU.W",
      "operands": "R4, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 25,
        "base_cycles": 25,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6615,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:MULXU.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6617,
      "address_region": "program_or_external",
      "bytes": "2008",
      "text": "BRA loc_19E3",
      "mnemonic": "BRA",
      "operands": "loc_19E3",
      "kind": "jump",
      "targets": [
        6627
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6615,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6619,
      "address_region": "program_or_external",
      "bytes": "AB85",
      "text": "MOV:G.W R3, R5",
      "mnemonic": "MOV:G.W",
      "operands": "R3, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6619,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 unknown after MOV source"
        ]
      }
    },
    {
      "address": 6621,
      "address_region": "program_or_external",
      "bytes": "0C01FF53",
      "text": "AND.W #H'01FF, R3",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6619,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6625,
      "address_region": "program_or_external",
      "bytes": "AB1A",
      "text": "SHLL.W R3",
      "mnemonic": "SHLL.W",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6619,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:AND.W"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6627,
      "address_region": "program_or_external",
      "bytes": "FBE00080",
      "text": "MOV:G.W @(-H'2000,R3), R0",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'2000,R3), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6627,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 6631,
      "address_region": "program_or_external",
      "bytes": "A821",
      "text": "ADD:G.W R0, R1",
      "mnemonic": "ADD:G.W",
      "operands": "R0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6627,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R1 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6633,
      "address_region": "program_or_external",
      "bytes": "A982",
      "text": "MOV:G.W R1, R2",
      "mnemonic": "MOV:G.W",
      "operands": "R1, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6627,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R2 unknown after MOV source"
        ]
      }
    },
    {
      "address": 6635,
      "address_region": "program_or_external",
      "bytes": "250C",
      "text": "BCS loc_19F9",
      "mnemonic": "BCS",
      "operands": "loc_19F9",
      "kind": "branch",
      "targets": [
        6649
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6627,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6637,
      "address_region": "program_or_external",
      "bytes": "A832",
      "text": "SUB.W R0, R2",
      "mnemonic": "SUB.W",
      "operands": "R0, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6637,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R2 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6639,
      "address_region": "program_or_external",
      "bytes": "4A8000",
      "text": "CMP:I #H'8000, R2",
      "mnemonic": "CMP:I",
      "operands": "#H'8000, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6637,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6642,
      "address_region": "program_or_external",
      "bytes": "230F",
      "text": "BLS loc_1A03",
      "mnemonic": "BLS",
      "operands": "loc_1A03",
      "kind": "branch",
      "targets": [
        6659
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6637,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6644,
      "address_region": "program_or_external",
      "bytes": "590000",
      "text": "MOV:I.W #H'0000, R1",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0000, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6644,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R1"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 = 0x0000"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R1"
            }
          }
        }
      }
    },
    {
      "address": 6647,
      "address_region": "program_or_external",
      "bytes": "200A",
      "text": "BRA loc_1A03",
      "mnemonic": "BRA",
      "operands": "loc_1A03",
      "kind": "jump",
      "targets": [
        6659
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6644,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R1"
            }
          }
        }
      }
    },
    {
      "address": 6649,
      "address_region": "program_or_external",
      "bytes": "AA30",
      "text": "SUB.W R2, R0",
      "mnemonic": "SUB.W",
      "operands": "R2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6649,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6651,
      "address_region": "program_or_external",
      "bytes": "488000",
      "text": "CMP:I #H'8000, R0",
      "mnemonic": "CMP:I",
      "operands": "#H'8000, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6649,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6654,
      "address_region": "program_or_external",
      "bytes": "2303",
      "text": "BLS loc_1A03",
      "mnemonic": "BLS",
      "operands": "loc_1A03",
      "kind": "branch",
      "targets": [
        6659
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6649,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6656,
      "address_region": "program_or_external",
      "bytes": "59FFFF",
      "text": "MOV:I.W #H'FFFF, R1",
      "mnemonic": "MOV:I.W",
      "operands": "#H'FFFF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6656,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 65535,
              "hex": "0xFFFF",
              "width": 16,
              "source": "MOV:I.W #H'FFFF, R1"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 = 0xFFFF"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 65535,
              "hex": "0xFFFF",
              "width": 16,
              "source": "MOV:I.W #H'FFFF, R1"
            }
          }
        }
      }
    },
    {
      "address": 6659,
      "address_region": "program_or_external",
      "bytes": "FBE00071",
      "text": "CMP:G.W @(-H'2000,R3), R1",
      "mnemonic": "CMP:G.W",
      "operands": "@(-H'2000,R3), R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6659,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6663,
      "address_region": "program_or_external",
      "bytes": "270B",
      "text": "BEQ loc_1A14",
      "mnemonic": "BEQ",
      "operands": "loc_1A14",
      "kind": "branch",
      "targets": [
        6676
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6659,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6665,
      "address_region": "program_or_external",
      "bytes": "FBE80091",
      "text": "MOV:G.W R1, @(-H'1800,R3)",
      "mnemonic": "MOV:G.W",
      "operands": "R1, @(-H'1800,R3)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6665,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6669,
      "address_region": "program_or_external",
      "bytes": "5280",
      "text": "MOV:E.B #H'80, R2",
      "mnemonic": "MOV:E.B",
      "operands": "#H'80, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6665,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        ],
        "notes": [
          "R2 = 0x80"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        }
      }
    },
    {
      "address": 6671,
      "address_region": "program_or_external",
      "bytes": "AD83",
      "text": "MOV:G.W R5, R3",
      "mnemonic": "MOV:G.W",
      "operands": "R5, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6665,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R3 unknown after MOV source"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        }
      }
    },
    {
      "address": 6673,
      "address_region": "program_or_external",
      "bytes": "1E2440",
      "text": "BSR loc_3E54",
      "mnemonic": "BSR",
      "operands": "loc_3E54",
      "kind": "call",
      "targets": [
        15956
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6665,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6676,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6676,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6709,
      "address_region": "program_or_external",
      "bytes": "AB85",
      "text": "MOV:G.W R3, R5",
      "mnemonic": "MOV:G.W",
      "operands": "R3, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6709,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 unknown after MOV source"
        ]
      }
    },
    {
      "address": 6711,
      "address_region": "program_or_external",
      "bytes": "0C01FF53",
      "text": "AND.W #H'01FF, R3",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6709,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6715,
      "address_region": "program_or_external",
      "bytes": "AB1A",
      "text": "SHLL.W R3",
      "mnemonic": "SHLL.W",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6709,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:AND.W"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6717,
      "address_region": "program_or_external",
      "bytes": "FBE00080",
      "text": "MOV:G.W @(-H'2000,R3), R0",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'2000,R3), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6709,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 6721,
      "address_region": "program_or_external",
      "bytes": "273A",
      "text": "BEQ loc_1A7D",
      "mnemonic": "BEQ",
      "operands": "loc_1A7D",
      "kind": "branch",
      "targets": [
        6781
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6709,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6723,
      "address_region": "program_or_external",
      "bytes": "0E48",
      "text": "BSR loc_1A8D",
      "mnemonic": "BSR",
      "operands": "loc_1A8D",
      "kind": "call",
      "targets": [
        6797
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6723,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6725,
      "address_region": "program_or_external",
      "bytes": "AC16",
      "text": "TST.W R4",
      "mnemonic": "TST.W",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6725,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6727,
      "address_region": "program_or_external",
      "bytes": "2610",
      "text": "BNE loc_1A59",
      "mnemonic": "BNE",
      "operands": "loc_1A59",
      "kind": "branch",
      "targets": [
        6745
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6725,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6729,
      "address_region": "program_or_external",
      "bytes": "A882",
      "text": "MOV:G.W R0, R2",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6729,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R2 unknown after MOV source"
        ]
      }
    },
    {
      "address": 6731,
      "address_region": "program_or_external",
      "bytes": "FBE40081",
      "text": "MOV:G.W @(-H'1C00,R3), R1",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'1C00,R3), R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6731,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 6735,
      "address_region": "program_or_external",
      "bytes": "A81B",
      "text": "SHLR.W R0",
      "mnemonic": "SHLR.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6731,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLR.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6737,
      "address_region": "program_or_external",
      "bytes": "2716",
      "text": "BEQ loc_1A69",
      "mnemonic": "BEQ",
      "operands": "loc_1A69",
      "kind": "branch",
      "targets": [
        6761
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6731,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6739,
      "address_region": "program_or_external",
      "bytes": "A851",
      "text": "AND.W R0, R1",
      "mnemonic": "AND.W",
      "operands": "R0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6739,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 6741,
      "address_region": "program_or_external",
      "bytes": "27F4",
      "text": "BEQ loc_1A4B",
      "mnemonic": "BEQ",
      "operands": "loc_1A4B",
      "kind": "branch",
      "targets": [
        6731
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6739,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6743,
      "address_region": "program_or_external",
      "bytes": "2012",
      "text": "BRA loc_1A6B",
      "mnemonic": "BRA",
      "operands": "loc_1A6B",
      "kind": "jump",
      "targets": [
        6763
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6743,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6745,
      "address_region": "program_or_external",
      "bytes": "A882",
      "text": "MOV:G.W R0, R2",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6745,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R2 unknown after MOV source"
        ]
      }
    },
    {
      "address": 6747,
      "address_region": "program_or_external",
      "bytes": "FBE40081",
      "text": "MOV:G.W @(-H'1C00,R3), R1",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'1C00,R3), R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6747,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 6751,
      "address_region": "program_or_external",
      "bytes": "A81A",
      "text": "SHLL.W R0",
      "mnemonic": "SHLL.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6747,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6753,
      "address_region": "program_or_external",
      "bytes": "2706",
      "text": "BEQ loc_1A69",
      "mnemonic": "BEQ",
      "operands": "loc_1A69",
      "kind": "branch",
      "targets": [
        6761
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6747,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6755,
      "address_region": "program_or_external",
      "bytes": "A851",
      "text": "AND.W R0, R1",
      "mnemonic": "AND.W",
      "operands": "R0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6755,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 6757,
      "address_region": "program_or_external",
      "bytes": "27F4",
      "text": "BEQ loc_1A5B",
      "mnemonic": "BEQ",
      "operands": "loc_1A5B",
      "kind": "branch",
      "targets": [
        6747
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6755,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6759,
      "address_region": "program_or_external",
      "bytes": "2002",
      "text": "BRA loc_1A6B",
      "mnemonic": "BRA",
      "operands": "loc_1A6B",
      "kind": "jump",
      "targets": [
        6763
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6759,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6761,
      "address_region": "program_or_external",
      "bytes": "AA80",
      "text": "MOV:G.W R2, R0",
      "mnemonic": "MOV:G.W",
      "operands": "R2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6761,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 6763,
      "address_region": "program_or_external",
      "bytes": "FBE00070",
      "text": "CMP:G.W @(-H'2000,R3), R0",
      "mnemonic": "CMP:G.W",
      "operands": "@(-H'2000,R3), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6763,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6767,
      "address_region": "program_or_external",
      "bytes": "270B",
      "text": "BEQ loc_1A7C",
      "mnemonic": "BEQ",
      "operands": "loc_1A7C",
      "kind": "branch",
      "targets": [
        6780
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6763,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6769,
      "address_region": "program_or_external",
      "bytes": "FBE80090",
      "text": "MOV:G.W R0, @(-H'1800,R3)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'1800,R3)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6769,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6773,
      "address_region": "program_or_external",
      "bytes": "5280",
      "text": "MOV:E.B #H'80, R2",
      "mnemonic": "MOV:E.B",
      "operands": "#H'80, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6769,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        ],
        "notes": [
          "R2 = 0x80"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        }
      }
    },
    {
      "address": 6775,
      "address_region": "program_or_external",
      "bytes": "AD83",
      "text": "MOV:G.W R5, R3",
      "mnemonic": "MOV:G.W",
      "operands": "R5, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6769,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R3 unknown after MOV source"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        }
      }
    },
    {
      "address": 6777,
      "address_region": "program_or_external",
      "bytes": "1E23D8",
      "text": "BSR loc_3E54",
      "mnemonic": "BSR",
      "operands": "loc_3E54",
      "kind": "call",
      "targets": [
        15956
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6769,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6780,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6780,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6781,
      "address_region": "program_or_external",
      "bytes": "A8CF",
      "text": "BSET.W #15, R0",
      "mnemonic": "BSET.W",
      "operands": "#15, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6781,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6783,
      "address_region": "program_or_external",
      "bytes": "A881",
      "text": "MOV:G.W R0, R1",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6783,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after MOV source"
        ]
      }
    },
    {
      "address": 6785,
      "address_region": "program_or_external",
      "bytes": "FBE40051",
      "text": "AND.W @(-H'1C00,R3), R1",
      "mnemonic": "AND.W",
      "operands": "@(-H'1C00,R3), R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6783,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 6789,
      "address_region": "program_or_external",
      "bytes": "2604",
      "text": "BNE loc_1A8B",
      "mnemonic": "BNE",
      "operands": "loc_1A8B",
      "kind": "branch",
      "targets": [
        6795
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6783,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6791,
      "address_region": "program_or_external",
      "bytes": "A81B",
      "text": "SHLR.W R0",
      "mnemonic": "SHLR.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6791,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6793,
      "address_region": "program_or_external",
      "bytes": "20F4",
      "text": "BRA loc_1A7F",
      "mnemonic": "BRA",
      "operands": "loc_1A7F",
      "kind": "jump",
      "targets": [
        6783
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6791,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6795,
      "address_region": "program_or_external",
      "bytes": "20B8",
      "text": "BRA loc_1A45",
      "mnemonic": "BRA",
      "operands": "loc_1A45",
      "kind": "jump",
      "targets": [
        6725
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6795,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6797,
      "address_region": "program_or_external",
      "bytes": "59000F",
      "text": "MOV:I.W #H'000F, R1",
      "mnemonic": "MOV:I.W",
      "operands": "#H'000F, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6797,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 15,
              "hex": "0x000F",
              "width": 16,
              "source": "MOV:I.W #H'000F, R1"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 = 0x000F"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 15,
              "hex": "0x000F",
              "width": 16,
              "source": "MOV:I.W #H'000F, R1"
            }
          }
        }
      }
    },
    {
      "address": 6800,
      "address_region": "program_or_external",
      "bytes": "A879",
      "text": "BTST.W R1, R0",
      "mnemonic": "BTST.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6800,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6802,
      "address_region": "program_or_external",
      "bytes": "2603",
      "text": "BNE loc_1A97",
      "mnemonic": "BNE",
      "operands": "loc_1A97",
      "kind": "branch",
      "targets": [
        6807
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6800,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6804,
      "address_region": "program_or_external",
      "bytes": "01B9F9",
      "text": "SCB/F R1, loc_1A90",
      "mnemonic": "SCB/F",
      "operands": "R1, loc_1A90",
      "kind": "branch",
      "targets": [
        6800
      ],
      "cycles": {
        "false": 3,
        "count_minus_1": 4,
        "taken": 8,
        "base_taken": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6804,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6807,
      "address_region": "program_or_external",
      "bytes": "A813",
      "text": "CLR.W R0",
      "mnemonic": "CLR.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6807,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 cleared"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R0"
            }
          }
        }
      }
    },
    {
      "address": 6809,
      "address_region": "program_or_external",
      "bytes": "A849",
      "text": "BSET.W R1, R0",
      "mnemonic": "BSET.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6807,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R0"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6811,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6807,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6812,
      "address_region": "program_or_external",
      "bytes": "AB16",
      "text": "TST.W R3",
      "mnemonic": "TST.W",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6812,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6814,
      "address_region": "program_or_external",
      "bytes": "2732",
      "text": "BEQ loc_1AD2",
      "mnemonic": "BEQ",
      "operands": "loc_1AD2",
      "kind": "branch",
      "targets": [
        6866
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6812,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6816,
      "address_region": "program_or_external",
      "bytes": "AB1A",
      "text": "SHLL.W R3",
      "mnemonic": "SHLL.W",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6816,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 6818,
      "address_region": "program_or_external",
      "bytes": "15F73380",
      "text": "MOV:G.B @H'F733, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F733, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63283,
          "name": null,
          "symbol": "ram_F733",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6816,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 6822,
      "address_region": "program_or_external",
      "bytes": "A015",
      "text": "NOT.B R0",
      "mnemonic": "NOT.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6816,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:NOT.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6824,
      "address_region": "program_or_external",
      "bytes": "040F50",
      "text": "AND.B #H'0F, R0",
      "mnemonic": "AND.B",
      "operands": "#H'0F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6816,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:NOT.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6827,
      "address_region": "program_or_external",
      "bytes": "AC16",
      "text": "TST.W R4",
      "mnemonic": "TST.W",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6816,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6829,
      "address_region": "program_or_external",
      "bytes": "260D",
      "text": "BNE loc_1ABC",
      "mnemonic": "BNE",
      "operands": "loc_1ABC",
      "kind": "branch",
      "targets": [
        6844
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6816,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6831,
      "address_region": "program_or_external",
      "bytes": "A00C",
      "text": "ADD:Q.B #-1, R0",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6831,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6833,
      "address_region": "program_or_external",
      "bytes": "040F50",
      "text": "AND.B #H'0F, R0",
      "mnemonic": "AND.B",
      "operands": "#H'0F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6831,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6836,
      "address_region": "program_or_external",
      "bytes": "FBE40078",
      "text": "BTST.W R0, @(-H'1C00,R3)",
      "mnemonic": "BTST.W",
      "operands": "R0, @(-H'1C00,R3)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6831,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6840,
      "address_region": "program_or_external",
      "bytes": "27F5",
      "text": "BEQ loc_1AAF",
      "mnemonic": "BEQ",
      "operands": "loc_1AAF",
      "kind": "branch",
      "targets": [
        6831
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6831,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6842,
      "address_region": "program_or_external",
      "bytes": "200B",
      "text": "BRA loc_1AC7",
      "mnemonic": "BRA",
      "operands": "loc_1AC7",
      "kind": "jump",
      "targets": [
        6855
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6842,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6844,
      "address_region": "program_or_external",
      "bytes": "A008",
      "text": "ADD:Q.B #1, R0",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6844,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6846,
      "address_region": "program_or_external",
      "bytes": "040F50",
      "text": "AND.B #H'0F, R0",
      "mnemonic": "AND.B",
      "operands": "#H'0F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6844,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6849,
      "address_region": "program_or_external",
      "bytes": "FBE40078",
      "text": "BTST.W R0, @(-H'1C00,R3)",
      "mnemonic": "BTST.W",
      "operands": "R0, @(-H'1C00,R3)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6844,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6853,
      "address_region": "program_or_external",
      "bytes": "27F5",
      "text": "BEQ loc_1ABC",
      "mnemonic": "BEQ",
      "operands": "loc_1ABC",
      "kind": "branch",
      "targets": [
        6844
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6844,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6855,
      "address_region": "program_or_external",
      "bytes": "A015",
      "text": "NOT.B R0",
      "mnemonic": "NOT.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6855,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:NOT.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6857,
      "address_region": "program_or_external",
      "bytes": "040F50",
      "text": "AND.B #H'0F, R0",
      "mnemonic": "AND.B",
      "operands": "#H'0F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6855,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:NOT.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6860,
      "address_region": "program_or_external",
      "bytes": "15F73390",
      "text": "MOV:G.B R0, @H'F733",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F733",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63283,
          "name": null,
          "symbol": "ram_F733",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6855,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6864,
      "address_region": "program_or_external",
      "bytes": "200E",
      "text": "BRA loc_1AE0",
      "mnemonic": "BRA",
      "operands": "loc_1AE0",
      "kind": "jump",
      "targets": [
        6880
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6855,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6866,
      "address_region": "program_or_external",
      "bytes": "AC16",
      "text": "TST.W R4",
      "mnemonic": "TST.W",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6866,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6868,
      "address_region": "program_or_external",
      "bytes": "2606",
      "text": "BNE loc_1ADC",
      "mnemonic": "BNE",
      "operands": "loc_1ADC",
      "kind": "branch",
      "targets": [
        6876
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6866,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6870,
      "address_region": "program_or_external",
      "bytes": "15F73308",
      "text": "ADD:Q.B #1, @H'F733",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F733",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63283,
          "name": null,
          "symbol": "ram_F733",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6870,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6874,
      "address_region": "program_or_external",
      "bytes": "2004",
      "text": "BRA loc_1AE0",
      "mnemonic": "BRA",
      "operands": "loc_1AE0",
      "kind": "jump",
      "targets": [
        6880
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6870,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6876,
      "address_region": "program_or_external",
      "bytes": "15F7330C",
      "text": "ADD:Q.B #-1, @H'F733",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F733",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63283,
          "name": null,
          "symbol": "ram_F733",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6876,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6880,
      "address_region": "program_or_external",
      "bytes": "1E2E17",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6880,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6883,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6880,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6884,
      "address_region": "program_or_external",
      "bytes": "15F75B80",
      "text": "MOV:G.B @H'F75B, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F75B, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63323,
          "name": null,
          "symbol": "ram_F75B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6884,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 6888,
      "address_region": "program_or_external",
      "bytes": "A012",
      "text": "EXTU.B R0",
      "mnemonic": "EXTU.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6884,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 6890,
      "address_region": "program_or_external",
      "bytes": "F0F75D81",
      "text": "MOV:G.B @(-H'08A3,R0), R1",
      "mnemonic": "MOV:G.B",
      "operands": "@(-H'08A3,R0), R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6884,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 6894,
      "address_region": "program_or_external",
      "bytes": "AC16",
      "text": "TST.W R4",
      "mnemonic": "TST.W",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6884,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6896,
      "address_region": "program_or_external",
      "bytes": "260A",
      "text": "BNE loc_1AFC",
      "mnemonic": "BNE",
      "operands": "loc_1AFC",
      "kind": "branch",
      "targets": [
        6908
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6884,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6898,
      "address_region": "program_or_external",
      "bytes": "A108",
      "text": "ADD:Q.B #1, R1",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6898,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6900,
      "address_region": "program_or_external",
      "bytes": "412E",
      "text": "CMP:E #H'2E, R1",
      "mnemonic": "CMP:E",
      "operands": "#H'2E, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6898,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6902,
      "address_region": "program_or_external",
      "bytes": "230B",
      "text": "BLS loc_1B03",
      "mnemonic": "BLS",
      "operands": "loc_1B03",
      "kind": "branch",
      "targets": [
        6915
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6898,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6904,
      "address_region": "program_or_external",
      "bytes": "5100",
      "text": "MOV:E.B #H'00, R1",
      "mnemonic": "MOV:E.B",
      "operands": "#H'00, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6904,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x00",
              "width": 8,
              "source": "MOV:E.B #H'00, R1"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 = 0x00"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 0,
              "hex": "0x00",
              "width": 8,
              "source": "MOV:E.B #H'00, R1"
            }
          }
        }
      }
    },
    {
      "address": 6906,
      "address_region": "program_or_external",
      "bytes": "2007",
      "text": "BRA loc_1B03",
      "mnemonic": "BRA",
      "operands": "loc_1B03",
      "kind": "jump",
      "targets": [
        6915
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6904,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 0,
              "hex": "0x00",
              "width": 8,
              "source": "MOV:E.B #H'00, R1"
            }
          }
        }
      }
    },
    {
      "address": 6908,
      "address_region": "program_or_external",
      "bytes": "040131",
      "text": "SUB.B #H'01, R1",
      "mnemonic": "SUB.B",
      "operands": "#H'01, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6908,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6911,
      "address_region": "program_or_external",
      "bytes": "2402",
      "text": "BCC loc_1B03",
      "mnemonic": "BCC",
      "operands": "loc_1B03",
      "kind": "branch",
      "targets": [
        6915
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6908,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6913,
      "address_region": "program_or_external",
      "bytes": "512E",
      "text": "MOV:E.B #H'2E, R1",
      "mnemonic": "MOV:E.B",
      "operands": "#H'2E, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6913,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 46,
              "hex": "0x2E",
              "width": 8,
              "source": "MOV:E.B #H'2E, R1"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 = 0x2E"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 46,
              "hex": "0x2E",
              "width": 8,
              "source": "MOV:E.B #H'2E, R1"
            }
          }
        }
      }
    },
    {
      "address": 6915,
      "address_region": "program_or_external",
      "bytes": "F0F75D91",
      "text": "MOV:G.B R1, @(-H'08A3,R0)",
      "mnemonic": "MOV:G.B",
      "operands": "R1, @(-H'08A3,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6915,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6919,
      "address_region": "program_or_external",
      "bytes": "1E2DF0",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6915,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6922,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6915,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6923,
      "address_region": "program_or_external",
      "bytes": "15F75B80",
      "text": "MOV:G.B @H'F75B, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F75B, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63323,
          "name": null,
          "symbol": "ram_F75B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6923,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 6927,
      "address_region": "program_or_external",
      "bytes": "AC16",
      "text": "TST.W R4",
      "mnemonic": "TST.W",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6923,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6929,
      "address_region": "program_or_external",
      "bytes": "260A",
      "text": "BNE loc_1B1D",
      "mnemonic": "BNE",
      "operands": "loc_1B1D",
      "kind": "branch",
      "targets": [
        6941
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6923,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6931,
      "address_region": "program_or_external",
      "bytes": "A008",
      "text": "ADD:Q.B #1, R0",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6931,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6933,
      "address_region": "program_or_external",
      "bytes": "4008",
      "text": "CMP:E #H'08, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'08, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6931,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6935,
      "address_region": "program_or_external",
      "bytes": "230C",
      "text": "BLS loc_1B25",
      "mnemonic": "BLS",
      "operands": "loc_1B25",
      "kind": "branch",
      "targets": [
        6949
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6931,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6937,
      "address_region": "program_or_external",
      "bytes": "5008",
      "text": "MOV:E.B #H'08, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'08, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6937,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 8,
              "hex": "0x08",
              "width": 8,
              "source": "MOV:E.B #H'08, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x08"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 8,
              "hex": "0x08",
              "width": 8,
              "source": "MOV:E.B #H'08, R0"
            }
          }
        }
      }
    },
    {
      "address": 6939,
      "address_region": "program_or_external",
      "bytes": "2008",
      "text": "BRA loc_1B25",
      "mnemonic": "BRA",
      "operands": "loc_1B25",
      "kind": "jump",
      "targets": [
        6949
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6937,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 8,
              "hex": "0x08",
              "width": 8,
              "source": "MOV:E.B #H'08, R0"
            }
          }
        }
      }
    },
    {
      "address": 6941,
      "address_region": "program_or_external",
      "bytes": "A00C",
      "text": "ADD:Q.B #-1, R0",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6941,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 6943,
      "address_region": "program_or_external",
      "bytes": "4001",
      "text": "CMP:E #H'01, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'01, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6941,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6945,
      "address_region": "program_or_external",
      "bytes": "2402",
      "text": "BCC loc_1B25",
      "mnemonic": "BCC",
      "operands": "loc_1B25",
      "kind": "branch",
      "targets": [
        6949
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6941,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6947,
      "address_region": "program_or_external",
      "bytes": "5001",
      "text": "MOV:E.B #H'01, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'01, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6947,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 1,
              "hex": "0x01",
              "width": 8,
              "source": "MOV:E.B #H'01, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x01"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 1,
              "hex": "0x01",
              "width": 8,
              "source": "MOV:E.B #H'01, R0"
            }
          }
        }
      }
    },
    {
      "address": 6949,
      "address_region": "program_or_external",
      "bytes": "15F75B90",
      "text": "MOV:G.B R0, @H'F75B",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F75B",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63323,
          "name": null,
          "symbol": "ram_F75B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6949,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 6953,
      "address_region": "program_or_external",
      "bytes": "1E2DCE",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6949,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6956,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6949,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6957,
      "address_region": "program_or_external",
      "bytes": "15F6D784",
      "text": "MOV:G.B @H'F6D7, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D7, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63191,
          "name": null,
          "symbol": "ram_F6D7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6957,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6961,
      "address_region": "program_or_external",
      "bytes": "15F6E764",
      "text": "XOR.B @H'F6E7, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6E7, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63207,
          "name": null,
          "symbol": "ram_F6E7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6957,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 6965,
      "address_region": "program_or_external",
      "bytes": "5D007E",
      "text": "MOV:I.W #H'007E, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'007E, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6957,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 126,
              "hex": "0x007E",
              "width": 16,
              "source": "MOV:I.W #H'007E, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x007E"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 126,
              "hex": "0x007E",
              "width": 16,
              "source": "MOV:I.W #H'007E, R5"
            }
          }
        }
      }
    },
    {
      "address": 6968,
      "address_region": "program_or_external",
      "bytes": "1E00D3",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6957,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 126,
              "hex": "0x007E",
              "width": 16,
              "source": "MOV:I.W #H'007E, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6971,
      "address_region": "program_or_external",
      "bytes": "15F6D784",
      "text": "MOV:G.B @H'F6D7, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D7, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63191,
          "name": null,
          "symbol": "ram_F6D7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6957,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6975,
      "address_region": "program_or_external",
      "bytes": "15F6E794",
      "text": "MOV:G.B R4, @H'F6E7",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6E7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63207,
          "name": null,
          "symbol": "ram_F6E7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6957,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6979,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6957,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 6980,
      "address_region": "program_or_external",
      "bytes": "15F6D684",
      "text": "MOV:G.B @H'F6D6, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63190,
          "name": null,
          "symbol": "ram_F6D6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6980,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6984,
      "address_region": "program_or_external",
      "bytes": "15F6E664",
      "text": "XOR.B @H'F6E6, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6E6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63206,
          "name": null,
          "symbol": "ram_F6E6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6980,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 6988,
      "address_region": "program_or_external",
      "bytes": "5D006E",
      "text": "MOV:I.W #H'006E, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'006E, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6980,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 110,
              "hex": "0x006E",
              "width": 16,
              "source": "MOV:I.W #H'006E, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x006E"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 110,
              "hex": "0x006E",
              "width": 16,
              "source": "MOV:I.W #H'006E, R5"
            }
          }
        }
      }
    },
    {
      "address": 6991,
      "address_region": "program_or_external",
      "bytes": "1E00BC",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6980,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 110,
              "hex": "0x006E",
              "width": 16,
              "source": "MOV:I.W #H'006E, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 6994,
      "address_region": "program_or_external",
      "bytes": "15F6D684",
      "text": "MOV:G.B @H'F6D6, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D6, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63190,
          "name": null,
          "symbol": "ram_F6D6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6980,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 6998,
      "address_region": "program_or_external",
      "bytes": "15F6E694",
      "text": "MOV:G.B R4, @H'F6E6",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6E6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63206,
          "name": null,
          "symbol": "ram_F6E6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6980,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7002,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 6980,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7003,
      "address_region": "program_or_external",
      "bytes": "15F6D584",
      "text": "MOV:G.B @H'F6D5, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D5, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63189,
          "name": null,
          "symbol": "ram_F6D5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7003,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7007,
      "address_region": "program_or_external",
      "bytes": "15F6E564",
      "text": "XOR.B @H'F6E5, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6E5, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63205,
          "name": null,
          "symbol": "ram_F6E5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7003,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 7011,
      "address_region": "program_or_external",
      "bytes": "5D005E",
      "text": "MOV:I.W #H'005E, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'005E, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7003,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 94,
              "hex": "0x005E",
              "width": 16,
              "source": "MOV:I.W #H'005E, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x005E"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 94,
              "hex": "0x005E",
              "width": 16,
              "source": "MOV:I.W #H'005E, R5"
            }
          }
        }
      }
    },
    {
      "address": 7014,
      "address_region": "program_or_external",
      "bytes": "1E00A5",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7003,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 94,
              "hex": "0x005E",
              "width": 16,
              "source": "MOV:I.W #H'005E, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 7017,
      "address_region": "program_or_external",
      "bytes": "15F6D584",
      "text": "MOV:G.B @H'F6D5, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D5, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63189,
          "name": null,
          "symbol": "ram_F6D5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7003,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7021,
      "address_region": "program_or_external",
      "bytes": "15F6E594",
      "text": "MOV:G.B R4, @H'F6E5",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6E5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63205,
          "name": null,
          "symbol": "ram_F6E5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7003,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7025,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7003,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7026,
      "address_region": "program_or_external",
      "bytes": "15F6D184",
      "text": "MOV:G.B @H'F6D1, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D1, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63185,
          "name": null,
          "symbol": "ram_F6D1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7026,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7030,
      "address_region": "program_or_external",
      "bytes": "15F6E164",
      "text": "XOR.B @H'F6E1, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6E1, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63201,
          "name": null,
          "symbol": "ram_F6E1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7026,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 7034,
      "address_region": "program_or_external",
      "bytes": "5D001E",
      "text": "MOV:I.W #H'001E, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'001E, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7026,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 30,
              "hex": "0x001E",
              "width": 16,
              "source": "MOV:I.W #H'001E, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x001E"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 30,
              "hex": "0x001E",
              "width": 16,
              "source": "MOV:I.W #H'001E, R5"
            }
          }
        }
      }
    },
    {
      "address": 7037,
      "address_region": "program_or_external",
      "bytes": "1E008E",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7026,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 30,
              "hex": "0x001E",
              "width": 16,
              "source": "MOV:I.W #H'001E, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 7040,
      "address_region": "program_or_external",
      "bytes": "15F6D184",
      "text": "MOV:G.B @H'F6D1, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D1, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63185,
          "name": null,
          "symbol": "ram_F6D1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7026,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7044,
      "address_region": "program_or_external",
      "bytes": "15F6E194",
      "text": "MOV:G.B R4, @H'F6E1",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6E1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63201,
          "name": null,
          "symbol": "ram_F6E1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7026,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7048,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7026,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7049,
      "address_region": "program_or_external",
      "bytes": "15F6D084",
      "text": "MOV:G.B @H'F6D0, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D0, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63184,
          "name": null,
          "symbol": "ram_F6D0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7049,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7053,
      "address_region": "program_or_external",
      "bytes": "15F6E064",
      "text": "XOR.B @H'F6E0, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6E0, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63200,
          "name": null,
          "symbol": "ram_F6E0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7049,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 7057,
      "address_region": "program_or_external",
      "bytes": "5D000E",
      "text": "MOV:I.W #H'000E, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'000E, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7049,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 14,
              "hex": "0x000E",
              "width": 16,
              "source": "MOV:I.W #H'000E, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x000E"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 14,
              "hex": "0x000E",
              "width": 16,
              "source": "MOV:I.W #H'000E, R5"
            }
          }
        }
      }
    },
    {
      "address": 7060,
      "address_region": "program_or_external",
      "bytes": "1E0077",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7049,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 14,
              "hex": "0x000E",
              "width": 16,
              "source": "MOV:I.W #H'000E, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 7063,
      "address_region": "program_or_external",
      "bytes": "15F6D084",
      "text": "MOV:G.B @H'F6D0, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D0, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63184,
          "name": null,
          "symbol": "ram_F6D0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7049,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7067,
      "address_region": "program_or_external",
      "bytes": "15F6E094",
      "text": "MOV:G.B R4, @H'F6E0",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6E0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63200,
          "name": null,
          "symbol": "ram_F6E0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7049,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7071,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7049,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7072,
      "address_region": "program_or_external",
      "bytes": "15F6D484",
      "text": "MOV:G.B @H'F6D4, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D4, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63188,
          "name": null,
          "symbol": "ram_F6D4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7072,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7076,
      "address_region": "program_or_external",
      "bytes": "15F6E464",
      "text": "XOR.B @H'F6E4, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6E4, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63204,
          "name": null,
          "symbol": "ram_F6E4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7072,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 7080,
      "address_region": "program_or_external",
      "bytes": "5D004E",
      "text": "MOV:I.W #H'004E, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'004E, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7072,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 78,
              "hex": "0x004E",
              "width": 16,
              "source": "MOV:I.W #H'004E, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x004E"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 78,
              "hex": "0x004E",
              "width": 16,
              "source": "MOV:I.W #H'004E, R5"
            }
          }
        }
      }
    },
    {
      "address": 7083,
      "address_region": "program_or_external",
      "bytes": "0E61",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7072,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 78,
              "hex": "0x004E",
              "width": 16,
              "source": "MOV:I.W #H'004E, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 7085,
      "address_region": "program_or_external",
      "bytes": "15F6D484",
      "text": "MOV:G.B @H'F6D4, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D4, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63188,
          "name": null,
          "symbol": "ram_F6D4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7072,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7089,
      "address_region": "program_or_external",
      "bytes": "15F6E494",
      "text": "MOV:G.B R4, @H'F6E4",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6E4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63204,
          "name": null,
          "symbol": "ram_F6E4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7072,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7093,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7072,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7094,
      "address_region": "program_or_external",
      "bytes": "15F6D384",
      "text": "MOV:G.B @H'F6D3, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D3, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63187,
          "name": null,
          "symbol": "ram_F6D3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7094,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7098,
      "address_region": "program_or_external",
      "bytes": "15F6E364",
      "text": "XOR.B @H'F6E3, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6E3, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63203,
          "name": null,
          "symbol": "ram_F6E3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7094,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 7102,
      "address_region": "program_or_external",
      "bytes": "5D003E",
      "text": "MOV:I.W #H'003E, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'003E, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7094,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 62,
              "hex": "0x003E",
              "width": 16,
              "source": "MOV:I.W #H'003E, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x003E"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 62,
              "hex": "0x003E",
              "width": 16,
              "source": "MOV:I.W #H'003E, R5"
            }
          }
        }
      }
    },
    {
      "address": 7105,
      "address_region": "program_or_external",
      "bytes": "0E4B",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7094,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 62,
              "hex": "0x003E",
              "width": 16,
              "source": "MOV:I.W #H'003E, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 7107,
      "address_region": "program_or_external",
      "bytes": "15F6D384",
      "text": "MOV:G.B @H'F6D3, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D3, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63187,
          "name": null,
          "symbol": "ram_F6D3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7094,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7111,
      "address_region": "program_or_external",
      "bytes": "15F6E394",
      "text": "MOV:G.B R4, @H'F6E3",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6E3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63203,
          "name": null,
          "symbol": "ram_F6E3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7094,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7115,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7094,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7116,
      "address_region": "program_or_external",
      "bytes": "15F6D284",
      "text": "MOV:G.B @H'F6D2, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63186,
          "name": null,
          "symbol": "ram_F6D2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7116,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7120,
      "address_region": "program_or_external",
      "bytes": "15F6E264",
      "text": "XOR.B @H'F6E2, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6E2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63202,
          "name": null,
          "symbol": "ram_F6E2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7116,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 7124,
      "address_region": "program_or_external",
      "bytes": "5D002E",
      "text": "MOV:I.W #H'002E, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'002E, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7116,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 46,
              "hex": "0x002E",
              "width": 16,
              "source": "MOV:I.W #H'002E, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x002E"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 46,
              "hex": "0x002E",
              "width": 16,
              "source": "MOV:I.W #H'002E, R5"
            }
          }
        }
      }
    },
    {
      "address": 7127,
      "address_region": "program_or_external",
      "bytes": "0E35",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7116,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 46,
              "hex": "0x002E",
              "width": 16,
              "source": "MOV:I.W #H'002E, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 7129,
      "address_region": "program_or_external",
      "bytes": "15F6D284",
      "text": "MOV:G.B @H'F6D2, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6D2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63186,
          "name": null,
          "symbol": "ram_F6D2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7116,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7133,
      "address_region": "program_or_external",
      "bytes": "15F6E294",
      "text": "MOV:G.B R4, @H'F6E2",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6E2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63202,
          "name": null,
          "symbol": "ram_F6E2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7116,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7137,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7116,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7138,
      "address_region": "program_or_external",
      "bytes": "15F6DC84",
      "text": "MOV:G.B @H'F6DC, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6DC, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63196,
          "name": null,
          "symbol": "ram_F6DC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7138,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7142,
      "address_region": "program_or_external",
      "bytes": "15F6EC64",
      "text": "XOR.B @H'F6EC, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6EC, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63212,
          "name": null,
          "symbol": "ram_F6EC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7138,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 7146,
      "address_region": "program_or_external",
      "bytes": "5D00CE",
      "text": "MOV:I.W #H'00CE, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00CE, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7138,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 206,
              "hex": "0x00CE",
              "width": 16,
              "source": "MOV:I.W #H'00CE, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x00CE"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 206,
              "hex": "0x00CE",
              "width": 16,
              "source": "MOV:I.W #H'00CE, R5"
            }
          }
        }
      }
    },
    {
      "address": 7149,
      "address_region": "program_or_external",
      "bytes": "0E1F",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7138,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 206,
              "hex": "0x00CE",
              "width": 16,
              "source": "MOV:I.W #H'00CE, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 7151,
      "address_region": "program_or_external",
      "bytes": "15F6DC84",
      "text": "MOV:G.B @H'F6DC, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6DC, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63196,
          "name": null,
          "symbol": "ram_F6DC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7138,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7155,
      "address_region": "program_or_external",
      "bytes": "15F6EC94",
      "text": "MOV:G.B R4, @H'F6EC",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6EC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63212,
          "name": null,
          "symbol": "ram_F6EC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7138,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7159,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7138,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7160,
      "address_region": "program_or_external",
      "bytes": "15F6DB84",
      "text": "MOV:G.B @H'F6DB, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6DB, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63195,
          "name": null,
          "symbol": "ram_F6DB",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7160,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7164,
      "address_region": "program_or_external",
      "bytes": "15F6EB64",
      "text": "XOR.B @H'F6EB, R4",
      "mnemonic": "XOR.B",
      "operands": "@H'F6EB, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63211,
          "name": null,
          "symbol": "ram_F6EB",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7160,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 7168,
      "address_region": "program_or_external",
      "bytes": "5D00BE",
      "text": "MOV:I.W #H'00BE, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00BE, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7160,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 190,
              "hex": "0x00BE",
              "width": 16,
              "source": "MOV:I.W #H'00BE, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x00BE"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 190,
              "hex": "0x00BE",
              "width": 16,
              "source": "MOV:I.W #H'00BE, R5"
            }
          }
        }
      }
    },
    {
      "address": 7171,
      "address_region": "program_or_external",
      "bytes": "0E09",
      "text": "BSR loc_1C0E",
      "mnemonic": "BSR",
      "operands": "loc_1C0E",
      "kind": "call",
      "targets": [
        7182
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7160,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:XOR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 190,
              "hex": "0x00BE",
              "width": 16,
              "source": "MOV:I.W #H'00BE, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 7173,
      "address_region": "program_or_external",
      "bytes": "15F6DB84",
      "text": "MOV:G.B @H'F6DB, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6DB, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63195,
          "name": null,
          "symbol": "ram_F6DB",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7160,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 7177,
      "address_region": "program_or_external",
      "bytes": "15F6EB94",
      "text": "MOV:G.B R4, @H'F6EB",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6EB",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63211,
          "name": null,
          "symbol": "ram_F6EB",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7160,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7181,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7160,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7182,
      "address_region": "program_or_external",
      "bytes": "A41A",
      "text": "SHLL.B R4",
      "mnemonic": "SHLL.B",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7182,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 7184,
      "address_region": "program_or_external",
      "bytes": "240A",
      "text": "BCC loc_1C1C",
      "mnemonic": "BCC",
      "operands": "loc_1C1C",
      "kind": "branch",
      "targets": [
        7196
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7182,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7186,
      "address_region": "program_or_external",
      "bytes": "FD270680",
      "text": "MOV:G.W @(H'2706,R5), R0",
      "mnemonic": "MOV:G.W",
      "operands": "@(H'2706,R5), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7186,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 7190,
      "address_region": "program_or_external",
      "bytes": "1230",
      "text": "STM.W {R4,R5}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R4,R5}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "note": "6+3n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7186,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7192,
      "address_region": "program_or_external",
      "bytes": "11D8",
      "text": "JSR @R0",
      "mnemonic": "JSR",
      "operands": "@R0",
      "kind": "call",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "indirect_flow": {
        "address": 7192,
        "instruction": "JSR @R0",
        "kind": "call",
        "target_register": "R0",
        "confidence": "unknown",
        "summary": "JSR @R0 uses R0; target not resolved"
      },
      "dataflow": {
        "block": 7186,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 7194,
      "address_region": "program_or_external",
      "bytes": "0230",
      "text": "LDM.W @SP+, {R4,R5}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R4,R5}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "note": "6+4n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7186,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4, R5"
        ]
      }
    },
    {
      "address": 7196,
      "address_region": "program_or_external",
      "bytes": "A416",
      "text": "TST.B R4",
      "mnemonic": "TST.B",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7196,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 7198,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_1C24",
      "mnemonic": "BEQ",
      "operands": "loc_1C24",
      "kind": "branch",
      "targets": [
        7204
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7196,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7200,
      "address_region": "program_or_external",
      "bytes": "AD0D",
      "text": "ADD:Q.W #-2, R5",
      "mnemonic": "ADD:Q.W",
      "operands": "#-2, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7200,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 7202,
      "address_region": "program_or_external",
      "bytes": "20EA",
      "text": "BRA loc_1C0E",
      "mnemonic": "BRA",
      "operands": "loc_1C0E",
      "kind": "jump",
      "targets": [
        7182
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7200,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 7204,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 7204,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 8487,
      "address_region": "program_or_external",
      "bytes": "15FB03C7",
      "text": "BSET.B #7, @H'FB03",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'FB03",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
          "name": null,
          "symbol": "ram_FB03",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 8487,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 8491,
      "address_region": "program_or_external",
      "bytes": "2608",
      "text": "BNE loc_2135",
      "mnemonic": "BNE",
      "operands": "loc_2135",
      "kind": "branch",
      "targets": [
        8501
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 8487,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 8493,
      "address_region": "program_or_external",
      "bytes": "1DF73281",
      "text": "MOV:G.W @H'F732, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F732, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 8493,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 8497,
      "address_region": "program_or_external",
      "bytes": "1DF73491",
      "text": "MOV:G.W R1, @H'F734",
      "mnemonic": "MOV:G.W",
      "operands": "R1, @H'F734",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63284,
          "name": null,
          "symbol": "ram_F734",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 8493,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 8501,
      "address_region": "program_or_external",
      "bytes": "1DF732071C03",
      "text": "MOV:G.W #H'1C03, @H'F732",
      "mnemonic": "MOV:G.W",
      "operands": "#H'1C03, @H'F732",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 8501,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 8507,
      "address_region": "program_or_external",
      "bytes": "15FB020614",
      "text": "MOV:G.B #H'14, @H'FB02",
      "mnemonic": "MOV:G.B",
      "operands": "#H'14, @H'FB02",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64258,
          "name": null,
          "symbol": "ram_FB02",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 8501,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 8512,
      "address_region": "program_or_external",
      "bytes": "1E27B7",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 8501,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 8515,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 8501,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9808,
      "address_region": "program_or_external",
      "bytes": "15F6F6D5",
      "text": "BCLR.B #5, @H'F6F6",
      "mnemonic": "BCLR.B",
      "operands": "#5, @H'F6F6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63222,
          "name": null,
          "symbol": "ram_F6F6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9808,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 9812,
      "address_region": "program_or_external",
      "bytes": "370068",
      "text": "BEQ loc_26BF",
      "mnemonic": "BEQ",
      "operands": "loc_26BF",
      "kind": "branch",
      "targets": [
        9919
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9808,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9815,
      "address_region": "program_or_external",
      "bytes": "1DE12480",
      "text": "MOV:G.W @H'E124, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'E124, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57636,
          "name": null,
          "symbol": "mem_E124",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9815,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 9819,
      "address_region": "program_or_external",
      "bytes": "A81A",
      "text": "SHLL.W R0",
      "mnemonic": "SHLL.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9815,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 9821,
      "address_region": "program_or_external",
      "bytes": "A010",
      "text": "SWAP.B R0",
      "mnemonic": "SWAP.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9815,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 9823,
      "address_region": "program_or_external",
      "bytes": "15F6F6F6",
      "text": "BTST.B #6, @H'F6F6",
      "mnemonic": "BTST.B",
      "operands": "#6, @H'F6F6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63222,
          "name": null,
          "symbol": "ram_F6F6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9815,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9827,
      "address_region": "program_or_external",
      "bytes": "2608",
      "text": "BNE loc_266D",
      "mnemonic": "BNE",
      "operands": "loc_266D",
      "kind": "branch",
      "targets": [
        9837
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9815,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9829,
      "address_region": "program_or_external",
      "bytes": "A008",
      "text": "ADD:Q.B #1, R0",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9829,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 9831,
      "address_region": "program_or_external",
      "bytes": "241A",
      "text": "BCC loc_2683",
      "mnemonic": "BCC",
      "operands": "loc_2683",
      "kind": "branch",
      "targets": [
        9859
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9829,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9833,
      "address_region": "program_or_external",
      "bytes": "50FF",
      "text": "MOV:E.B #H'FF, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'FF, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9833,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 255,
              "hex": "0xFF",
              "width": 8,
              "source": "MOV:E.B #H'FF, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0xFF"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 255,
              "hex": "0xFF",
              "width": 8,
              "source": "MOV:E.B #H'FF, R0"
            }
          }
        }
      }
    },
    {
      "address": 9835,
      "address_region": "program_or_external",
      "bytes": "2016",
      "text": "BRA loc_2683",
      "mnemonic": "BRA",
      "operands": "loc_2683",
      "kind": "jump",
      "targets": [
        9859
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9833,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 255,
              "hex": "0xFF",
              "width": 8,
              "source": "MOV:E.B #H'FF, R0"
            }
          }
        }
      }
    },
    {
      "address": 9837,
      "address_region": "program_or_external",
      "bytes": "A00C",
      "text": "ADD:Q.B #-1, R0",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9837,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 9839,
      "address_region": "program_or_external",
      "bytes": "1DE004FD",
      "text": "BTST.W #13, @H'E004",
      "mnemonic": "BTST.W",
      "operands": "#13, @H'E004",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57348,
          "name": null,
          "symbol": "mem_E004",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9837,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9843,
      "address_region": "program_or_external",
      "bytes": "2608",
      "text": "BNE loc_267D",
      "mnemonic": "BNE",
      "operands": "loc_267D",
      "kind": "branch",
      "targets": [
        9853
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9837,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9845,
      "address_region": "program_or_external",
      "bytes": "4049",
      "text": "CMP:E #H'49, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'49, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9845,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 9847,
      "address_region": "program_or_external",
      "bytes": "240A",
      "text": "BCC loc_2683",
      "mnemonic": "BCC",
      "operands": "loc_2683",
      "kind": "branch",
      "targets": [
        9859
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9845,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9849,
      "address_region": "program_or_external",
      "bytes": "5049",
      "text": "MOV:E.B #H'49, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'49, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9849,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 73,
              "hex": "0x49",
              "width": 8,
              "source": "MOV:E.B #H'49, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x49"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 73,
              "hex": "0x49",
              "width": 8,
              "source": "MOV:E.B #H'49, R0"
            }
          }
        }
      }
    },
    {
      "address": 9851,
      "address_region": "program_or_external",
      "bytes": "2006",
      "text": "BRA loc_2683",
      "mnemonic": "BRA",
      "operands": "loc_2683",
      "kind": "jump",
      "targets": [
        9859
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9849,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 73,
              "hex": "0x49",
              "width": 8,
              "source": "MOV:E.B #H'49, R0"
            }
          }
        }
      }
    },
    {
      "address": 9853,
      "address_region": "program_or_external",
      "bytes": "4016",
      "text": "CMP:E #H'16, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'16, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9853,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 9855,
      "address_region": "program_or_external",
      "bytes": "2402",
      "text": "BCC loc_2683",
      "mnemonic": "BCC",
      "operands": "loc_2683",
      "kind": "branch",
      "targets": [
        9859
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9853,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9857,
      "address_region": "program_or_external",
      "bytes": "5016",
      "text": "MOV:E.B #H'16, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'16, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9857,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 22,
              "hex": "0x16",
              "width": 8,
              "source": "MOV:E.B #H'16, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x16"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 22,
              "hex": "0x16",
              "width": 8,
              "source": "MOV:E.B #H'16, R0"
            }
          }
        }
      }
    },
    {
      "address": 9859,
      "address_region": "program_or_external",
      "bytes": "A012",
      "text": "EXTU.B R0",
      "mnemonic": "EXTU.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9859,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 9861,
      "address_region": "program_or_external",
      "bytes": "A010",
      "text": "SWAP.B R0",
      "mnemonic": "SWAP.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9859,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 9863,
      "address_region": "program_or_external",
      "bytes": "A81B",
      "text": "SHLR.W R0",
      "mnemonic": "SHLR.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9859,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLR.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 9865,
      "address_region": "program_or_external",
      "bytes": "A8CF",
      "text": "BSET.W #15, R0",
      "mnemonic": "BSET.W",
      "operands": "#15, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9859,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SHLR.W"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 9867,
      "address_region": "program_or_external",
      "bytes": "1DE12470",
      "text": "CMP:G.W @H'E124, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'E124, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57636,
          "name": null,
          "symbol": "mem_E124",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9859,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9871,
      "address_region": "program_or_external",
      "bytes": "272E",
      "text": "BEQ loc_26BF",
      "mnemonic": "BEQ",
      "operands": "loc_26BF",
      "kind": "branch",
      "targets": [
        9919
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9859,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9873,
      "address_region": "program_or_external",
      "bytes": "1DE92490",
      "text": "MOV:G.W R0, @H'E924",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'E924",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 59684,
          "name": null,
          "symbol": "mem_E924",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9873,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 9877,
      "address_region": "program_or_external",
      "bytes": "5280",
      "text": "MOV:E.B #H'80, R2",
      "mnemonic": "MOV:E.B",
      "operands": "#H'80, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9873,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        ],
        "notes": [
          "R2 = 0x80"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        }
      }
    },
    {
      "address": 9879,
      "address_region": "program_or_external",
      "bytes": "5B0092",
      "text": "MOV:I.W #H'0092, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0092, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9873,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 146,
              "hex": "0x0092",
              "width": 16,
              "source": "MOV:I.W #H'0092, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x0092"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            },
            "R3": {
              "known": true,
              "value": 146,
              "hex": "0x0092",
              "width": 16,
              "source": "MOV:I.W #H'0092, R3"
            }
          }
        }
      }
    },
    {
      "address": 9882,
      "address_region": "program_or_external",
      "bytes": "15F791F7",
      "text": "BTST.B #7, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9873,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            },
            "R3": {
              "known": true,
              "value": 146,
              "hex": "0x0092",
              "width": 16,
              "source": "MOV:I.W #H'0092, R3"
            }
          }
        }
      }
    },
    {
      "address": 9886,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_26A8",
      "mnemonic": "BEQ",
      "operands": "loc_26A8",
      "kind": "branch",
      "targets": [
        9896
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9873,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            },
            "R3": {
              "known": true,
              "value": 146,
              "hex": "0x0092",
              "width": 16,
              "source": "MOV:I.W #H'0092, R3"
            }
          }
        }
      }
    },
    {
      "address": 9888,
      "address_region": "program_or_external",
      "bytes": "15F404F4",
      "text": "BTST.B #4, @H'F404",
      "mnemonic": "BTST.B",
      "operands": "#4, @H'F404",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62468,
          "name": null,
          "symbol": "mem_F404",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9888,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 9892,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_26A8",
      "mnemonic": "BEQ",
      "operands": "loc_26A8",
      "kind": "branch",
      "targets": [
        9896
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9888,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9894,
      "address_region": "program_or_external",
      "bytes": "ABCE",
      "text": "BSET.W #14, R3",
      "mnemonic": "BSET.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9894,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 9896,
      "address_region": "program_or_external",
      "bytes": "1E17A9",
      "text": "BSR loc_3E54",
      "mnemonic": "BSR",
      "operands": "loc_3E54",
      "kind": "call",
      "targets": [
        15956
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9896,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 9899,
      "address_region": "program_or_external",
      "bytes": "15F6F6C0",
      "text": "BSET.B #0, @H'F6F6",
      "mnemonic": "BSET.B",
      "operands": "#0, @H'F6F6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63222,
          "name": null,
          "symbol": "ram_F6F6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9896,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 9903,
      "address_region": "program_or_external",
      "bytes": "2608",
      "text": "BNE loc_26B9",
      "mnemonic": "BNE",
      "operands": "loc_26B9",
      "kind": "branch",
      "targets": [
        9913
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9896,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9905,
      "address_region": "program_or_external",
      "bytes": "1DF6F40707D0",
      "text": "MOV:G.W #H'07D0, @H'F6F4",
      "mnemonic": "MOV:G.W",
      "operands": "#H'07D0, @H'F6F4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63220,
          "name": null,
          "symbol": "ram_F6F4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9905,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 9911,
      "address_region": "program_or_external",
      "bytes": "2006",
      "text": "BRA loc_26BF",
      "mnemonic": "BRA",
      "operands": "loc_26BF",
      "kind": "jump",
      "targets": [
        9919
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9905,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 9913,
      "address_region": "program_or_external",
      "bytes": "1DF6F40700C8",
      "text": "MOV:G.W #H'00C8, @H'F6F4",
      "mnemonic": "MOV:G.W",
      "operands": "#H'00C8, @H'F6F4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63220,
          "name": null,
          "symbol": "ram_F6F4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9913,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 9919,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 9919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10246,
      "address_region": "program_or_external",
      "bytes": "15F9B981",
      "text": "MOV:G.B @H'F9B9, R1",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B9, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63929,
          "name": null,
          "symbol": "ram_F9B9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10246,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10250,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10246,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10252,
      "address_region": "program_or_external",
      "bytes": "15F9B471",
      "text": "CMP:G.B @H'F9B4, R1",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F9B4, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63924,
          "name": null,
          "symbol": "ram_F9B4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10246,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10256,
      "address_region": "program_or_external",
      "bytes": "2603",
      "text": "BNE loc_2815",
      "mnemonic": "BNE",
      "operands": "loc_2815",
      "kind": "branch",
      "targets": [
        10261
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10246,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10258,
      "address_region": "program_or_external",
      "bytes": "300491",
      "text": "BRA loc_2CA6",
      "mnemonic": "BRA",
      "operands": "loc_2CA6",
      "kind": "jump",
      "targets": [
        11430
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10258,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10261,
      "address_region": "program_or_external",
      "bytes": "A980",
      "text": "MOV:G.W R1, R0",
      "mnemonic": "MOV:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 10263,
      "address_region": "program_or_external",
      "bytes": "A81A",
      "text": "SHLL.W R0",
      "mnemonic": "SHLL.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 10265,
      "address_region": "program_or_external",
      "bytes": "F8F97080",
      "text": "MOV:G.W @(-H'0690,R0), R0",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'0690,R0), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 10269,
      "address_region": "program_or_external",
      "bytes": "A108",
      "text": "ADD:Q.B #1, R1",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R1 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 10271,
      "address_region": "program_or_external",
      "bytes": "041F51",
      "text": "AND.B #H'1F, R1",
      "mnemonic": "AND.B",
      "operands": "#H'1F, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10274,
      "address_region": "program_or_external",
      "bytes": "15F9B991",
      "text": "MOV:G.B R1, @H'F9B9",
      "mnemonic": "MOV:G.B",
      "operands": "R1, @H'F9B9",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63929,
          "name": null,
          "symbol": "ram_F9B9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10278,
      "address_region": "program_or_external",
      "bytes": "0C01FF50",
      "text": "AND.W #H'01FF, R0",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 10282,
      "address_region": "program_or_external",
      "bytes": "A885",
      "text": "MOV:G.W R0, R5",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R5 unknown after MOV source"
        ]
      }
    },
    {
      "address": 10284,
      "address_region": "program_or_external",
      "bytes": "1E39D7",
      "text": "BSR loc_6206",
      "mnemonic": "BSR",
      "operands": "loc_6206",
      "kind": "call",
      "targets": [
        25094
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 10287,
      "address_region": "program_or_external",
      "bytes": "A884",
      "text": "MOV:G.W R0, R4",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after MOV source"
        ]
      }
    },
    {
      "address": 10289,
      "address_region": "program_or_external",
      "bytes": "AC1A",
      "text": "SHLL.W R4",
      "mnemonic": "SHLL.W",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 10291,
      "address_region": "program_or_external",
      "bytes": "A816",
      "text": "TST.W R0",
      "mnemonic": "TST.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10293,
      "address_region": "program_or_external",
      "bytes": "2768",
      "text": "BEQ loc_289F",
      "mnemonic": "BEQ",
      "operands": "loc_289F",
      "kind": "branch",
      "targets": [
        10399
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10261,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10295,
      "address_region": "program_or_external",
      "bytes": "1DF73681",
      "text": "MOV:G.W @H'F736, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F736, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63286,
          "name": null,
          "symbol": "ram_F736",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10295,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10299,
      "address_region": "program_or_external",
      "bytes": "0C01FF51",
      "text": "AND.W #H'01FF, R1",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10295,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10303,
      "address_region": "program_or_external",
      "bytes": "A970",
      "text": "CMP:G.W R1, R0",
      "mnemonic": "CMP:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10295,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10305,
      "address_region": "program_or_external",
      "bytes": "370467",
      "text": "BEQ loc_2CAB",
      "mnemonic": "BEQ",
      "operands": "loc_2CAB",
      "kind": "branch",
      "targets": [
        11435
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10295,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10308,
      "address_region": "program_or_external",
      "bytes": "1DF73881",
      "text": "MOV:G.W @H'F738, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F738, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63288,
          "name": null,
          "symbol": "ram_F738",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10308,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10312,
      "address_region": "program_or_external",
      "bytes": "0C01FF51",
      "text": "AND.W #H'01FF, R1",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10308,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10316,
      "address_region": "program_or_external",
      "bytes": "A970",
      "text": "CMP:G.W R1, R0",
      "mnemonic": "CMP:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10308,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10318,
      "address_region": "program_or_external",
      "bytes": "37045A",
      "text": "BEQ loc_2CAB",
      "mnemonic": "BEQ",
      "operands": "loc_2CAB",
      "kind": "branch",
      "targets": [
        11435
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10308,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10321,
      "address_region": "program_or_external",
      "bytes": "1DF73A81",
      "text": "MOV:G.W @H'F73A, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F73A, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63290,
          "name": null,
          "symbol": "ram_F73A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10321,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10325,
      "address_region": "program_or_external",
      "bytes": "0C01FF51",
      "text": "AND.W #H'01FF, R1",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10321,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10329,
      "address_region": "program_or_external",
      "bytes": "A970",
      "text": "CMP:G.W R1, R0",
      "mnemonic": "CMP:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10321,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10331,
      "address_region": "program_or_external",
      "bytes": "37044D",
      "text": "BEQ loc_2CAB",
      "mnemonic": "BEQ",
      "operands": "loc_2CAB",
      "kind": "branch",
      "targets": [
        11435
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10321,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10334,
      "address_region": "program_or_external",
      "bytes": "1DF73C81",
      "text": "MOV:G.W @H'F73C, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F73C, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63292,
          "name": null,
          "symbol": "ram_F73C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10334,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10338,
      "address_region": "program_or_external",
      "bytes": "0C01FF51",
      "text": "AND.W #H'01FF, R1",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10334,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10342,
      "address_region": "program_or_external",
      "bytes": "A970",
      "text": "CMP:G.W R1, R0",
      "mnemonic": "CMP:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10334,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10344,
      "address_region": "program_or_external",
      "bytes": "370440",
      "text": "BEQ loc_2CAB",
      "mnemonic": "BEQ",
      "operands": "loc_2CAB",
      "kind": "branch",
      "targets": [
        11435
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10334,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10347,
      "address_region": "program_or_external",
      "bytes": "1DF73E81",
      "text": "MOV:G.W @H'F73E, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F73E, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63294,
          "name": null,
          "symbol": "ram_F73E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10347,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10351,
      "address_region": "program_or_external",
      "bytes": "0C01FF51",
      "text": "AND.W #H'01FF, R1",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10347,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10355,
      "address_region": "program_or_external",
      "bytes": "A970",
      "text": "CMP:G.W R1, R0",
      "mnemonic": "CMP:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10347,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10357,
      "address_region": "program_or_external",
      "bytes": "370433",
      "text": "BEQ loc_2CAB",
      "mnemonic": "BEQ",
      "operands": "loc_2CAB",
      "kind": "branch",
      "targets": [
        11435
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10347,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10360,
      "address_region": "program_or_external",
      "bytes": "1DF74081",
      "text": "MOV:G.W @H'F740, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F740, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63296,
          "name": null,
          "symbol": "ram_F740",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10360,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10364,
      "address_region": "program_or_external",
      "bytes": "0C01FF51",
      "text": "AND.W #H'01FF, R1",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10360,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10368,
      "address_region": "program_or_external",
      "bytes": "A970",
      "text": "CMP:G.W R1, R0",
      "mnemonic": "CMP:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10360,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10370,
      "address_region": "program_or_external",
      "bytes": "370426",
      "text": "BEQ loc_2CAB",
      "mnemonic": "BEQ",
      "operands": "loc_2CAB",
      "kind": "branch",
      "targets": [
        11435
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10360,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10373,
      "address_region": "program_or_external",
      "bytes": "1DF74281",
      "text": "MOV:G.W @H'F742, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F742, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63298,
          "name": null,
          "symbol": "ram_F742",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10373,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10377,
      "address_region": "program_or_external",
      "bytes": "0C01FF51",
      "text": "AND.W #H'01FF, R1",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10373,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10381,
      "address_region": "program_or_external",
      "bytes": "A970",
      "text": "CMP:G.W R1, R0",
      "mnemonic": "CMP:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10373,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10383,
      "address_region": "program_or_external",
      "bytes": "370419",
      "text": "BEQ loc_2CAB",
      "mnemonic": "BEQ",
      "operands": "loc_2CAB",
      "kind": "branch",
      "targets": [
        11435
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10373,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10386,
      "address_region": "program_or_external",
      "bytes": "1DF75481",
      "text": "MOV:G.W @H'F754, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F754, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63316,
          "name": null,
          "symbol": "ram_F754",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10386,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10390,
      "address_region": "program_or_external",
      "bytes": "0C01FF51",
      "text": "AND.W #H'01FF, R1",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10386,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 10394,
      "address_region": "program_or_external",
      "bytes": "A970",
      "text": "CMP:G.W R1, R0",
      "mnemonic": "CMP:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10386,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10396,
      "address_region": "program_or_external",
      "bytes": "37040C",
      "text": "BEQ loc_2CAB",
      "mnemonic": "BEQ",
      "operands": "loc_2CAB",
      "kind": "branch",
      "targets": [
        11435
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10386,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 10399,
      "address_region": "program_or_external",
      "bytes": "FC28A681",
      "text": "MOV:G.W @(H'28A6,R4), R1",
      "mnemonic": "MOV:G.W",
      "operands": "@(H'28A6,R4), R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 10399,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 10403,
      "address_region": "program_or_external",
      "bytes": "11D1",
      "text": "JMP @R1",
      "mnemonic": "JMP",
      "operands": "@R1",
      "kind": "jump",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "indirect_flow": {
        "address": 10403,
        "instruction": "JMP @R1",
        "kind": "jump",
        "target_register": "R1",
        "confidence": "table_load",
        "table": {
          "base": 10406,
          "index_register": "R4",
          "target_register": "R1",
          "load_address": 10399,
          "load_instruction": "MOV:G.W @(H'28A6,R4), R1",
          "entry_size": 2,
          "entry_count": 128,
          "decoded_target_count": 103,
          "entries": [
            {
              "index": 0,
              "entry_address": 10406,
              "target": 11449,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 1,
              "entry_address": 10408,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 2,
              "entry_address": 10410,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 3,
              "entry_address": 10412,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 4,
              "entry_address": 10414,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 5,
              "entry_address": 10416,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 6,
              "entry_address": 10418,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 7,
              "entry_address": 10420,
              "target": 11715,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 8,
              "entry_address": 10422,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 9,
              "entry_address": 10424,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 10,
              "entry_address": 10426,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 11,
              "entry_address": 10428,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 12,
              "entry_address": 10430,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 13,
              "entry_address": 10432,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 14,
              "entry_address": 10434,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 15,
              "entry_address": 10436,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 16,
              "entry_address": 10438,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 17,
              "entry_address": 10440,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 18,
              "entry_address": 10442,
              "target": 11779,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 19,
              "entry_address": 10444,
              "target": 11782,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 20,
              "entry_address": 10446,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 21,
              "entry_address": 10448,
              "target": 11833,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 22,
              "entry_address": 10450,
              "target": 11866,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 23,
              "entry_address": 10452,
              "target": 11909,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 24,
              "entry_address": 10454,
              "target": 11887,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 25,
              "entry_address": 10456,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 26,
              "entry_address": 10458,
              "target": 11972,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 27,
              "entry_address": 10460,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 28,
              "entry_address": 10462,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 29,
              "entry_address": 10464,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 30,
              "entry_address": 10466,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 31,
              "entry_address": 10468,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 32,
              "entry_address": 10470,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 33,
              "entry_address": 10472,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 34,
              "entry_address": 10474,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 35,
              "entry_address": 10476,
              "target": 12006,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 36,
              "entry_address": 10478,
              "target": 12044,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 37,
              "entry_address": 10480,
              "target": 12060,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 38,
              "entry_address": 10482,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 39,
              "entry_address": 10484,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 40,
              "entry_address": 10486,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 41,
              "entry_address": 10488,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 42,
              "entry_address": 10490,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 43,
              "entry_address": 10492,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 44,
              "entry_address": 10494,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 45,
              "entry_address": 10496,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 46,
              "entry_address": 10498,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 47,
              "entry_address": 10500,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 48,
              "entry_address": 10502,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 49,
              "entry_address": 10504,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 50,
              "entry_address": 10506,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 51,
              "entry_address": 10508,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 52,
              "entry_address": 10510,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 53,
              "entry_address": 10512,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 54,
              "entry_address": 10514,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 55,
              "entry_address": 10516,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 56,
              "entry_address": 10518,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 57,
              "entry_address": 10520,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 58,
              "entry_address": 10522,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 59,
              "entry_address": 10524,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 60,
              "entry_address": 10526,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 61,
              "entry_address": 10528,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 62,
              "entry_address": 10530,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 63,
              "entry_address": 10532,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 64,
              "entry_address": 10534,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 65,
              "entry_address": 10536,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 66,
              "entry_address": 10538,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 67,
              "entry_address": 10540,
              "target": 12106,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 68,
              "entry_address": 10542,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 69,
              "entry_address": 10544,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 70,
              "entry_address": 10546,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 71,
              "entry_address": 10548,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 72,
              "entry_address": 10550,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 73,
              "entry_address": 10552,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 74,
              "entry_address": 10554,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 75,
              "entry_address": 10556,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 76,
              "entry_address": 10558,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 77,
              "entry_address": 10560,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 78,
              "entry_address": 10562,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 79,
              "entry_address": 10564,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 80,
              "entry_address": 10566,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 81,
              "entry_address": 10568,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 82,
              "entry_address": 10570,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 83,
              "entry_address": 10572,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 84,
              "entry_address": 10574,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 85,
              "entry_address": 10576,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 86,
              "entry_address": 10578,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 87,
              "entry_address": 10580,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 88,
              "entry_address": 10582,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 89,
              "entry_address": 10584,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 90,
              "entry_address": 10586,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 91,
              "entry_address": 10588,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 92,
              "entry_address": 10590,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 93,
              "entry_address": 10592,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 94,
              "entry_address": 10594,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 95,
              "entry_address": 10596,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 96,
              "entry_address": 10598,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 97,
              "entry_address": 10600,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 98,
              "entry_address": 10602,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 99,
              "entry_address": 10604,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 100,
              "entry_address": 10606,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 101,
              "entry_address": 10608,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 102,
              "entry_address": 10610,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 103,
              "entry_address": 10612,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 104,
              "entry_address": 10614,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 105,
              "entry_address": 10616,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 106,
              "entry_address": 10618,
              "target": 12124,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 107,
              "entry_address": 10620,
              "target": 12146,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 108,
              "entry_address": 10622,
              "target": 12207,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 109,
              "entry_address": 10624,
              "target": 12309,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 110,
              "entry_address": 10626,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 111,
              "entry_address": 10628,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 112,
              "entry_address": 10630,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 113,
              "entry_address": 10632,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 114,
              "entry_address": 10634,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 115,
              "entry_address": 10636,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 116,
              "entry_address": 10638,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 117,
              "entry_address": 10640,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 118,
              "entry_address": 10642,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 119,
              "entry_address": 10644,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 120,
              "entry_address": 10646,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 121,
              "entry_address": 10648,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 122,
              "entry_address": 10650,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 123,
              "entry_address": 10652,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 124,
              "entry_address": 10654,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 125,
              "entry_address": 10656,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 126,
              "entry_address": 10658,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            },
            {
              "index": 127,
              "entry_address": 10660,
              "target": 11430,
              "target_label": "loc_2CA6",
              "target_region": "program_or_external",
              "decoded_code": true
            }
          ]
        },
        "summary": "JMP @R1 uses R1 loaded from pointer table H'28A6 via R4 (103/128 decoded targets)"
      },
      "dataflow": {
        "block": 10399,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "indirect_jump"
            }
          }
        ],
        "notes": [
          "indirect jump ends known register state"
        ]
      }
    },
    {
      "address": 11430,
      "address_region": "program_or_external",
      "bytes": "15F769D7",
      "text": "BCLR.B #7, @H'F769",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F769",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63337,
          "name": null,
          "symbol": "ram_F769",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 11430,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 11434,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 11430,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 11435,
      "address_region": "program_or_external",
      "bytes": "1231",
      "text": "STM.W {R0,R4,R5}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R4,R5}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 15,
        "note": "6+3n, n=3",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 11435,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 11437,
      "address_region": "program_or_external",
      "bytes": "1E1C4A",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 11435,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 11440,
      "address_region": "program_or_external",
      "bytes": "0231",
      "text": "LDM.W @SP+, {R0,R4,R5}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R4,R5}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 18,
        "note": "6+4n, n=3",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 11435,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0, R4, R5"
        ]
      }
    },
    {
      "address": 11442,
      "address_region": "program_or_external",
      "bytes": "15F769C7",
      "text": "BSET.B #7, @H'F769",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'F769",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63337,
          "name": null,
          "symbol": "ram_F769",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 11435,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 11446,
      "address_region": "program_or_external",
      "bytes": "30FBE6",
      "text": "BRA loc_289F",
      "mnemonic": "BRA",
      "operands": "loc_289F",
      "kind": "jump",
      "targets": [
        10399
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 11435,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14640,
      "address_region": "program_or_external",
      "bytes": "580007",
      "text": "MOV:I.W #H'0007, R0",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0007, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14640,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 7,
              "hex": "0x0007",
              "width": 16,
              "source": "MOV:I.W #H'0007, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x0007"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 7,
              "hex": "0x0007",
              "width": 16,
              "source": "MOV:I.W #H'0007, R0"
            }
          }
        }
      }
    },
    {
      "address": 14643,
      "address_region": "program_or_external",
      "bytes": "15FE8E78",
      "text": "BTST.B R0, @P7DR",
      "mnemonic": "BTST.B",
      "operands": "R0, @P7DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65166,
          "name": "P7DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14643,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14647,
      "address_region": "program_or_external",
      "bytes": "270A",
      "text": "BEQ loc_3943",
      "mnemonic": "BEQ",
      "operands": "loc_3943",
      "kind": "branch",
      "targets": [
        14659
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14643,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14649,
      "address_region": "program_or_external",
      "bytes": "F0F6801A",
      "text": "SHLL.B @(-H'0980,R0)",
      "mnemonic": "SHLL.B",
      "operands": "@(-H'0980,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14649,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14653,
      "address_region": "program_or_external",
      "bytes": "F0F680C0",
      "text": "BSET.B #0, @(-H'0980,R0)",
      "mnemonic": "BSET.B",
      "operands": "#0, @(-H'0980,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14649,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14657,
      "address_region": "program_or_external",
      "bytes": "2004",
      "text": "BRA loc_3947",
      "mnemonic": "BRA",
      "operands": "loc_3947",
      "kind": "jump",
      "targets": [
        14663
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14649,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14659,
      "address_region": "program_or_external",
      "bytes": "F0F6801A",
      "text": "SHLL.B @(-H'0980,R0)",
      "mnemonic": "SHLL.B",
      "operands": "@(-H'0980,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14659,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14663,
      "address_region": "program_or_external",
      "bytes": "F0F68004FF",
      "text": "CMP:G.B #H'FF, @(-H'0980,R0)",
      "mnemonic": "CMP:G.B",
      "operands": "#H'FF, @(-H'0980,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14663,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14668,
      "address_region": "program_or_external",
      "bytes": "2606",
      "text": "BNE loc_3954",
      "mnemonic": "BNE",
      "operands": "loc_3954",
      "kind": "branch",
      "targets": [
        14676
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14663,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14670,
      "address_region": "program_or_external",
      "bytes": "15F68848",
      "text": "BSET.B R0, @H'F688",
      "mnemonic": "BSET.B",
      "operands": "R0, @H'F688",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63112,
          "name": null,
          "symbol": "ram_F688",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14670,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14674,
      "address_region": "program_or_external",
      "bytes": "200B",
      "text": "BRA loc_395F",
      "mnemonic": "BRA",
      "operands": "loc_395F",
      "kind": "jump",
      "targets": [
        14687
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14670,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14676,
      "address_region": "program_or_external",
      "bytes": "F0F6800400",
      "text": "CMP:G.B #H'00, @(-H'0980,R0)",
      "mnemonic": "CMP:G.B",
      "operands": "#H'00, @(-H'0980,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14676,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14681,
      "address_region": "program_or_external",
      "bytes": "2604",
      "text": "BNE loc_395F",
      "mnemonic": "BNE",
      "operands": "loc_395F",
      "kind": "branch",
      "targets": [
        14687
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14676,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14683,
      "address_region": "program_or_external",
      "bytes": "15F68858",
      "text": "BCLR.B R0, @H'F688",
      "mnemonic": "BCLR.B",
      "operands": "R0, @H'F688",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63112,
          "name": null,
          "symbol": "ram_F688",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14683,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14687,
      "address_region": "program_or_external",
      "bytes": "01B8D1",
      "text": "SCB/F R0, loc_3933",
      "mnemonic": "SCB/F",
      "operands": "R0, loc_3933",
      "kind": "branch",
      "targets": [
        14643
      ],
      "cycles": {
        "false": 3,
        "count_minus_1": 4,
        "taken": 9,
        "base_taken": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14687,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14690,
      "address_region": "program_or_external",
      "bytes": "15F72208",
      "text": "ADD:Q.B #1, @H'F722",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F722",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63266,
          "name": null,
          "symbol": "ram_F722",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14690,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14694,
      "address_region": "program_or_external",
      "bytes": "15F722043C",
      "text": "CMP:G.B #H'3C, @H'F722",
      "mnemonic": "CMP:G.B",
      "operands": "#H'3C, @H'F722",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63266,
          "name": null,
          "symbol": "ram_F722",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14690,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14699,
      "address_region": "program_or_external",
      "bytes": "270F",
      "text": "BEQ loc_397C",
      "mnemonic": "BEQ",
      "operands": "loc_397C",
      "kind": "branch",
      "targets": [
        14716
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14690,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14701,
      "address_region": "program_or_external",
      "bytes": "15F7220478",
      "text": "CMP:G.B #H'78, @H'F722",
      "mnemonic": "CMP:G.B",
      "operands": "#H'78, @H'F722",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63266,
          "name": null,
          "symbol": "ram_F722",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14701,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14706,
      "address_region": "program_or_external",
      "bytes": "270B",
      "text": "BEQ loc_397F",
      "mnemonic": "BEQ",
      "operands": "loc_397F",
      "kind": "branch",
      "targets": [
        14719
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14701,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14708,
      "address_region": "program_or_external",
      "bytes": "15F72204B4",
      "text": "CMP:G.B #H'B4, @H'F722",
      "mnemonic": "CMP:G.B",
      "operands": "#H'B4, @H'F722",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63266,
          "name": null,
          "symbol": "ram_F722",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14708,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14713,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3983",
      "mnemonic": "BEQ",
      "operands": "loc_3983",
      "kind": "branch",
      "targets": [
        14723
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14708,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14715,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
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        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14715,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14716,
      "address_region": "program_or_external",
      "bytes": "0E17",
      "text": "BSR loc_3995",
      "mnemonic": "BSR",
      "operands": "loc_3995",
      "kind": "call",
      "targets": [
        14741
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14716,
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            "kind": "register",
            "name": "R0",
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              "reason": "block_entry"
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "register",
            "name": "R1",
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              "reason": "block_entry"
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              "reason": "call"
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          },
          {
            "kind": "register",
            "name": "R2",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "register",
            "name": "R4",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 14718,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14716,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14719,
      "address_region": "program_or_external",
      "bytes": "1E00AC",
      "text": "BSR loc_3A2E",
      "mnemonic": "BSR",
      "operands": "loc_3A2E",
      "kind": "call",
      "targets": [
        14894
      ],
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        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14719,
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            "kind": "register",
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              "reason": "call"
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          },
          {
            "kind": "register",
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              "reason": "call"
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          },
          {
            "kind": "register",
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              "reason": "block_entry"
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            "after": {
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              "reason": "call"
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              "reason": "call"
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          },
          {
            "kind": "register",
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              "reason": "block_entry"
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              "reason": "call"
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          },
          {
            "kind": "register",
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "register",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "register",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
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              "known": false,
              "reason": "block_entry"
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "control",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
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            "before": {
              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "SR",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 14722,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
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        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14719,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14723,
      "address_region": "program_or_external",
      "bytes": "0E05",
      "text": "BSR loc_398A",
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      "operands": "loc_398A",
      "kind": "call",
      "targets": [
        14730
      ],
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        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
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      "dataflow": {
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            "kind": "register",
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              "reason": "call"
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          },
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            "kind": "register",
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          },
          {
            "kind": "register",
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            "after": {
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              "reason": "call"
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          },
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            "kind": "register",
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              "reason": "block_entry"
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          },
          {
            "kind": "register",
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              "reason": "call"
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          },
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            "kind": "register",
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              "reason": "block_entry"
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              "reason": "call"
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          },
          {
            "kind": "register",
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              "reason": "block_entry"
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              "known": false,
              "reason": "call"
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          },
          {
            "kind": "register",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
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              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "EP",
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              "known": false,
              "reason": "block_entry"
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "control",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
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              "known": false,
              "reason": "block_entry"
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "SR",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 14725,
      "address_region": "program_or_external",
      "bytes": "15F72213",
      "text": "CLR.B @H'F722",
      "mnemonic": "CLR.B",
      "operands": "@H'F722",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63266,
          "name": null,
          "symbol": "ram_F722",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14723,
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            "kind": "control",
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              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14729,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
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        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14723,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14730,
      "address_region": "program_or_external",
      "bytes": "15FEE8F7",
      "text": "BTST.B #7, @ADCSR",
      "mnemonic": "BTST.B",
      "operands": "#7, @ADCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65256,
          "name": "ADCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14730,
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          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14734,
      "address_region": "program_or_external",
      "bytes": "2604",
      "text": "BNE loc_3994",
      "mnemonic": "BNE",
      "operands": "loc_3994",
      "kind": "branch",
      "targets": [
        14740
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14730,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14736,
      "address_region": "program_or_external",
      "bytes": "15FEE8C5",
      "text": "BSET.B #5, @ADCSR",
      "mnemonic": "BSET.B",
      "operands": "#5, @ADCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65256,
          "name": "ADCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set ADST (bit 5) of ADCSR",
      "valid": true,
      "dataflow": {
        "block": 14736,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14740,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14740,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14741,
      "address_region": "program_or_external",
      "bytes": "15F72016",
      "text": "TST.B @H'F720",
      "mnemonic": "TST.B",
      "operands": "@H'F720",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63264,
          "name": null,
          "symbol": "ram_F720",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14741,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14745,
      "address_region": "program_or_external",
      "bytes": "360091",
      "text": "BNE loc_3A2D",
      "mnemonic": "BNE",
      "operands": "loc_3A2D",
      "kind": "branch",
      "targets": [
        14893
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14741,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14748,
      "address_region": "program_or_external",
      "bytes": "15F10106A0",
      "text": "MOV:G.B #H'A0, @H'F101",
      "mnemonic": "MOV:G.B",
      "operands": "#H'A0, @H'F101",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61697,
          "name": null,
          "symbol": "mem_F101",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14748,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14753,
      "address_region": "program_or_external",
      "bytes": "15F100F1",
      "text": "BTST.B #1, @H'F100",
      "mnemonic": "BTST.B",
      "operands": "#1, @H'F100",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61696,
          "name": null,
          "symbol": "mem_F100",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14748,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14757,
      "address_region": "program_or_external",
      "bytes": "370085",
      "text": "BEQ loc_3A2D",
      "mnemonic": "BEQ",
      "operands": "loc_3A2D",
      "kind": "branch",
      "targets": [
        14893
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14748,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14760,
      "address_region": "program_or_external",
      "bytes": "15F71B80",
      "text": "MOV:G.B @H'F71B, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F71B, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63259,
          "name": null,
          "symbol": "ram_F71B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14764,
      "address_region": "program_or_external",
      "bytes": "15F72340",
      "text": "OR.B @H'F723, R0",
      "mnemonic": "OR.B",
      "operands": "@H'F723, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63267,
          "name": null,
          "symbol": "ram_F723",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14768,
      "address_region": "program_or_external",
      "bytes": "15F71350",
      "text": "AND.B @H'F713, R0",
      "mnemonic": "AND.B",
      "operands": "@H'F713, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63251,
          "name": null,
          "symbol": "ram_F713",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:OR.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14772,
      "address_region": "program_or_external",
      "bytes": "15F10290",
      "text": "MOV:G.B R0, @H'F102",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F102",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61698,
          "name": null,
          "symbol": "mem_F102",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14776,
      "address_region": "program_or_external",
      "bytes": "15F71A80",
      "text": "MOV:G.B @H'F71A, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F71A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63258,
          "name": null,
          "symbol": "ram_F71A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14780,
      "address_region": "program_or_external",
      "bytes": "15F72340",
      "text": "OR.B @H'F723, R0",
      "mnemonic": "OR.B",
      "operands": "@H'F723, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63267,
          "name": null,
          "symbol": "ram_F723",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14784,
      "address_region": "program_or_external",
      "bytes": "15F71250",
      "text": "AND.B @H'F712, R0",
      "mnemonic": "AND.B",
      "operands": "@H'F712, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63250,
          "name": null,
          "symbol": "ram_F712",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:OR.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14788,
      "address_region": "program_or_external",
      "bytes": "15F10390",
      "text": "MOV:G.B R0, @H'F103",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F103",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61699,
          "name": null,
          "symbol": "mem_F103",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14792,
      "address_region": "program_or_external",
      "bytes": "15F71980",
      "text": "MOV:G.B @H'F719, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F719, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63257,
          "name": null,
          "symbol": "ram_F719",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14796,
      "address_region": "program_or_external",
      "bytes": "15F72340",
      "text": "OR.B @H'F723, R0",
      "mnemonic": "OR.B",
      "operands": "@H'F723, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63267,
          "name": null,
          "symbol": "ram_F723",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14800,
      "address_region": "program_or_external",
      "bytes": "15F71150",
      "text": "AND.B @H'F711, R0",
      "mnemonic": "AND.B",
      "operands": "@H'F711, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63249,
          "name": null,
          "symbol": "ram_F711",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:OR.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14804,
      "address_region": "program_or_external",
      "bytes": "15F10490",
      "text": "MOV:G.B R0, @H'F104",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F104",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61700,
          "name": null,
          "symbol": "mem_F104",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14808,
      "address_region": "program_or_external",
      "bytes": "15F71880",
      "text": "MOV:G.B @H'F718, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F718, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63256,
          "name": null,
          "symbol": "ram_F718",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14812,
      "address_region": "program_or_external",
      "bytes": "15F72340",
      "text": "OR.B @H'F723, R0",
      "mnemonic": "OR.B",
      "operands": "@H'F723, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63267,
          "name": null,
          "symbol": "ram_F723",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14816,
      "address_region": "program_or_external",
      "bytes": "15F71050",
      "text": "AND.B @H'F710, R0",
      "mnemonic": "AND.B",
      "operands": "@H'F710, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63248,
          "name": null,
          "symbol": "ram_F710",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:OR.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14820,
      "address_region": "program_or_external",
      "bytes": "15F10590",
      "text": "MOV:G.B R0, @H'F105",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F105",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61701,
          "name": null,
          "symbol": "mem_F105",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14824,
      "address_region": "program_or_external",
      "bytes": "15F70280",
      "text": "MOV:G.B @H'F702, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F702, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63234,
          "name": null,
          "symbol": "ram_F702",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14828,
      "address_region": "program_or_external",
      "bytes": "15F10990",
      "text": "MOV:G.B R0, @H'F109",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F109",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61705,
          "name": null,
          "symbol": "mem_F109",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14832,
      "address_region": "program_or_external",
      "bytes": "15F70380",
      "text": "MOV:G.B @H'F703, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F703, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63235,
          "name": null,
          "symbol": "ram_F703",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14836,
      "address_region": "program_or_external",
      "bytes": "15F10A90",
      "text": "MOV:G.B R0, @H'F10A",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F10A",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61706,
          "name": null,
          "symbol": "mem_F10A",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14840,
      "address_region": "program_or_external",
      "bytes": "15F70480",
      "text": "MOV:G.B @H'F704, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F704, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63236,
          "name": null,
          "symbol": "ram_F704",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14844,
      "address_region": "program_or_external",
      "bytes": "15F10B90",
      "text": "MOV:G.B R0, @H'F10B",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F10B",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61707,
          "name": null,
          "symbol": "mem_F10B",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14848,
      "address_region": "program_or_external",
      "bytes": "15F70580",
      "text": "MOV:G.B @H'F705, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F705, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63237,
          "name": null,
          "symbol": "ram_F705",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14852,
      "address_region": "program_or_external",
      "bytes": "15F10C90",
      "text": "MOV:G.B R0, @H'F10C",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F10C",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61708,
          "name": null,
          "symbol": "mem_F10C",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14856,
      "address_region": "program_or_external",
      "bytes": "15F70080",
      "text": "MOV:G.B @H'F700, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F700, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63232,
          "name": null,
          "symbol": "ram_F700",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14860,
      "address_region": "program_or_external",
      "bytes": "15F10D90",
      "text": "MOV:G.B R0, @H'F10D",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F10D",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61709,
          "name": null,
          "symbol": "mem_F10D",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14864,
      "address_region": "program_or_external",
      "bytes": "15F70180",
      "text": "MOV:G.B @H'F701, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F701, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63233,
          "name": null,
          "symbol": "ram_F701",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14868,
      "address_region": "program_or_external",
      "bytes": "15F10E90",
      "text": "MOV:G.B R0, @H'F10E",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F10E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61710,
          "name": null,
          "symbol": "mem_F10E",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14872,
      "address_region": "program_or_external",
      "bytes": "15FE8E80",
      "text": "MOV:G.B @P7DR, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@P7DR, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65166,
          "name": "P7DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14876,
      "address_region": "program_or_external",
      "bytes": "A015",
      "text": "NOT.B R0",
      "mnemonic": "NOT.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:NOT.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14878,
      "address_region": "program_or_external",
      "bytes": "040350",
      "text": "AND.B #H'03, R0",
      "mnemonic": "AND.B",
      "operands": "#H'03, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:NOT.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14881,
      "address_region": "program_or_external",
      "bytes": "04A040",
      "text": "OR.B #H'A0, R0",
      "mnemonic": "OR.B",
      "operands": "#H'A0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14884,
      "address_region": "program_or_external",
      "bytes": "15F10F90",
      "text": "MOV:G.B R0, @H'F10F",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F10F",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61711,
          "name": null,
          "symbol": "mem_F10F",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14888,
      "address_region": "program_or_external",
      "bytes": "15F7200603",
      "text": "MOV:G.B #H'03, @H'F720",
      "mnemonic": "MOV:G.B",
      "operands": "#H'03, @H'F720",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63264,
          "name": null,
          "symbol": "ram_F720",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14893,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14893,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14894,
      "address_region": "program_or_external",
      "bytes": "15F72116",
      "text": "TST.B @H'F721",
      "mnemonic": "TST.B",
      "operands": "@H'F721",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63265,
          "name": null,
          "symbol": "ram_F721",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14894,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14898,
      "address_region": "program_or_external",
      "bytes": "360091",
      "text": "BNE loc_3AC6",
      "mnemonic": "BNE",
      "operands": "loc_3AC6",
      "kind": "branch",
      "targets": [
        15046
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14894,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14901,
      "address_region": "program_or_external",
      "bytes": "15F00106A0",
      "text": "MOV:G.B #H'A0, @H'F001",
      "mnemonic": "MOV:G.B",
      "operands": "#H'A0, @H'F001",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61441,
          "name": null,
          "symbol": "mem_F001",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14901,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 14906,
      "address_region": "program_or_external",
      "bytes": "15F000F1",
      "text": "BTST.B #1, @H'F000",
      "mnemonic": "BTST.B",
      "operands": "#1, @H'F000",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61440,
          "name": null,
          "symbol": "mem_F000",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14901,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14910,
      "address_region": "program_or_external",
      "bytes": "370085",
      "text": "BEQ loc_3AC6",
      "mnemonic": "BEQ",
      "operands": "loc_3AC6",
      "kind": "branch",
      "targets": [
        15046
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14901,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14913,
      "address_region": "program_or_external",
      "bytes": "15F71F80",
      "text": "MOV:G.B @H'F71F, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F71F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63263,
          "name": null,
          "symbol": "ram_F71F",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14917,
      "address_region": "program_or_external",
      "bytes": "15F72340",
      "text": "OR.B @H'F723, R0",
      "mnemonic": "OR.B",
      "operands": "@H'F723, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63267,
          "name": null,
          "symbol": "ram_F723",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14921,
      "address_region": "program_or_external",
      "bytes": "15F71750",
      "text": "AND.B @H'F717, R0",
      "mnemonic": "AND.B",
      "operands": "@H'F717, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63255,
          "name": null,
          "symbol": "ram_F717",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:OR.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14925,
      "address_region": "program_or_external",
      "bytes": "15F00290",
      "text": "MOV:G.B R0, @H'F002",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F002",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61442,
          "name": null,
          "symbol": "mem_F002",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14929,
      "address_region": "program_or_external",
      "bytes": "15F71E80",
      "text": "MOV:G.B @H'F71E, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F71E, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63262,
          "name": null,
          "symbol": "ram_F71E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14933,
      "address_region": "program_or_external",
      "bytes": "15F72340",
      "text": "OR.B @H'F723, R0",
      "mnemonic": "OR.B",
      "operands": "@H'F723, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63267,
          "name": null,
          "symbol": "ram_F723",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14937,
      "address_region": "program_or_external",
      "bytes": "15F71650",
      "text": "AND.B @H'F716, R0",
      "mnemonic": "AND.B",
      "operands": "@H'F716, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63254,
          "name": null,
          "symbol": "ram_F716",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:OR.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14941,
      "address_region": "program_or_external",
      "bytes": "15F00390",
      "text": "MOV:G.B R0, @H'F003",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F003",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61443,
          "name": null,
          "symbol": "mem_F003",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14945,
      "address_region": "program_or_external",
      "bytes": "15F71D80",
      "text": "MOV:G.B @H'F71D, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F71D, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63261,
          "name": null,
          "symbol": "ram_F71D",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14949,
      "address_region": "program_or_external",
      "bytes": "15F72340",
      "text": "OR.B @H'F723, R0",
      "mnemonic": "OR.B",
      "operands": "@H'F723, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63267,
          "name": null,
          "symbol": "ram_F723",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14953,
      "address_region": "program_or_external",
      "bytes": "15F71550",
      "text": "AND.B @H'F715, R0",
      "mnemonic": "AND.B",
      "operands": "@H'F715, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63253,
          "name": null,
          "symbol": "ram_F715",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:OR.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14957,
      "address_region": "program_or_external",
      "bytes": "15F00490",
      "text": "MOV:G.B R0, @H'F004",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F004",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61444,
          "name": null,
          "symbol": "mem_F004",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14961,
      "address_region": "program_or_external",
      "bytes": "15F71C80",
      "text": "MOV:G.B @H'F71C, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F71C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63260,
          "name": null,
          "symbol": "ram_F71C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14965,
      "address_region": "program_or_external",
      "bytes": "15F72340",
      "text": "OR.B @H'F723, R0",
      "mnemonic": "OR.B",
      "operands": "@H'F723, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63267,
          "name": null,
          "symbol": "ram_F723",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14969,
      "address_region": "program_or_external",
      "bytes": "15F71450",
      "text": "AND.B @H'F714, R0",
      "mnemonic": "AND.B",
      "operands": "@H'F714, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63252,
          "name": null,
          "symbol": "ram_F714",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:OR.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 14973,
      "address_region": "program_or_external",
      "bytes": "15F00590",
      "text": "MOV:G.B R0, @H'F005",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F005",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61445,
          "name": null,
          "symbol": "mem_F005",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14977,
      "address_region": "program_or_external",
      "bytes": "15F70880",
      "text": "MOV:G.B @H'F708, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F708, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63240,
          "name": null,
          "symbol": "ram_F708",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14981,
      "address_region": "program_or_external",
      "bytes": "15F00990",
      "text": "MOV:G.B R0, @H'F009",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F009",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61449,
          "name": null,
          "symbol": "mem_F009",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14985,
      "address_region": "program_or_external",
      "bytes": "15F70980",
      "text": "MOV:G.B @H'F709, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F709, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63241,
          "name": null,
          "symbol": "ram_F709",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14989,
      "address_region": "program_or_external",
      "bytes": "15F00A90",
      "text": "MOV:G.B R0, @H'F00A",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F00A",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61450,
          "name": null,
          "symbol": "mem_F00A",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 14993,
      "address_region": "program_or_external",
      "bytes": "15F70A80",
      "text": "MOV:G.B @H'F70A, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F70A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63242,
          "name": null,
          "symbol": "ram_F70A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 14997,
      "address_region": "program_or_external",
      "bytes": "15F00B90",
      "text": "MOV:G.B R0, @H'F00B",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F00B",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61451,
          "name": null,
          "symbol": "mem_F00B",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15001,
      "address_region": "program_or_external",
      "bytes": "15F70B80",
      "text": "MOV:G.B @H'F70B, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F70B, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63243,
          "name": null,
          "symbol": "ram_F70B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15005,
      "address_region": "program_or_external",
      "bytes": "15F00C90",
      "text": "MOV:G.B R0, @H'F00C",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F00C",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61452,
          "name": null,
          "symbol": "mem_F00C",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15009,
      "address_region": "program_or_external",
      "bytes": "15F70680",
      "text": "MOV:G.B @H'F706, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F706, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63238,
          "name": null,
          "symbol": "ram_F706",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15013,
      "address_region": "program_or_external",
      "bytes": "15F00D90",
      "text": "MOV:G.B R0, @H'F00D",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F00D",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61453,
          "name": null,
          "symbol": "mem_F00D",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15017,
      "address_region": "program_or_external",
      "bytes": "15F70780",
      "text": "MOV:G.B @H'F707, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F707, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63239,
          "name": null,
          "symbol": "ram_F707",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15021,
      "address_region": "program_or_external",
      "bytes": "15F00E90",
      "text": "MOV:G.B R0, @H'F00E",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F00E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61454,
          "name": null,
          "symbol": "mem_F00E",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15025,
      "address_region": "program_or_external",
      "bytes": "15FE8E80",
      "text": "MOV:G.B @P7DR, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@P7DR, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65166,
          "name": "P7DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15029,
      "address_region": "program_or_external",
      "bytes": "A015",
      "text": "NOT.B R0",
      "mnemonic": "NOT.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:NOT.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15031,
      "address_region": "program_or_external",
      "bytes": "040350",
      "text": "AND.B #H'03, R0",
      "mnemonic": "AND.B",
      "operands": "#H'03, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:NOT.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15034,
      "address_region": "program_or_external",
      "bytes": "04A040",
      "text": "OR.B #H'A0, R0",
      "mnemonic": "OR.B",
      "operands": "#H'A0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15037,
      "address_region": "program_or_external",
      "bytes": "15F00F90",
      "text": "MOV:G.B R0, @H'F00F",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F00F",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61455,
          "name": null,
          "symbol": "mem_F00F",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15041,
      "address_region": "program_or_external",
      "bytes": "15F7210603",
      "text": "MOV:G.B #H'03, @H'F721",
      "mnemonic": "MOV:G.B",
      "operands": "#H'03, @H'F721",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63265,
          "name": null,
          "symbol": "ram_F721",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 14913,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15046,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15046,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15047,
      "address_region": "program_or_external",
      "bytes": "BF90",
      "text": "MOV:G.W R0, @-R7",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @-R7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 5,
        "base_cycles": 5,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15047,
        "changes": [
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15049,
      "address_region": "program_or_external",
      "bytes": "15F100F1",
      "text": "BTST.B #1, @H'F100",
      "mnemonic": "BTST.B",
      "operands": "#1, @H'F100",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61696,
          "name": null,
          "symbol": "mem_F100",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15047,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15053,
      "address_region": "program_or_external",
      "bytes": "36015D",
      "text": "BNE loc_3C2D",
      "mnemonic": "BNE",
      "operands": "loc_3C2D",
      "kind": "branch",
      "targets": [
        15405
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15047,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15056,
      "address_region": "program_or_external",
      "bytes": "15F10F80",
      "text": "MOV:G.B @H'F10F, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F10F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61711,
          "name": null,
          "symbol": "mem_F10F",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15056,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15060,
      "address_region": "program_or_external",
      "bytes": "40A9",
      "text": "CMP:E #H'A9, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'A9, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15056,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15062,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3AE0",
      "mnemonic": "BEQ",
      "operands": "loc_3AE0",
      "kind": "branch",
      "targets": [
        15072
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15056,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15064,
      "address_region": "program_or_external",
      "bytes": "40A8",
      "text": "CMP:E #H'A8, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'A8, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15064,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15066,
      "address_region": "program_or_external",
      "bytes": "370085",
      "text": "BEQ loc_3B62",
      "mnemonic": "BEQ",
      "operands": "loc_3B62",
      "kind": "branch",
      "targets": [
        15202
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15064,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15069,
      "address_region": "program_or_external",
      "bytes": "30014D",
      "text": "BRA loc_3C2D",
      "mnemonic": "BRA",
      "operands": "loc_3C2D",
      "kind": "jump",
      "targets": [
        15405
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15069,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15072,
      "address_region": "program_or_external",
      "bytes": "15F6F080",
      "text": "MOV:G.B @H'F6F0, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6F0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15072,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15076,
      "address_region": "program_or_external",
      "bytes": "04C050",
      "text": "AND.B #H'C0, R0",
      "mnemonic": "AND.B",
      "operands": "#H'C0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15072,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15079,
      "address_region": "program_or_external",
      "bytes": "15F6F090",
      "text": "MOV:G.B R0, @H'F6F0",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15072,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15083,
      "address_region": "program_or_external",
      "bytes": "1DF10C80",
      "text": "MOV:G.W @H'F10C, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F10C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61708,
          "name": null,
          "symbol": "mem_F10C",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15072,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15087,
      "address_region": "program_or_external",
      "bytes": "1DF69A70",
      "text": "CMP:G.W @H'F69A, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F69A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63130,
          "name": null,
          "symbol": "ram_F69A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15072,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15091,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3AFD",
      "mnemonic": "BEQ",
      "operands": "loc_3AFD",
      "kind": "branch",
      "targets": [
        15101
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15072,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15093,
      "address_region": "program_or_external",
      "bytes": "15F6F0C5",
      "text": "BSET.B #5, @H'F6F0",
      "mnemonic": "BSET.B",
      "operands": "#5, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15093,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15097,
      "address_region": "program_or_external",
      "bytes": "1DF69A90",
      "text": "MOV:G.W R0, @H'F69A",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F69A",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63130,
          "name": null,
          "symbol": "ram_F69A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15093,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15101,
      "address_region": "program_or_external",
      "bytes": "1DF10A80",
      "text": "MOV:G.W @H'F10A, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F10A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61706,
          "name": null,
          "symbol": "mem_F10A",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15101,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15105,
      "address_region": "program_or_external",
      "bytes": "1DF69870",
      "text": "CMP:G.W @H'F698, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F698, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63128,
          "name": null,
          "symbol": "ram_F698",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15101,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15109,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3B0F",
      "mnemonic": "BEQ",
      "operands": "loc_3B0F",
      "kind": "branch",
      "targets": [
        15119
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15101,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15111,
      "address_region": "program_or_external",
      "bytes": "15F6F0C4",
      "text": "BSET.B #4, @H'F6F0",
      "mnemonic": "BSET.B",
      "operands": "#4, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15111,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15115,
      "address_region": "program_or_external",
      "bytes": "1DF69890",
      "text": "MOV:G.W R0, @H'F698",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F698",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63128,
          "name": null,
          "symbol": "ram_F698",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15111,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15119,
      "address_region": "program_or_external",
      "bytes": "1DF10880",
      "text": "MOV:G.W @H'F108, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F108, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61704,
          "name": null,
          "symbol": "mem_F108",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15119,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15123,
      "address_region": "program_or_external",
      "bytes": "1DF69670",
      "text": "CMP:G.W @H'F696, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F696, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63126,
          "name": null,
          "symbol": "ram_F696",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15119,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15127,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3B21",
      "mnemonic": "BEQ",
      "operands": "loc_3B21",
      "kind": "branch",
      "targets": [
        15137
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15119,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15129,
      "address_region": "program_or_external",
      "bytes": "15F6F0C3",
      "text": "BSET.B #3, @H'F6F0",
      "mnemonic": "BSET.B",
      "operands": "#3, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15129,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15133,
      "address_region": "program_or_external",
      "bytes": "1DF69690",
      "text": "MOV:G.W R0, @H'F696",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F696",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63126,
          "name": null,
          "symbol": "ram_F696",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15129,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15137,
      "address_region": "program_or_external",
      "bytes": "1DF10680",
      "text": "MOV:G.W @H'F106, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F106, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61702,
          "name": null,
          "symbol": "mem_F106",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15137,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15141,
      "address_region": "program_or_external",
      "bytes": "1DF69470",
      "text": "CMP:G.W @H'F694, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F694, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63124,
          "name": null,
          "symbol": "ram_F694",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15137,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15145,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3B33",
      "mnemonic": "BEQ",
      "operands": "loc_3B33",
      "kind": "branch",
      "targets": [
        15155
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15137,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15147,
      "address_region": "program_or_external",
      "bytes": "15F6F0C2",
      "text": "BSET.B #2, @H'F6F0",
      "mnemonic": "BSET.B",
      "operands": "#2, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15147,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15151,
      "address_region": "program_or_external",
      "bytes": "1DF69490",
      "text": "MOV:G.W R0, @H'F694",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F694",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63124,
          "name": null,
          "symbol": "ram_F694",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15147,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15155,
      "address_region": "program_or_external",
      "bytes": "1DF10480",
      "text": "MOV:G.W @H'F104, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F104, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61700,
          "name": null,
          "symbol": "mem_F104",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15155,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15159,
      "address_region": "program_or_external",
      "bytes": "1DF69270",
      "text": "CMP:G.W @H'F692, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F692, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63122,
          "name": null,
          "symbol": "ram_F692",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15155,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15163,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3B45",
      "mnemonic": "BEQ",
      "operands": "loc_3B45",
      "kind": "branch",
      "targets": [
        15173
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15155,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15165,
      "address_region": "program_or_external",
      "bytes": "15F6F0C1",
      "text": "BSET.B #1, @H'F6F0",
      "mnemonic": "BSET.B",
      "operands": "#1, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15165,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15169,
      "address_region": "program_or_external",
      "bytes": "1DF69290",
      "text": "MOV:G.W R0, @H'F692",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F692",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63122,
          "name": null,
          "symbol": "ram_F692",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15165,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15173,
      "address_region": "program_or_external",
      "bytes": "1DF10280",
      "text": "MOV:G.W @H'F102, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F102, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61698,
          "name": null,
          "symbol": "mem_F102",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15173,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15177,
      "address_region": "program_or_external",
      "bytes": "1DF69070",
      "text": "CMP:G.W @H'F690, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F690, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63120,
          "name": null,
          "symbol": "ram_F690",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15173,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15181,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3B57",
      "mnemonic": "BEQ",
      "operands": "loc_3B57",
      "kind": "branch",
      "targets": [
        15191
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15173,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15183,
      "address_region": "program_or_external",
      "bytes": "15F6F0C0",
      "text": "BSET.B #0, @H'F6F0",
      "mnemonic": "BSET.B",
      "operands": "#0, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15183,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15187,
      "address_region": "program_or_external",
      "bytes": "1DF69090",
      "text": "MOV:G.W R0, @H'F690",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F690",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63120,
          "name": null,
          "symbol": "ram_F690",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15183,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15191,
      "address_region": "program_or_external",
      "bytes": "15F10180",
      "text": "MOV:G.B @H'F101, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F101, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61697,
          "name": null,
          "symbol": "mem_F101",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15191,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15195,
      "address_region": "program_or_external",
      "bytes": "15F720D0",
      "text": "BCLR.B #0, @H'F720",
      "mnemonic": "BCLR.B",
      "operands": "#0, @H'F720",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63264,
          "name": null,
          "symbol": "ram_F720",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15191,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15199,
      "address_region": "program_or_external",
      "bytes": "3000CB",
      "text": "BRA loc_3C2D",
      "mnemonic": "BRA",
      "operands": "loc_3C2D",
      "kind": "jump",
      "targets": [
        15405
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15191,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15202,
      "address_region": "program_or_external",
      "bytes": "15F6F080",
      "text": "MOV:G.B @H'F6F0, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6F0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15202,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15206,
      "address_region": "program_or_external",
      "bytes": "043F50",
      "text": "AND.B #H'3F, R0",
      "mnemonic": "AND.B",
      "operands": "#H'3F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15202,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15209,
      "address_region": "program_or_external",
      "bytes": "15F6F090",
      "text": "MOV:G.B R0, @H'F6F0",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15202,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15213,
      "address_region": "program_or_external",
      "bytes": "15F6F213",
      "text": "CLR.B @H'F6F2",
      "mnemonic": "CLR.B",
      "operands": "@H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15202,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15217,
      "address_region": "program_or_external",
      "bytes": "1DF10C80",
      "text": "MOV:G.W @H'F10C, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F10C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61708,
          "name": null,
          "symbol": "mem_F10C",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15202,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15221,
      "address_region": "program_or_external",
      "bytes": "1DF69E70",
      "text": "CMP:G.W @H'F69E, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F69E, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63134,
          "name": null,
          "symbol": "ram_F69E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15202,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15225,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3B83",
      "mnemonic": "BEQ",
      "operands": "loc_3B83",
      "kind": "branch",
      "targets": [
        15235
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15202,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15227,
      "address_region": "program_or_external",
      "bytes": "15F6F0C7",
      "text": "BSET.B #7, @H'F6F0",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15227,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15231,
      "address_region": "program_or_external",
      "bytes": "1DF69E90",
      "text": "MOV:G.W R0, @H'F69E",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F69E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63134,
          "name": null,
          "symbol": "ram_F69E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15227,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15235,
      "address_region": "program_or_external",
      "bytes": "1DF10A80",
      "text": "MOV:G.W @H'F10A, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F10A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61706,
          "name": null,
          "symbol": "mem_F10A",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15235,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15239,
      "address_region": "program_or_external",
      "bytes": "1DF69C70",
      "text": "CMP:G.W @H'F69C, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F69C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63132,
          "name": null,
          "symbol": "ram_F69C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15235,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15243,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3B95",
      "mnemonic": "BEQ",
      "operands": "loc_3B95",
      "kind": "branch",
      "targets": [
        15253
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15235,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15245,
      "address_region": "program_or_external",
      "bytes": "15F6F0C6",
      "text": "BSET.B #6, @H'F6F0",
      "mnemonic": "BSET.B",
      "operands": "#6, @H'F6F0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63216,
          "name": null,
          "symbol": "ram_F6F0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15245,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15249,
      "address_region": "program_or_external",
      "bytes": "1DF69C90",
      "text": "MOV:G.W R0, @H'F69C",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F69C",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63132,
          "name": null,
          "symbol": "ram_F69C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15245,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15253,
      "address_region": "program_or_external",
      "bytes": "15F10980",
      "text": "MOV:G.B @H'F109, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F109, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61705,
          "name": null,
          "symbol": "mem_F109",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15253,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15257,
      "address_region": "program_or_external",
      "bytes": "15F6D070",
      "text": "CMP:G.B @H'F6D0, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63184,
          "name": null,
          "symbol": "ram_F6D0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15253,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15261,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3BA7",
      "mnemonic": "BEQ",
      "operands": "loc_3BA7",
      "kind": "branch",
      "targets": [
        15271
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15253,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15263,
      "address_region": "program_or_external",
      "bytes": "15F6F2C0",
      "text": "BSET.B #0, @H'F6F2",
      "mnemonic": "BSET.B",
      "operands": "#0, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15263,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15267,
      "address_region": "program_or_external",
      "bytes": "15F6D090",
      "text": "MOV:G.B R0, @H'F6D0",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63184,
          "name": null,
          "symbol": "ram_F6D0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15263,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15271,
      "address_region": "program_or_external",
      "bytes": "15F10880",
      "text": "MOV:G.B @H'F108, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F108, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61704,
          "name": null,
          "symbol": "mem_F108",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15271,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15275,
      "address_region": "program_or_external",
      "bytes": "15F6D170",
      "text": "CMP:G.B @H'F6D1, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63185,
          "name": null,
          "symbol": "ram_F6D1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15271,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15279,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3BB9",
      "mnemonic": "BEQ",
      "operands": "loc_3BB9",
      "kind": "branch",
      "targets": [
        15289
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15271,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15281,
      "address_region": "program_or_external",
      "bytes": "15F6F2C1",
      "text": "BSET.B #1, @H'F6F2",
      "mnemonic": "BSET.B",
      "operands": "#1, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15281,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15285,
      "address_region": "program_or_external",
      "bytes": "15F6D190",
      "text": "MOV:G.B R0, @H'F6D1",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63185,
          "name": null,
          "symbol": "ram_F6D1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15281,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15289,
      "address_region": "program_or_external",
      "bytes": "15F10780",
      "text": "MOV:G.B @H'F107, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F107, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61703,
          "name": null,
          "symbol": "mem_F107",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15289,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15293,
      "address_region": "program_or_external",
      "bytes": "15F6D270",
      "text": "CMP:G.B @H'F6D2, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63186,
          "name": null,
          "symbol": "ram_F6D2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15289,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15297,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3BCB",
      "mnemonic": "BEQ",
      "operands": "loc_3BCB",
      "kind": "branch",
      "targets": [
        15307
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15289,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15299,
      "address_region": "program_or_external",
      "bytes": "15F6F2C2",
      "text": "BSET.B #2, @H'F6F2",
      "mnemonic": "BSET.B",
      "operands": "#2, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15299,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15303,
      "address_region": "program_or_external",
      "bytes": "15F6D290",
      "text": "MOV:G.B R0, @H'F6D2",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63186,
          "name": null,
          "symbol": "ram_F6D2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15299,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15307,
      "address_region": "program_or_external",
      "bytes": "15F10680",
      "text": "MOV:G.B @H'F106, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F106, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61702,
          "name": null,
          "symbol": "mem_F106",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15307,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15311,
      "address_region": "program_or_external",
      "bytes": "15F6D370",
      "text": "CMP:G.B @H'F6D3, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D3, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63187,
          "name": null,
          "symbol": "ram_F6D3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15307,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15315,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3BDD",
      "mnemonic": "BEQ",
      "operands": "loc_3BDD",
      "kind": "branch",
      "targets": [
        15325
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15307,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15317,
      "address_region": "program_or_external",
      "bytes": "15F6F2C3",
      "text": "BSET.B #3, @H'F6F2",
      "mnemonic": "BSET.B",
      "operands": "#3, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15317,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15321,
      "address_region": "program_or_external",
      "bytes": "15F6D390",
      "text": "MOV:G.B R0, @H'F6D3",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63187,
          "name": null,
          "symbol": "ram_F6D3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15317,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15325,
      "address_region": "program_or_external",
      "bytes": "15F10580",
      "text": "MOV:G.B @H'F105, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F105, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61701,
          "name": null,
          "symbol": "mem_F105",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15325,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15329,
      "address_region": "program_or_external",
      "bytes": "15F6D470",
      "text": "CMP:G.B @H'F6D4, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D4, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63188,
          "name": null,
          "symbol": "ram_F6D4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15325,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15333,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3BEF",
      "mnemonic": "BEQ",
      "operands": "loc_3BEF",
      "kind": "branch",
      "targets": [
        15343
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15325,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15335,
      "address_region": "program_or_external",
      "bytes": "15F6F2C4",
      "text": "BSET.B #4, @H'F6F2",
      "mnemonic": "BSET.B",
      "operands": "#4, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15335,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15339,
      "address_region": "program_or_external",
      "bytes": "15F6D490",
      "text": "MOV:G.B R0, @H'F6D4",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63188,
          "name": null,
          "symbol": "ram_F6D4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15335,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15343,
      "address_region": "program_or_external",
      "bytes": "15F10480",
      "text": "MOV:G.B @H'F104, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F104, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61700,
          "name": null,
          "symbol": "mem_F104",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15343,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15347,
      "address_region": "program_or_external",
      "bytes": "15F6D570",
      "text": "CMP:G.B @H'F6D5, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D5, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63189,
          "name": null,
          "symbol": "ram_F6D5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15343,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15351,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3C01",
      "mnemonic": "BEQ",
      "operands": "loc_3C01",
      "kind": "branch",
      "targets": [
        15361
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15343,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15353,
      "address_region": "program_or_external",
      "bytes": "15F6F2C5",
      "text": "BSET.B #5, @H'F6F2",
      "mnemonic": "BSET.B",
      "operands": "#5, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15353,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15357,
      "address_region": "program_or_external",
      "bytes": "15F6D590",
      "text": "MOV:G.B R0, @H'F6D5",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63189,
          "name": null,
          "symbol": "ram_F6D5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15353,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15361,
      "address_region": "program_or_external",
      "bytes": "15F10380",
      "text": "MOV:G.B @H'F103, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F103, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61699,
          "name": null,
          "symbol": "mem_F103",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15361,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15365,
      "address_region": "program_or_external",
      "bytes": "15F6D670",
      "text": "CMP:G.B @H'F6D6, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D6, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63190,
          "name": null,
          "symbol": "ram_F6D6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15361,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15369,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3C13",
      "mnemonic": "BEQ",
      "operands": "loc_3C13",
      "kind": "branch",
      "targets": [
        15379
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15361,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15371,
      "address_region": "program_or_external",
      "bytes": "15F6F2C6",
      "text": "BSET.B #6, @H'F6F2",
      "mnemonic": "BSET.B",
      "operands": "#6, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15371,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15375,
      "address_region": "program_or_external",
      "bytes": "15F6D690",
      "text": "MOV:G.B R0, @H'F6D6",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63190,
          "name": null,
          "symbol": "ram_F6D6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15371,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15379,
      "address_region": "program_or_external",
      "bytes": "15F10280",
      "text": "MOV:G.B @H'F102, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F102, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61698,
          "name": null,
          "symbol": "mem_F102",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15379,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15383,
      "address_region": "program_or_external",
      "bytes": "15F6D770",
      "text": "CMP:G.B @H'F6D7, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D7, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63191,
          "name": null,
          "symbol": "ram_F6D7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15379,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15387,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3C25",
      "mnemonic": "BEQ",
      "operands": "loc_3C25",
      "kind": "branch",
      "targets": [
        15397
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15379,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15389,
      "address_region": "program_or_external",
      "bytes": "15F6F2C7",
      "text": "BSET.B #7, @H'F6F2",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'F6F2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63218,
          "name": null,
          "symbol": "ram_F6F2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15389,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15393,
      "address_region": "program_or_external",
      "bytes": "15F6D790",
      "text": "MOV:G.B R0, @H'F6D7",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63191,
          "name": null,
          "symbol": "ram_F6D7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15389,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15397,
      "address_region": "program_or_external",
      "bytes": "15F10180",
      "text": "MOV:G.B @H'F101, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F101, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61697,
          "name": null,
          "symbol": "mem_F101",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15397,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15401,
      "address_region": "program_or_external",
      "bytes": "15F720D1",
      "text": "BCLR.B #1, @H'F720",
      "mnemonic": "BCLR.B",
      "operands": "#1, @H'F720",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63264,
          "name": null,
          "symbol": "ram_F720",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15397,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15405,
      "address_region": "program_or_external",
      "bytes": "CF80",
      "text": "MOV:G.W @R7+, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@R7+, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 5,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15405,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15407,
      "address_region": "program_or_external",
      "bytes": "0A",
      "text": "RTE",
      "mnemonic": "RTE",
      "operands": "",
      "kind": "rte",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "base_cycles": 13,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15405,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15408,
      "address_region": "program_or_external",
      "bytes": "BF90",
      "text": "MOV:G.W R0, @-R7",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @-R7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 5,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15408,
        "changes": [
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15410,
      "address_region": "program_or_external",
      "bytes": "15F000F1",
      "text": "BTST.B #1, @H'F000",
      "mnemonic": "BTST.B",
      "operands": "#1, @H'F000",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61440,
          "name": null,
          "symbol": "mem_F000",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15408,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15414,
      "address_region": "program_or_external",
      "bytes": "36015D",
      "text": "BNE loc_3D96",
      "mnemonic": "BNE",
      "operands": "loc_3D96",
      "kind": "branch",
      "targets": [
        15766
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15408,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15417,
      "address_region": "program_or_external",
      "bytes": "15F00F80",
      "text": "MOV:G.B @H'F00F, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F00F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61455,
          "name": null,
          "symbol": "mem_F00F",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15417,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15421,
      "address_region": "program_or_external",
      "bytes": "40A9",
      "text": "CMP:E #H'A9, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'A9, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15417,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15423,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3C49",
      "mnemonic": "BEQ",
      "operands": "loc_3C49",
      "kind": "branch",
      "targets": [
        15433
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15417,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15425,
      "address_region": "program_or_external",
      "bytes": "40A8",
      "text": "CMP:E #H'A8, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'A8, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15425,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15427,
      "address_region": "program_or_external",
      "bytes": "370085",
      "text": "BEQ loc_3CCB",
      "mnemonic": "BEQ",
      "operands": "loc_3CCB",
      "kind": "branch",
      "targets": [
        15563
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15425,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15430,
      "address_region": "program_or_external",
      "bytes": "30014D",
      "text": "BRA loc_3D96",
      "mnemonic": "BRA",
      "operands": "loc_3D96",
      "kind": "jump",
      "targets": [
        15766
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15430,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15433,
      "address_region": "program_or_external",
      "bytes": "15F6F180",
      "text": "MOV:G.B @H'F6F1, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6F1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15433,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15437,
      "address_region": "program_or_external",
      "bytes": "04C050",
      "text": "AND.B #H'C0, R0",
      "mnemonic": "AND.B",
      "operands": "#H'C0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15433,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15440,
      "address_region": "program_or_external",
      "bytes": "15F6F190",
      "text": "MOV:G.B R0, @H'F6F1",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15433,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15444,
      "address_region": "program_or_external",
      "bytes": "1DF00C80",
      "text": "MOV:G.W @H'F00C, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F00C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61452,
          "name": null,
          "symbol": "mem_F00C",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15433,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15448,
      "address_region": "program_or_external",
      "bytes": "1DF6AA70",
      "text": "CMP:G.W @H'F6AA, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F6AA, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63146,
          "name": null,
          "symbol": "ram_F6AA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15433,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15452,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3C66",
      "mnemonic": "BEQ",
      "operands": "loc_3C66",
      "kind": "branch",
      "targets": [
        15462
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15433,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15454,
      "address_region": "program_or_external",
      "bytes": "15F6F1C5",
      "text": "BSET.B #5, @H'F6F1",
      "mnemonic": "BSET.B",
      "operands": "#5, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15454,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15458,
      "address_region": "program_or_external",
      "bytes": "1DF6AA90",
      "text": "MOV:G.W R0, @H'F6AA",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F6AA",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63146,
          "name": null,
          "symbol": "ram_F6AA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15454,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15462,
      "address_region": "program_or_external",
      "bytes": "1DF00A80",
      "text": "MOV:G.W @H'F00A, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F00A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61450,
          "name": null,
          "symbol": "mem_F00A",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15462,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15466,
      "address_region": "program_or_external",
      "bytes": "1DF6A870",
      "text": "CMP:G.W @H'F6A8, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F6A8, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63144,
          "name": null,
          "symbol": "ram_F6A8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15462,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15470,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3C78",
      "mnemonic": "BEQ",
      "operands": "loc_3C78",
      "kind": "branch",
      "targets": [
        15480
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15462,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15472,
      "address_region": "program_or_external",
      "bytes": "15F6F1C4",
      "text": "BSET.B #4, @H'F6F1",
      "mnemonic": "BSET.B",
      "operands": "#4, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15472,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15476,
      "address_region": "program_or_external",
      "bytes": "1DF6A890",
      "text": "MOV:G.W R0, @H'F6A8",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F6A8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63144,
          "name": null,
          "symbol": "ram_F6A8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15472,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15480,
      "address_region": "program_or_external",
      "bytes": "1DF00880",
      "text": "MOV:G.W @H'F008, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F008, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61448,
          "name": null,
          "symbol": "mem_F008",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15480,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15484,
      "address_region": "program_or_external",
      "bytes": "1DF6A670",
      "text": "CMP:G.W @H'F6A6, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F6A6, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63142,
          "name": null,
          "symbol": "ram_F6A6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15480,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15488,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3C8A",
      "mnemonic": "BEQ",
      "operands": "loc_3C8A",
      "kind": "branch",
      "targets": [
        15498
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15480,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15490,
      "address_region": "program_or_external",
      "bytes": "15F6F1C3",
      "text": "BSET.B #3, @H'F6F1",
      "mnemonic": "BSET.B",
      "operands": "#3, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15490,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15494,
      "address_region": "program_or_external",
      "bytes": "1DF6A690",
      "text": "MOV:G.W R0, @H'F6A6",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F6A6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63142,
          "name": null,
          "symbol": "ram_F6A6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15490,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15498,
      "address_region": "program_or_external",
      "bytes": "1DF00680",
      "text": "MOV:G.W @H'F006, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F006, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61446,
          "name": null,
          "symbol": "mem_F006",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15498,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15502,
      "address_region": "program_or_external",
      "bytes": "1DF6A470",
      "text": "CMP:G.W @H'F6A4, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F6A4, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63140,
          "name": null,
          "symbol": "ram_F6A4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15498,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15506,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3C9C",
      "mnemonic": "BEQ",
      "operands": "loc_3C9C",
      "kind": "branch",
      "targets": [
        15516
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15498,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15508,
      "address_region": "program_or_external",
      "bytes": "15F6F1C2",
      "text": "BSET.B #2, @H'F6F1",
      "mnemonic": "BSET.B",
      "operands": "#2, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15508,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15512,
      "address_region": "program_or_external",
      "bytes": "1DF6A490",
      "text": "MOV:G.W R0, @H'F6A4",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F6A4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63140,
          "name": null,
          "symbol": "ram_F6A4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15508,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15516,
      "address_region": "program_or_external",
      "bytes": "1DF00480",
      "text": "MOV:G.W @H'F004, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F004, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61444,
          "name": null,
          "symbol": "mem_F004",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15516,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15520,
      "address_region": "program_or_external",
      "bytes": "1DF6A270",
      "text": "CMP:G.W @H'F6A2, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F6A2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63138,
          "name": null,
          "symbol": "ram_F6A2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15516,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15524,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3CAE",
      "mnemonic": "BEQ",
      "operands": "loc_3CAE",
      "kind": "branch",
      "targets": [
        15534
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15516,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15526,
      "address_region": "program_or_external",
      "bytes": "15F6F1C1",
      "text": "BSET.B #1, @H'F6F1",
      "mnemonic": "BSET.B",
      "operands": "#1, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15526,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15530,
      "address_region": "program_or_external",
      "bytes": "1DF6A290",
      "text": "MOV:G.W R0, @H'F6A2",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F6A2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63138,
          "name": null,
          "symbol": "ram_F6A2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15526,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15534,
      "address_region": "program_or_external",
      "bytes": "1DF00280",
      "text": "MOV:G.W @H'F002, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F002, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61442,
          "name": null,
          "symbol": "mem_F002",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15534,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15538,
      "address_region": "program_or_external",
      "bytes": "1DF6A070",
      "text": "CMP:G.W @H'F6A0, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F6A0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63136,
          "name": null,
          "symbol": "ram_F6A0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15534,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15542,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3CC0",
      "mnemonic": "BEQ",
      "operands": "loc_3CC0",
      "kind": "branch",
      "targets": [
        15552
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15534,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15544,
      "address_region": "program_or_external",
      "bytes": "15F6F1C0",
      "text": "BSET.B #0, @H'F6F1",
      "mnemonic": "BSET.B",
      "operands": "#0, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15544,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15548,
      "address_region": "program_or_external",
      "bytes": "1DF6A090",
      "text": "MOV:G.W R0, @H'F6A0",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F6A0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63136,
          "name": null,
          "symbol": "ram_F6A0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15544,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15552,
      "address_region": "program_or_external",
      "bytes": "15F00180",
      "text": "MOV:G.B @H'F001, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F001, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61441,
          "name": null,
          "symbol": "mem_F001",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15552,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15556,
      "address_region": "program_or_external",
      "bytes": "15F721D0",
      "text": "BCLR.B #0, @H'F721",
      "mnemonic": "BCLR.B",
      "operands": "#0, @H'F721",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63265,
          "name": null,
          "symbol": "ram_F721",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15552,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15560,
      "address_region": "program_or_external",
      "bytes": "3000CB",
      "text": "BRA loc_3D96",
      "mnemonic": "BRA",
      "operands": "loc_3D96",
      "kind": "jump",
      "targets": [
        15766
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15552,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15563,
      "address_region": "program_or_external",
      "bytes": "15F6F180",
      "text": "MOV:G.B @H'F6F1, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F6F1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15563,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15567,
      "address_region": "program_or_external",
      "bytes": "043F50",
      "text": "AND.B #H'3F, R0",
      "mnemonic": "AND.B",
      "operands": "#H'3F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15563,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15570,
      "address_region": "program_or_external",
      "bytes": "15F6F190",
      "text": "MOV:G.B R0, @H'F6F1",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15563,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15574,
      "address_region": "program_or_external",
      "bytes": "15F6F313",
      "text": "CLR.B @H'F6F3",
      "mnemonic": "CLR.B",
      "operands": "@H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15563,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15578,
      "address_region": "program_or_external",
      "bytes": "1DF00C80",
      "text": "MOV:G.W @H'F00C, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F00C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61452,
          "name": null,
          "symbol": "mem_F00C",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15563,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15582,
      "address_region": "program_or_external",
      "bytes": "1DF6AE70",
      "text": "CMP:G.W @H'F6AE, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F6AE, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63150,
          "name": null,
          "symbol": "ram_F6AE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15563,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15586,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3CEC",
      "mnemonic": "BEQ",
      "operands": "loc_3CEC",
      "kind": "branch",
      "targets": [
        15596
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15563,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15588,
      "address_region": "program_or_external",
      "bytes": "15F6F1C7",
      "text": "BSET.B #7, @H'F6F1",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15588,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15592,
      "address_region": "program_or_external",
      "bytes": "1DF6AE90",
      "text": "MOV:G.W R0, @H'F6AE",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F6AE",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63150,
          "name": null,
          "symbol": "ram_F6AE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15588,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15596,
      "address_region": "program_or_external",
      "bytes": "1DF00A80",
      "text": "MOV:G.W @H'F00A, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F00A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61450,
          "name": null,
          "symbol": "mem_F00A",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15596,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15600,
      "address_region": "program_or_external",
      "bytes": "1DF6AC70",
      "text": "CMP:G.W @H'F6AC, R0",
      "mnemonic": "CMP:G.W",
      "operands": "@H'F6AC, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63148,
          "name": null,
          "symbol": "ram_F6AC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15596,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15604,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3CFE",
      "mnemonic": "BEQ",
      "operands": "loc_3CFE",
      "kind": "branch",
      "targets": [
        15614
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15596,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15606,
      "address_region": "program_or_external",
      "bytes": "15F6F1C6",
      "text": "BSET.B #6, @H'F6F1",
      "mnemonic": "BSET.B",
      "operands": "#6, @H'F6F1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63217,
          "name": null,
          "symbol": "ram_F6F1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15606,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15610,
      "address_region": "program_or_external",
      "bytes": "1DF6AC90",
      "text": "MOV:G.W R0, @H'F6AC",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F6AC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63148,
          "name": null,
          "symbol": "ram_F6AC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15606,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15614,
      "address_region": "program_or_external",
      "bytes": "15F00980",
      "text": "MOV:G.B @H'F009, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F009, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61449,
          "name": null,
          "symbol": "mem_F009",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15614,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15618,
      "address_region": "program_or_external",
      "bytes": "15F6D870",
      "text": "CMP:G.B @H'F6D8, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D8, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63192,
          "name": null,
          "symbol": "ram_F6D8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15614,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15622,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3D10",
      "mnemonic": "BEQ",
      "operands": "loc_3D10",
      "kind": "branch",
      "targets": [
        15632
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15614,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15624,
      "address_region": "program_or_external",
      "bytes": "15F6F3C0",
      "text": "BSET.B #0, @H'F6F3",
      "mnemonic": "BSET.B",
      "operands": "#0, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15624,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15628,
      "address_region": "program_or_external",
      "bytes": "15F6D890",
      "text": "MOV:G.B R0, @H'F6D8",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63192,
          "name": null,
          "symbol": "ram_F6D8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15624,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15632,
      "address_region": "program_or_external",
      "bytes": "15F00880",
      "text": "MOV:G.B @H'F008, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F008, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61448,
          "name": null,
          "symbol": "mem_F008",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15632,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15636,
      "address_region": "program_or_external",
      "bytes": "15F6D970",
      "text": "CMP:G.B @H'F6D9, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6D9, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63193,
          "name": null,
          "symbol": "ram_F6D9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15632,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15640,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3D22",
      "mnemonic": "BEQ",
      "operands": "loc_3D22",
      "kind": "branch",
      "targets": [
        15650
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15632,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15642,
      "address_region": "program_or_external",
      "bytes": "15F6F3C1",
      "text": "BSET.B #1, @H'F6F3",
      "mnemonic": "BSET.B",
      "operands": "#1, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15642,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15646,
      "address_region": "program_or_external",
      "bytes": "15F6D990",
      "text": "MOV:G.B R0, @H'F6D9",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6D9",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63193,
          "name": null,
          "symbol": "ram_F6D9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15642,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15650,
      "address_region": "program_or_external",
      "bytes": "15F00780",
      "text": "MOV:G.B @H'F007, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F007, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61447,
          "name": null,
          "symbol": "mem_F007",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15650,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15654,
      "address_region": "program_or_external",
      "bytes": "15F6DA70",
      "text": "CMP:G.B @H'F6DA, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6DA, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63194,
          "name": null,
          "symbol": "ram_F6DA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15650,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15658,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3D34",
      "mnemonic": "BEQ",
      "operands": "loc_3D34",
      "kind": "branch",
      "targets": [
        15668
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15650,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15660,
      "address_region": "program_or_external",
      "bytes": "15F6F3C2",
      "text": "BSET.B #2, @H'F6F3",
      "mnemonic": "BSET.B",
      "operands": "#2, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15660,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15664,
      "address_region": "program_or_external",
      "bytes": "15F6DA90",
      "text": "MOV:G.B R0, @H'F6DA",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6DA",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63194,
          "name": null,
          "symbol": "ram_F6DA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15660,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15668,
      "address_region": "program_or_external",
      "bytes": "15F00680",
      "text": "MOV:G.B @H'F006, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F006, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61446,
          "name": null,
          "symbol": "mem_F006",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15668,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15672,
      "address_region": "program_or_external",
      "bytes": "15F6DB70",
      "text": "CMP:G.B @H'F6DB, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6DB, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63195,
          "name": null,
          "symbol": "ram_F6DB",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15668,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15676,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3D46",
      "mnemonic": "BEQ",
      "operands": "loc_3D46",
      "kind": "branch",
      "targets": [
        15686
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15668,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15678,
      "address_region": "program_or_external",
      "bytes": "15F6F3C3",
      "text": "BSET.B #3, @H'F6F3",
      "mnemonic": "BSET.B",
      "operands": "#3, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15678,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15682,
      "address_region": "program_or_external",
      "bytes": "15F6DB90",
      "text": "MOV:G.B R0, @H'F6DB",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6DB",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63195,
          "name": null,
          "symbol": "ram_F6DB",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15678,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15686,
      "address_region": "program_or_external",
      "bytes": "15F00580",
      "text": "MOV:G.B @H'F005, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F005, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61445,
          "name": null,
          "symbol": "mem_F005",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15686,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15690,
      "address_region": "program_or_external",
      "bytes": "15F6DC70",
      "text": "CMP:G.B @H'F6DC, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6DC, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63196,
          "name": null,
          "symbol": "ram_F6DC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15686,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15694,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3D58",
      "mnemonic": "BEQ",
      "operands": "loc_3D58",
      "kind": "branch",
      "targets": [
        15704
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15686,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15696,
      "address_region": "program_or_external",
      "bytes": "15F6F3C4",
      "text": "BSET.B #4, @H'F6F3",
      "mnemonic": "BSET.B",
      "operands": "#4, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15696,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15700,
      "address_region": "program_or_external",
      "bytes": "15F6DC90",
      "text": "MOV:G.B R0, @H'F6DC",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6DC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63196,
          "name": null,
          "symbol": "ram_F6DC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15696,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15704,
      "address_region": "program_or_external",
      "bytes": "15F00480",
      "text": "MOV:G.B @H'F004, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F004, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61444,
          "name": null,
          "symbol": "mem_F004",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15704,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15708,
      "address_region": "program_or_external",
      "bytes": "15F6DD70",
      "text": "CMP:G.B @H'F6DD, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6DD, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63197,
          "name": null,
          "symbol": "ram_F6DD",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15704,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15712,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3D6A",
      "mnemonic": "BEQ",
      "operands": "loc_3D6A",
      "kind": "branch",
      "targets": [
        15722
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15704,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15714,
      "address_region": "program_or_external",
      "bytes": "15F6F3C5",
      "text": "BSET.B #5, @H'F6F3",
      "mnemonic": "BSET.B",
      "operands": "#5, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15714,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15718,
      "address_region": "program_or_external",
      "bytes": "15F6DD90",
      "text": "MOV:G.B R0, @H'F6DD",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6DD",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63197,
          "name": null,
          "symbol": "ram_F6DD",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15714,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15722,
      "address_region": "program_or_external",
      "bytes": "15F00380",
      "text": "MOV:G.B @H'F003, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F003, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61443,
          "name": null,
          "symbol": "mem_F003",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15722,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15726,
      "address_region": "program_or_external",
      "bytes": "15F6DE70",
      "text": "CMP:G.B @H'F6DE, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6DE, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63198,
          "name": null,
          "symbol": "ram_F6DE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15722,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15730,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3D7C",
      "mnemonic": "BEQ",
      "operands": "loc_3D7C",
      "kind": "branch",
      "targets": [
        15740
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15722,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15732,
      "address_region": "program_or_external",
      "bytes": "15F6F3C6",
      "text": "BSET.B #6, @H'F6F3",
      "mnemonic": "BSET.B",
      "operands": "#6, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15732,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15736,
      "address_region": "program_or_external",
      "bytes": "15F6DE90",
      "text": "MOV:G.B R0, @H'F6DE",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6DE",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63198,
          "name": null,
          "symbol": "ram_F6DE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15732,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15740,
      "address_region": "program_or_external",
      "bytes": "15F00280",
      "text": "MOV:G.B @H'F002, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F002, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61442,
          "name": null,
          "symbol": "mem_F002",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15740,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15744,
      "address_region": "program_or_external",
      "bytes": "15F6DF70",
      "text": "CMP:G.B @H'F6DF, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F6DF, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63199,
          "name": null,
          "symbol": "ram_F6DF",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15740,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15748,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3D8E",
      "mnemonic": "BEQ",
      "operands": "loc_3D8E",
      "kind": "branch",
      "targets": [
        15758
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15740,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15750,
      "address_region": "program_or_external",
      "bytes": "15F6F3C7",
      "text": "BSET.B #7, @H'F6F3",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'F6F3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63219,
          "name": null,
          "symbol": "ram_F6F3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15750,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15754,
      "address_region": "program_or_external",
      "bytes": "15F6DF90",
      "text": "MOV:G.B R0, @H'F6DF",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F6DF",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63199,
          "name": null,
          "symbol": "ram_F6DF",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15750,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15758,
      "address_region": "program_or_external",
      "bytes": "15F00180",
      "text": "MOV:G.B @H'F001, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F001, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61441,
          "name": null,
          "symbol": "mem_F001",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15758,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15762,
      "address_region": "program_or_external",
      "bytes": "15F721D1",
      "text": "BCLR.B #1, @H'F721",
      "mnemonic": "BCLR.B",
      "operands": "#1, @H'F721",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63265,
          "name": null,
          "symbol": "ram_F721",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15758,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15766,
      "address_region": "program_or_external",
      "bytes": "CF80",
      "text": "MOV:G.W @R7+, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@R7+, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 5,
        "base_cycles": 5,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15766,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15768,
      "address_region": "program_or_external",
      "bytes": "0A",
      "text": "RTE",
      "mnemonic": "RTE",
      "operands": "",
      "kind": "rte",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 13,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15766,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15769,
      "address_region": "program_or_external",
      "bytes": "15FEE8D5",
      "text": "BCLR.B #5, @ADCSR",
      "mnemonic": "BCLR.B",
      "operands": "#5, @ADCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65256,
          "name": "ADCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear ADST (bit 5) of ADCSR",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15773,
      "address_region": "program_or_external",
      "bytes": "123F",
      "text": "STM.W {R0,R1,R2,R3,R4,R5}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R1,R2,R3,R4,R5}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 24,
        "note": "6+3n, n=6",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15775,
      "address_region": "program_or_external",
      "bytes": "15F68A80",
      "text": "MOV:G.B @H'F68A, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F68A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63114,
          "name": null,
          "symbol": "ram_F68A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15779,
      "address_region": "program_or_external",
      "bytes": "0414A8",
      "text": "MULXU.B #H'14, R0",
      "mnemonic": "MULXU.B",
      "operands": "#H'14, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 19,
        "base_cycles": 19,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:MULXU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15782,
      "address_region": "program_or_external",
      "bytes": "1DFEE081",
      "text": "MOV:G.W @ADDRA_H, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@ADDRA_H, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65248,
          "name": "ADDRA_H",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "peripheral_access": [
        {
          "address": 15782,
          "instruction": "MOV:G.W @ADDRA_H, R1",
          "register": "ADDRA",
          "high_address": 65248,
          "low_address": 65249,
          "referenced_address": 65248,
          "referenced_address_hex": "H'FEE0",
          "byte": "high",
          "size": "W",
          "direction": "read"
        }
      ],
      "dataflow": {
        "block": 15769,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 15786,
      "address_region": "program_or_external",
      "bytes": "A110",
      "text": "SWAP.B R1",
      "mnemonic": "SWAP.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 15788,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 15790,
      "address_region": "program_or_external",
      "bytes": "F1CFB681",
      "text": "MOV:G.B @(-H'304A,R1), R1",
      "mnemonic": "MOV:G.B",
      "operands": "@(-H'304A,R1), R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 15794,
      "address_region": "program_or_external",
      "bytes": "A920",
      "text": "ADD:G.W R1, R0",
      "mnemonic": "ADD:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:MULXU.B"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 15796,
      "address_region": "program_or_external",
      "bytes": "0415B8",
      "text": "DIVXU.B #H'15, R0",
      "mnemonic": "DIVXU.B",
      "operands": "#H'15, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 23,
        "base_cycles": 23,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:DIVXU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15799,
      "address_region": "program_or_external",
      "bytes": "15F68A70",
      "text": "CMP:G.B @H'F68A, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F68A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63114,
          "name": null,
          "symbol": "ram_F68A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15803,
      "address_region": "program_or_external",
      "bytes": "274B",
      "text": "BEQ loc_3E08",
      "mnemonic": "BEQ",
      "operands": "loc_3E08",
      "kind": "branch",
      "targets": [
        15880
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15769,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15805,
      "address_region": "program_or_external",
      "bytes": "15F68A82",
      "text": "MOV:G.B @H'F68A, R2",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F68A, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63114,
          "name": null,
          "symbol": "ram_F68A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15805,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R2 unknown after memory load"
        ]
      }
    },
    {
      "address": 15809,
      "address_region": "program_or_external",
      "bytes": "15F68A90",
      "text": "MOV:G.B R0, @H'F68A",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F68A",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63114,
          "name": null,
          "symbol": "ram_F68A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15805,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15813,
      "address_region": "program_or_external",
      "bytes": "15F7310403",
      "text": "CMP:G.B #H'03, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'03, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15805,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15818,
      "address_region": "program_or_external",
      "bytes": "223C",
      "text": "BHI loc_3E08",
      "mnemonic": "BHI",
      "operands": "loc_3E08",
      "kind": "branch",
      "targets": [
        15880
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15805,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15820,
      "address_region": "program_or_external",
      "bytes": "A012",
      "text": "EXTU.B R0",
      "mnemonic": "EXTU.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15820,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15822,
      "address_region": "program_or_external",
      "bytes": "A212",
      "text": "EXTU.B R2",
      "mnemonic": "EXTU.B",
      "operands": "R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15820,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R2"
        ]
      }
    },
    {
      "address": 15824,
      "address_region": "program_or_external",
      "bytes": "0C0101A8",
      "text": "MULXU.W #H'0101, R0",
      "mnemonic": "MULXU.W",
      "operands": "#H'0101, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 25,
        "base_cycles": 25,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15820,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:MULXU.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15828,
      "address_region": "program_or_external",
      "bytes": "0C0101AA",
      "text": "MULXU.W #H'0101, R2",
      "mnemonic": "MULXU.W",
      "operands": "#H'0101, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 25,
        "base_cycles": 25,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15820,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:MULXU.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R2"
        ]
      }
    },
    {
      "address": 15832,
      "address_region": "program_or_external",
      "bytes": "AB31",
      "text": "SUB.W R3, R1",
      "mnemonic": "SUB.W",
      "operands": "R3, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15820,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R1 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 15834,
      "address_region": "program_or_external",
      "bytes": "1DE10280",
      "text": "MOV:G.W @H'E102, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'E102, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57602,
          "name": null,
          "symbol": "mem_E102",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15820,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:MULXU.W"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15838,
      "address_region": "program_or_external",
      "bytes": "A821",
      "text": "ADD:G.W R0, R1",
      "mnemonic": "ADD:G.W",
      "operands": "R0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15820,
        "changes": [],
        "notes": [
          "R1 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 15840,
      "address_region": "program_or_external",
      "bytes": "A982",
      "text": "MOV:G.W R1, R2",
      "mnemonic": "MOV:G.W",
      "operands": "R1, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15820,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "unsupported:MULXU.W"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R2 unknown after MOV source"
        ]
      }
    },
    {
      "address": 15842,
      "address_region": "program_or_external",
      "bytes": "250C",
      "text": "BCS loc_3DF0",
      "mnemonic": "BCS",
      "operands": "loc_3DF0",
      "kind": "branch",
      "targets": [
        15856
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15820,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15844,
      "address_region": "program_or_external",
      "bytes": "A832",
      "text": "SUB.W R0, R2",
      "mnemonic": "SUB.W",
      "operands": "R0, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15844,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R2 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 15846,
      "address_region": "program_or_external",
      "bytes": "4A8000",
      "text": "CMP:I #H'8000, R2",
      "mnemonic": "CMP:I",
      "operands": "#H'8000, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15844,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15849,
      "address_region": "program_or_external",
      "bytes": "230F",
      "text": "BLS loc_3DFA",
      "mnemonic": "BLS",
      "operands": "loc_3DFA",
      "kind": "branch",
      "targets": [
        15866
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15844,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15851,
      "address_region": "program_or_external",
      "bytes": "590000",
      "text": "MOV:I.W #H'0000, R1",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0000, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15851,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R1"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 = 0x0000"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R1"
            }
          }
        }
      }
    },
    {
      "address": 15854,
      "address_region": "program_or_external",
      "bytes": "200A",
      "text": "BRA loc_3DFA",
      "mnemonic": "BRA",
      "operands": "loc_3DFA",
      "kind": "jump",
      "targets": [
        15866
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15851,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R1"
            }
          }
        }
      }
    },
    {
      "address": 15856,
      "address_region": "program_or_external",
      "bytes": "AA30",
      "text": "SUB.W R2, R0",
      "mnemonic": "SUB.W",
      "operands": "R2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15856,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 15858,
      "address_region": "program_or_external",
      "bytes": "488000",
      "text": "CMP:I #H'8000, R0",
      "mnemonic": "CMP:I",
      "operands": "#H'8000, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15856,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15861,
      "address_region": "program_or_external",
      "bytes": "2303",
      "text": "BLS loc_3DFA",
      "mnemonic": "BLS",
      "operands": "loc_3DFA",
      "kind": "branch",
      "targets": [
        15866
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15856,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15863,
      "address_region": "program_or_external",
      "bytes": "59FFFF",
      "text": "MOV:I.W #H'FFFF, R1",
      "mnemonic": "MOV:I.W",
      "operands": "#H'FFFF, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15863,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 65535,
              "hex": "0xFFFF",
              "width": 16,
              "source": "MOV:I.W #H'FFFF, R1"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 = 0xFFFF"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 65535,
              "hex": "0xFFFF",
              "width": 16,
              "source": "MOV:I.W #H'FFFF, R1"
            }
          }
        }
      }
    },
    {
      "address": 15866,
      "address_region": "program_or_external",
      "bytes": "1DE10271",
      "text": "CMP:G.W @H'E102, R1",
      "mnemonic": "CMP:G.W",
      "operands": "@H'E102, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57602,
          "name": null,
          "symbol": "mem_E102",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15866,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15870,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_3E08",
      "mnemonic": "BEQ",
      "operands": "loc_3E08",
      "kind": "branch",
      "targets": [
        15880
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15866,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15872,
      "address_region": "program_or_external",
      "bytes": "1DF68E91",
      "text": "MOV:G.W R1, @H'F68E",
      "mnemonic": "MOV:G.W",
      "operands": "R1, @H'F68E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63118,
          "name": null,
          "symbol": "ram_F68E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15872,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15876,
      "address_region": "program_or_external",
      "bytes": "15F689C7",
      "text": "BSET.B #7, @H'F689",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'F689",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63113,
          "name": null,
          "symbol": "ram_F689",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15872,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15880,
      "address_region": "program_or_external",
      "bytes": "15F68B80",
      "text": "MOV:G.B @H'F68B, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F68B, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63115,
          "name": null,
          "symbol": "ram_F68B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15880,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15884,
      "address_region": "program_or_external",
      "bytes": "0414A8",
      "text": "MULXU.B #H'14, R0",
      "mnemonic": "MULXU.B",
      "operands": "#H'14, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 19,
        "base_cycles": 19,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15880,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:MULXU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15887,
      "address_region": "program_or_external",
      "bytes": "1DFEE281",
      "text": "MOV:G.W @ADDRB_H, R1",
      "mnemonic": "MOV:G.W",
      "operands": "@ADDRB_H, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65250,
          "name": "ADDRB_H",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "peripheral_access": [
        {
          "address": 15887,
          "instruction": "MOV:G.W @ADDRB_H, R1",
          "register": "ADDRB",
          "high_address": 65250,
          "low_address": 65251,
          "referenced_address": 65250,
          "referenced_address_hex": "H'FEE2",
          "byte": "high",
          "size": "W",
          "direction": "read"
        }
      ],
      "dataflow": {
        "block": 15880,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 15891,
      "address_region": "program_or_external",
      "bytes": "A110",
      "text": "SWAP.B R1",
      "mnemonic": "SWAP.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15880,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 15893,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15880,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 15895,
      "address_region": "program_or_external",
      "bytes": "A920",
      "text": "ADD:G.W R1, R0",
      "mnemonic": "ADD:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15880,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:MULXU.B"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 15897,
      "address_region": "program_or_external",
      "bytes": "0415B8",
      "text": "DIVXU.B #H'15, R0",
      "mnemonic": "DIVXU.B",
      "operands": "#H'15, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 23,
        "base_cycles": 23,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15880,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:DIVXU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15900,
      "address_region": "program_or_external",
      "bytes": "1DF68C16",
      "text": "TST.W @H'F68C",
      "mnemonic": "TST.W",
      "operands": "@H'F68C",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63116,
          "name": null,
          "symbol": "ram_F68C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15880,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15904,
      "address_region": "program_or_external",
      "bytes": "2706",
      "text": "BEQ loc_3E28",
      "mnemonic": "BEQ",
      "operands": "loc_3E28",
      "kind": "branch",
      "targets": [
        15912
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15880,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15906,
      "address_region": "program_or_external",
      "bytes": "15F68B70",
      "text": "CMP:G.B @H'F68B, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F68B, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63115,
          "name": null,
          "symbol": "ram_F68B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15906,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15910,
      "address_region": "program_or_external",
      "bytes": "2725",
      "text": "BEQ loc_3E4D",
      "mnemonic": "BEQ",
      "operands": "loc_3E4D",
      "kind": "branch",
      "targets": [
        15949
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15906,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15912,
      "address_region": "program_or_external",
      "bytes": "15F68B90",
      "text": "MOV:G.B R0, @H'F68B",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F68B",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63115,
          "name": null,
          "symbol": "ram_F68B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15916,
      "address_region": "program_or_external",
      "bytes": "A012",
      "text": "EXTU.B R0",
      "mnemonic": "EXTU.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15918,
      "address_region": "program_or_external",
      "bytes": "A883",
      "text": "MOV:G.W R0, R3",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R3 unknown after MOV source"
        ]
      }
    },
    {
      "address": 15920,
      "address_region": "program_or_external",
      "bytes": "A3AB",
      "text": "MULXU.B R3, R3",
      "mnemonic": "MULXU.B",
      "operands": "R3, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 18,
        "base_cycles": 18,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:MULXU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 15922,
      "address_region": "program_or_external",
      "bytes": "AA13",
      "text": "CLR.W R2",
      "mnemonic": "CLR.W",
      "operands": "R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R2"
            }
          }
        ],
        "notes": [
          "R2 cleared"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R2"
            }
          }
        }
      }
    },
    {
      "address": 15924,
      "address_region": "program_or_external",
      "bytes": "0C00C8BA",
      "text": "DIVXU.W #H'00C8, R2",
      "mnemonic": "DIVXU.W",
      "operands": "#H'00C8, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 29,
        "base_cycles": 29,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R2"
            },
            "after": {
              "known": false,
              "reason": "unsupported:DIVXU.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R2"
        ]
      }
    },
    {
      "address": 15928,
      "address_region": "program_or_external",
      "bytes": "0404A8",
      "text": "MULXU.B #H'04, R0",
      "mnemonic": "MULXU.B",
      "operands": "#H'04, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 19,
        "base_cycles": 19,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:MULXU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15931,
      "address_region": "program_or_external",
      "bytes": "0C00AB20",
      "text": "ADD:G.W #H'00AB, R0",
      "mnemonic": "ADD:G.W",
      "operands": "#H'00AB, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:MULXU.B"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 15935,
      "address_region": "program_or_external",
      "bytes": "AB20",
      "text": "ADD:G.W R3, R0",
      "mnemonic": "ADD:G.W",
      "operands": "R3, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 15937,
      "address_region": "program_or_external",
      "bytes": "15FE8EF4",
      "text": "BTST.B #4, @P7DR",
      "mnemonic": "BTST.B",
      "operands": "#4, @P7DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65166,
          "name": "P7DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15941,
      "address_region": "program_or_external",
      "bytes": "2602",
      "text": "BNE loc_3E49",
      "mnemonic": "BNE",
      "operands": "loc_3E49",
      "kind": "branch",
      "targets": [
        15945
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15912,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15943,
      "address_region": "program_or_external",
      "bytes": "A81B",
      "text": "SHLR.W R0",
      "mnemonic": "SHLR.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15943,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15945,
      "address_region": "program_or_external",
      "bytes": "1DF68C90",
      "text": "MOV:G.W R0, @H'F68C",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F68C",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63116,
          "name": null,
          "symbol": "ram_F68C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15945,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15949,
      "address_region": "program_or_external",
      "bytes": "023F",
      "text": "LDM.W @SP+, {R0,R1,R2,R3,R4,R5}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R1,R2,R3,R4,R5}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 30,
        "note": "6+4n, n=6",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15949,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0, R1, R2, R3, R4, R5"
        ]
      }
    },
    {
      "address": 15951,
      "address_region": "program_or_external",
      "bytes": "15FEE8D7",
      "text": "BCLR.B #7, @ADCSR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @ADCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65256,
          "name": "ADCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear ADF (bit 7) of ADCSR",
      "valid": true,
      "dataflow": {
        "block": 15949,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15955,
      "address_region": "program_or_external",
      "bytes": "0A",
      "text": "RTE",
      "mnemonic": "RTE",
      "operands": "",
      "kind": "rte",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "base_cycles": 13,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15949,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15956,
      "address_region": "program_or_external",
      "bytes": "A2F7",
      "text": "BTST.B #7, R2",
      "mnemonic": "BTST.B",
      "operands": "#7, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15956,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15958,
      "address_region": "program_or_external",
      "bytes": "2742",
      "text": "BEQ loc_3E9A",
      "mnemonic": "BEQ",
      "operands": "loc_3E9A",
      "kind": "branch",
      "targets": [
        16026
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15956,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15960,
      "address_region": "program_or_external",
      "bytes": "15F9B580",
      "text": "MOV:G.B @H'F9B5, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B5, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15960,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 15964,
      "address_region": "program_or_external",
      "bytes": "A012",
      "text": "EXTU.B R0",
      "mnemonic": "EXTU.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15960,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15966,
      "address_region": "program_or_external",
      "bytes": "A81A",
      "text": "SHLL.W R0",
      "mnemonic": "SHLL.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15960,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 15968,
      "address_region": "program_or_external",
      "bytes": "15F9B081",
      "text": "MOV:G.B @H'F9B0, R1",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63920,
          "name": null,
          "symbol": "ram_F9B0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15960,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 15972,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15960,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 15974,
      "address_region": "program_or_external",
      "bytes": "A91A",
      "text": "SHLL.W R1",
      "mnemonic": "SHLL.W",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15960,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 15976,
      "address_region": "program_or_external",
      "bytes": "A071",
      "text": "CMP:G.B R0, R1",
      "mnemonic": "CMP:G.B",
      "operands": "R0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15976,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15978,
      "address_region": "program_or_external",
      "bytes": "270A",
      "text": "BEQ loc_3E76",
      "mnemonic": "BEQ",
      "operands": "loc_3E76",
      "kind": "branch",
      "targets": [
        15990
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15976,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15980,
      "address_region": "program_or_external",
      "bytes": "F8F87073",
      "text": "CMP:G.W @(-H'0790,R0), R3",
      "mnemonic": "CMP:G.W",
      "operands": "@(-H'0790,R0), R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15980,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15984,
      "address_region": "program_or_external",
      "bytes": "2728",
      "text": "BEQ loc_3E9A",
      "mnemonic": "BEQ",
      "operands": "loc_3E9A",
      "kind": "branch",
      "targets": [
        16026
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15980,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15986,
      "address_region": "program_or_external",
      "bytes": "A009",
      "text": "ADD:Q.B #2, R0",
      "mnemonic": "ADD:Q.B",
      "operands": "#2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15986,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 15988,
      "address_region": "program_or_external",
      "bytes": "20F2",
      "text": "BRA loc_3E68",
      "mnemonic": "BRA",
      "operands": "loc_3E68",
      "kind": "jump",
      "targets": [
        15976
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15986,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15990,
      "address_region": "program_or_external",
      "bytes": "F9F87093",
      "text": "MOV:G.W R3, @(-H'0790,R1)",
      "mnemonic": "MOV:G.W",
      "operands": "R3, @(-H'0790,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15990,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 15994,
      "address_region": "program_or_external",
      "bytes": "15F9B008",
      "text": "ADD:Q.B #1, @H'F9B0",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F9B0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63920,
          "name": null,
          "symbol": "ram_F9B0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15990,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 15998,
      "address_region": "program_or_external",
      "bytes": "15F9B0D7",
      "text": "BCLR.B #7, @H'F9B0",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F9B0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63920,
          "name": null,
          "symbol": "ram_F9B0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 15990,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16002,
      "address_region": "program_or_external",
      "bytes": "15F9B080",
      "text": "MOV:G.B @H'F9B0, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63920,
          "name": null,
          "symbol": "ram_F9B0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16002,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 16006,
      "address_region": "program_or_external",
      "bytes": "A008",
      "text": "ADD:Q.B #1, R0",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16002,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16008,
      "address_region": "program_or_external",
      "bytes": "047F50",
      "text": "AND.B #H'7F, R0",
      "mnemonic": "AND.B",
      "operands": "#H'7F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16002,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 16011,
      "address_region": "program_or_external",
      "bytes": "15F9B570",
      "text": "CMP:G.B @H'F9B5, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F9B5, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16002,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16015,
      "address_region": "program_or_external",
      "bytes": "2609",
      "text": "BNE loc_3E9A",
      "mnemonic": "BNE",
      "operands": "loc_3E9A",
      "kind": "branch",
      "targets": [
        16026
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16002,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16017,
      "address_region": "program_or_external",
      "bytes": "120C",
      "text": "STM.W {R2,R3}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R2,R3}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "note": "6+3n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16017,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16019,
      "address_region": "program_or_external",
      "bytes": "1E013D",
      "text": "BSR loc_3FD3",
      "mnemonic": "BSR",
      "operands": "loc_3FD3",
      "kind": "call",
      "targets": [
        16339
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16017,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16022,
      "address_region": "program_or_external",
      "bytes": "020C",
      "text": "LDM.W @SP+, {R2,R3}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R2,R3}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "note": "6+4n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16017,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R2, R3"
        ]
      }
    },
    {
      "address": 16024,
      "address_region": "program_or_external",
      "bytes": "20E8",
      "text": "BRA loc_3E82",
      "mnemonic": "BRA",
      "operands": "loc_3E82",
      "kind": "jump",
      "targets": [
        16002
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16017,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16026,
      "address_region": "program_or_external",
      "bytes": "A2F6",
      "text": "BTST.B #6, R2",
      "mnemonic": "BTST.B",
      "operands": "#6, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16026,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16028,
      "address_region": "program_or_external",
      "bytes": "272D",
      "text": "BEQ loc_3ECB",
      "mnemonic": "BEQ",
      "operands": "loc_3ECB",
      "kind": "branch",
      "targets": [
        16075
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16026,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16030,
      "address_region": "program_or_external",
      "bytes": "15F9B980",
      "text": "MOV:G.B @H'F9B9, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B9, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63929,
          "name": null,
          "symbol": "ram_F9B9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16030,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 16034,
      "address_region": "program_or_external",
      "bytes": "A012",
      "text": "EXTU.B R0",
      "mnemonic": "EXTU.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16030,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 16036,
      "address_region": "program_or_external",
      "bytes": "A81A",
      "text": "SHLL.W R0",
      "mnemonic": "SHLL.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16030,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 16038,
      "address_region": "program_or_external",
      "bytes": "15F9B481",
      "text": "MOV:G.B @H'F9B4, R1",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B4, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63924,
          "name": null,
          "symbol": "ram_F9B4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16030,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 16042,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16030,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 16044,
      "address_region": "program_or_external",
      "bytes": "A91A",
      "text": "SHLL.W R1",
      "mnemonic": "SHLL.W",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16030,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 16046,
      "address_region": "program_or_external",
      "bytes": "A071",
      "text": "CMP:G.B R0, R1",
      "mnemonic": "CMP:G.B",
      "operands": "R0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16046,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16048,
      "address_region": "program_or_external",
      "bytes": "270D",
      "text": "BEQ loc_3EBF",
      "mnemonic": "BEQ",
      "operands": "loc_3EBF",
      "kind": "branch",
      "targets": [
        16063
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16046,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16050,
      "address_region": "program_or_external",
      "bytes": "F8F97073",
      "text": "CMP:G.W @(-H'0690,R0), R3",
      "mnemonic": "CMP:G.W",
      "operands": "@(-H'0690,R0), R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16050,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16054,
      "address_region": "program_or_external",
      "bytes": "2713",
      "text": "BEQ loc_3ECB",
      "mnemonic": "BEQ",
      "operands": "loc_3ECB",
      "kind": "branch",
      "targets": [
        16075
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16050,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16056,
      "address_region": "program_or_external",
      "bytes": "A009",
      "text": "ADD:Q.B #2, R0",
      "mnemonic": "ADD:Q.B",
      "operands": "#2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16056,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16058,
      "address_region": "program_or_external",
      "bytes": "043F50",
      "text": "AND.B #H'3F, R0",
      "mnemonic": "AND.B",
      "operands": "#H'3F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16056,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 16061,
      "address_region": "program_or_external",
      "bytes": "20EF",
      "text": "BRA loc_3EAE",
      "mnemonic": "BRA",
      "operands": "loc_3EAE",
      "kind": "jump",
      "targets": [
        16046
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16056,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16063,
      "address_region": "program_or_external",
      "bytes": "F9F97093",
      "text": "MOV:G.W R3, @(-H'0690,R1)",
      "mnemonic": "MOV:G.W",
      "operands": "R3, @(-H'0690,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16063,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16067,
      "address_region": "program_or_external",
      "bytes": "15F9B408",
      "text": "ADD:Q.B #1, @H'F9B4",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F9B4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63924,
          "name": null,
          "symbol": "ram_F9B4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16063,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16071,
      "address_region": "program_or_external",
      "bytes": "15F9B4D5",
      "text": "BCLR.B #5, @H'F9B4",
      "mnemonic": "BCLR.B",
      "operands": "#5, @H'F9B4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63924,
          "name": null,
          "symbol": "ram_F9B4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16063,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16075,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16075,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16076,
      "address_region": "program_or_external",
      "bytes": "121F",
      "text": "STM.W {R0,R1,R2,R3,R4}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R1,R2,R3,R4}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 21,
        "note": "6+3n, n=5",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16076,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16078,
      "address_region": "program_or_external",
      "bytes": "A512",
      "text": "EXTU.B R5",
      "mnemonic": "EXTU.B",
      "operands": "R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16076,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R5"
        ]
      }
    },
    {
      "address": 16080,
      "address_region": "program_or_external",
      "bytes": "4503",
      "text": "CMP:E #H'03, R5",
      "mnemonic": "CMP:E",
      "operands": "#H'03, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16076,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16082,
      "address_region": "program_or_external",
      "bytes": "2305",
      "text": "BLS loc_3ED9",
      "mnemonic": "BLS",
      "operands": "loc_3ED9",
      "kind": "branch",
      "targets": [
        16089
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16076,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16084,
      "address_region": "program_or_external",
      "bytes": "1E0069",
      "text": "BSR loc_3F40",
      "mnemonic": "BSR",
      "operands": "loc_3F40",
      "kind": "call",
      "targets": [
        16192
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16084,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16087,
      "address_region": "program_or_external",
      "bytes": "204C",
      "text": "BRA loc_3F25",
      "mnemonic": "BRA",
      "operands": "loc_3F25",
      "kind": "jump",
      "targets": [
        16165
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16084,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16089,
      "address_region": "program_or_external",
      "bytes": "A583",
      "text": "MOV:G.B R5, R3",
      "mnemonic": "MOV:G.B",
      "operands": "R5, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16089,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R3 unknown after MOV source"
        ]
      }
    },
    {
      "address": 16091,
      "address_region": "program_or_external",
      "bytes": "4500",
      "text": "CMP:E #H'00, R5",
      "mnemonic": "CMP:E",
      "operands": "#H'00, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16089,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16093,
      "address_region": "program_or_external",
      "bytes": "270A",
      "text": "BEQ loc_3EE9",
      "mnemonic": "BEQ",
      "operands": "loc_3EE9",
      "kind": "branch",
      "targets": [
        16105
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16089,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16095,
      "address_region": "program_or_external",
      "bytes": "4501",
      "text": "CMP:E #H'01, R5",
      "mnemonic": "CMP:E",
      "operands": "#H'01, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16095,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16097,
      "address_region": "program_or_external",
      "bytes": "270B",
      "text": "BEQ loc_3EEE",
      "mnemonic": "BEQ",
      "operands": "loc_3EEE",
      "kind": "branch",
      "targets": [
        16110
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16095,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16099,
      "address_region": "program_or_external",
      "bytes": "4502",
      "text": "CMP:E #H'02, R5",
      "mnemonic": "CMP:E",
      "operands": "#H'02, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16099,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16101,
      "address_region": "program_or_external",
      "bytes": "270C",
      "text": "BEQ loc_3EF3",
      "mnemonic": "BEQ",
      "operands": "loc_3EF3",
      "kind": "branch",
      "targets": [
        16115
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16099,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16103,
      "address_region": "program_or_external",
      "bytes": "200F",
      "text": "BRA loc_3EF8",
      "mnemonic": "BRA",
      "operands": "loc_3EF8",
      "kind": "jump",
      "targets": [
        16120
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16103,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16105,
      "address_region": "program_or_external",
      "bytes": "5D0080",
      "text": "MOV:I.W #H'0080, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0080, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16105,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R5"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 = 0x0080"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R5"
            }
          }
        }
      }
    },
    {
      "address": 16108,
      "address_region": "program_or_external",
      "bytes": "200D",
      "text": "BRA loc_3EFB",
      "mnemonic": "BRA",
      "operands": "loc_3EFB",
      "kind": "jump",
      "targets": [
        16123
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16105,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R5"
            }
          }
        }
      }
    },
    {
      "address": 16110,
      "address_region": "program_or_external",
      "bytes": "5D00C0",
      "text": "MOV:I.W #H'00C0, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00C0, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16110,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 192,
              "hex": "0x00C0",
              "width": 16,
              "source": "MOV:I.W #H'00C0, R5"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 = 0x00C0"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 192,
              "hex": "0x00C0",
              "width": 16,
              "source": "MOV:I.W #H'00C0, R5"
            }
          }
        }
      }
    },
    {
      "address": 16113,
      "address_region": "program_or_external",
      "bytes": "2008",
      "text": "BRA loc_3EFB",
      "mnemonic": "BRA",
      "operands": "loc_3EFB",
      "kind": "jump",
      "targets": [
        16123
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16110,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 192,
              "hex": "0x00C0",
              "width": 16,
              "source": "MOV:I.W #H'00C0, R5"
            }
          }
        }
      }
    },
    {
      "address": 16115,
      "address_region": "program_or_external",
      "bytes": "5D0090",
      "text": "MOV:I.W #H'0090, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0090, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16115,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 144,
              "hex": "0x0090",
              "width": 16,
              "source": "MOV:I.W #H'0090, R5"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 = 0x0090"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 144,
              "hex": "0x0090",
              "width": 16,
              "source": "MOV:I.W #H'0090, R5"
            }
          }
        }
      }
    },
    {
      "address": 16118,
      "address_region": "program_or_external",
      "bytes": "2003",
      "text": "BRA loc_3EFB",
      "mnemonic": "BRA",
      "operands": "loc_3EFB",
      "kind": "jump",
      "targets": [
        16123
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16115,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 144,
              "hex": "0x0090",
              "width": 16,
              "source": "MOV:I.W #H'0090, R5"
            }
          }
        }
      }
    },
    {
      "address": 16120,
      "address_region": "program_or_external",
      "bytes": "5D00D0",
      "text": "MOV:I.W #H'00D0, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00D0, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16120,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 208,
              "hex": "0x00D0",
              "width": 16,
              "source": "MOV:I.W #H'00D0, R5"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 = 0x00D0"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 208,
              "hex": "0x00D0",
              "width": 16,
              "source": "MOV:I.W #H'00D0, R5"
            }
          }
        }
      }
    },
    {
      "address": 16123,
      "address_region": "program_or_external",
      "bytes": "0410AB",
      "text": "MULXU.B #H'10, R3",
      "mnemonic": "MULXU.B",
      "operands": "#H'10, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 19,
        "base_cycles": 19,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16123,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:MULXU.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 16126,
      "address_region": "program_or_external",
      "bytes": "0CFAB023",
      "text": "ADD:G.W #H'FAB0, R3",
      "mnemonic": "ADD:G.W",
      "operands": "#H'FAB0, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16123,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:MULXU.B"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R3 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16130,
      "address_region": "program_or_external",
      "bytes": "A913",
      "text": "CLR.W R1",
      "mnemonic": "CLR.W",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16123,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R1"
            }
          }
        ],
        "notes": [
          "R1 cleared"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R1"
            }
          }
        }
      }
    },
    {
      "address": 16132,
      "address_region": "program_or_external",
      "bytes": "F1FAF082",
      "text": "MOV:G.B @(-H'0510,R1), R2",
      "mnemonic": "MOV:G.B",
      "operands": "@(-H'0510,R1), R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16132,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R2 unknown after memory load"
        ]
      }
    },
    {
      "address": 16136,
      "address_region": "program_or_external",
      "bytes": "D372",
      "text": "CMP:G.B @R3, R2",
      "mnemonic": "CMP:G.B",
      "operands": "@R3, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 5,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16132,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16138,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_3F10",
      "mnemonic": "BEQ",
      "operands": "loc_3F10",
      "kind": "branch",
      "targets": [
        16144
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16132,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16140,
      "address_region": "program_or_external",
      "bytes": "D392",
      "text": "MOV:G.B R2, @R3",
      "mnemonic": "MOV:G.B",
      "operands": "R2, @R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 5,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16140,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16142,
      "address_region": "program_or_external",
      "bytes": "0E18",
      "text": "BSR loc_3F28",
      "mnemonic": "BSR",
      "operands": "loc_3F28",
      "kind": "call",
      "targets": [
        16168
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16140,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16144,
      "address_region": "program_or_external",
      "bytes": "A108",
      "text": "ADD:Q.B #1, R1",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16144,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16146,
      "address_region": "program_or_external",
      "bytes": "A308",
      "text": "ADD:Q.B #1, R3",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16144,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R3 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16148,
      "address_region": "program_or_external",
      "bytes": "4110",
      "text": "CMP:E #H'10, R1",
      "mnemonic": "CMP:E",
      "operands": "#H'10, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16144,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16150,
      "address_region": "program_or_external",
      "bytes": "2702",
      "text": "BEQ loc_3F1A",
      "mnemonic": "BEQ",
      "operands": "loc_3F1A",
      "kind": "branch",
      "targets": [
        16154
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16144,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16152,
      "address_region": "program_or_external",
      "bytes": "20EA",
      "text": "BRA loc_3F04",
      "mnemonic": "BRA",
      "operands": "loc_3F04",
      "kind": "jump",
      "targets": [
        16132
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16152,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16154,
      "address_region": "program_or_external",
      "bytes": "1DFB000700E0",
      "text": "MOV:G.W #H'00E0, @H'FB00",
      "mnemonic": "MOV:G.W",
      "operands": "#H'00E0, @H'FB00",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64256,
          "name": null,
          "symbol": "ram_FB00",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16154,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16160,
      "address_region": "program_or_external",
      "bytes": "5C00E0",
      "text": "MOV:I.W #H'00E0, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00E0, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16154,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 224,
              "hex": "0x00E0",
              "width": 16,
              "source": "MOV:I.W #H'00E0, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x00E0"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 224,
              "hex": "0x00E0",
              "width": 16,
              "source": "MOV:I.W #H'00E0, R4"
            }
          }
        }
      }
    },
    {
      "address": 16163,
      "address_region": "program_or_external",
      "bytes": "0E1B",
      "text": "BSR loc_3F40",
      "mnemonic": "BSR",
      "operands": "loc_3F40",
      "kind": "call",
      "targets": [
        16192
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16154,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 224,
              "hex": "0x00E0",
              "width": 16,
              "source": "MOV:I.W #H'00E0, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16165,
      "address_region": "program_or_external",
      "bytes": "021F",
      "text": "LDM.W @SP+, {R0,R1,R2,R3,R4}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R1,R2,R3,R4}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 26,
        "note": "6+4n, n=5",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16165,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0, R1, R2, R3, R4"
        ]
      }
    },
    {
      "address": 16167,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16165,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16168,
      "address_region": "program_or_external",
      "bytes": "AD84",
      "text": "MOV:G.W R5, R4",
      "mnemonic": "MOV:G.W",
      "operands": "R5, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16168,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after MOV source"
        ]
      }
    },
    {
      "address": 16170,
      "address_region": "program_or_external",
      "bytes": "A124",
      "text": "ADD:G.B R1, R4",
      "mnemonic": "ADD:G.B",
      "operands": "R1, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16168,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16172,
      "address_region": "program_or_external",
      "bytes": "1DFB0074",
      "text": "CMP:G.W @H'FB00, R4",
      "mnemonic": "CMP:G.W",
      "operands": "@H'FB00, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64256,
          "name": null,
          "symbol": "ram_FB00",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16168,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16176,
      "address_region": "program_or_external",
      "bytes": "2706",
      "text": "BEQ loc_3F38",
      "mnemonic": "BEQ",
      "operands": "loc_3F38",
      "kind": "branch",
      "targets": [
        16184
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16168,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16178,
      "address_region": "program_or_external",
      "bytes": "1DFB0094",
      "text": "MOV:G.W R4, @H'FB00",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'FB00",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64256,
          "name": null,
          "symbol": "ram_FB00",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16178,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16182,
      "address_region": "program_or_external",
      "bytes": "0E08",
      "text": "BSR loc_3F40",
      "mnemonic": "BSR",
      "operands": "loc_3F40",
      "kind": "call",
      "targets": [
        16192
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16178,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16184,
      "address_region": "program_or_external",
      "bytes": "5C0200",
      "text": "MOV:I.W #H'0200, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0200, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16184,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0200"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            }
          }
        }
      }
    },
    {
      "address": 16187,
      "address_region": "program_or_external",
      "bytes": "A224",
      "text": "ADD:G.B R2, R4",
      "mnemonic": "ADD:G.B",
      "operands": "R2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16184,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 512,
              "hex": "0x0200",
              "width": 16,
              "source": "MOV:I.W #H'0200, R4"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16189,
      "address_region": "program_or_external",
      "bytes": "0E01",
      "text": "BSR loc_3F40",
      "mnemonic": "BSR",
      "operands": "loc_3F40",
      "kind": "call",
      "targets": [
        16192
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16184,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16191,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16184,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16192,
      "address_region": "program_or_external",
      "bytes": "BF98",
      "text": "STC.W SR, @-R7",
      "mnemonic": "STC.W",
      "operands": "SR, @-R7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 7,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16192,
        "changes": [
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16194,
      "address_region": "program_or_external",
      "bytes": "0C00FF58",
      "text": "ANDC.W #H'00FF, SR",
      "mnemonic": "ANDC.W",
      "operands": "#H'00FF, SR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16192,
        "changes": [
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "SR unknown after ANDC"
        ]
      }
    },
    {
      "address": 16198,
      "address_region": "program_or_external",
      "bytes": "0C060048",
      "text": "ORC.W #H'0600, SR",
      "mnemonic": "ORC.W",
      "operands": "#H'0600, SR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16192,
        "changes": [],
        "notes": [
          "SR unknown after ORC"
        ]
      }
    },
    {
      "address": 16202,
      "address_region": "program_or_external",
      "bytes": "15F2000080",
      "text": "MOVFPE.B @H'F200, R0",
      "mnemonic": "MOVFPE.B",
      "operands": "@H'F200, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "note": "E-clock peripheral transfer",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61952,
          "name": null,
          "symbol": "mem_F200",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16202,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      },
      "lcd_driver": [
        {
          "address": 16202,
          "instruction": "MOVFPE.B @H'F200, R0",
          "lcd_address": 61952,
          "lcd_name": "lcd_status_control",
          "direction": "read",
          "role": "lcd_status_read",
          "register": "R0",
          "summary": "LCD status read from E-clock H'F200"
        },
        {
          "address": 16202,
          "kind": "lcd_busy_status_read",
          "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear",
          "loop_start": 16202
        }
      ]
    },
    {
      "address": 16207,
      "address_region": "program_or_external",
      "bytes": "A0F7",
      "text": "BTST.B #7, R0",
      "mnemonic": "BTST.B",
      "operands": "#7, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16202,
        "changes": [],
        "notes": []
      },
      "lcd_driver": [
        {
          "address": 16207,
          "kind": "lcd_busy_flag_test",
          "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear",
          "loop_start": 16202
        }
      ]
    },
    {
      "address": 16209,
      "address_region": "program_or_external",
      "bytes": "26F7",
      "text": "BNE loc_3F4A",
      "mnemonic": "BNE",
      "operands": "loc_3F4A",
      "kind": "branch",
      "targets": [
        16202
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16202,
        "changes": [],
        "notes": []
      },
      "lcd_driver": [
        {
          "address": 16209,
          "kind": "lcd_busy_wait_branch",
          "summary": "LCD busy-flag poll: read H'F200, test bit 7, branch until clear",
          "loop_start": 16202
        }
      ]
    },
    {
      "address": 16211,
      "address_region": "program_or_external",
      "bytes": "ACF8",
      "text": "BTST.W #8, R4",
      "mnemonic": "BTST.W",
      "operands": "#8, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16211,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16213,
      "address_region": "program_or_external",
      "bytes": "2616",
      "text": "BNE loc_3F6D",
      "mnemonic": "BNE",
      "operands": "loc_3F6D",
      "kind": "branch",
      "targets": [
        16237
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16211,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16215,
      "address_region": "program_or_external",
      "bytes": "ACF9",
      "text": "BTST.W #9, R4",
      "mnemonic": "BTST.W",
      "operands": "#9, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16215,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16217,
      "address_region": "program_or_external",
      "bytes": "2607",
      "text": "BNE loc_3F62",
      "mnemonic": "BNE",
      "operands": "loc_3F62",
      "kind": "branch",
      "targets": [
        16226
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16215,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16219,
      "address_region": "program_or_external",
      "bytes": "15F2000094",
      "text": "MOVTPE.B R4, @H'F200",
      "mnemonic": "MOVTPE.B",
      "operands": "R4, @H'F200",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "note": "E-clock peripheral transfer",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61952,
          "name": null,
          "symbol": "mem_F200",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16219,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      },
      "lcd_driver": [
        {
          "address": 16219,
          "instruction": "MOVTPE.B R4, @H'F200",
          "lcd_address": 61952,
          "lcd_name": "lcd_status_control",
          "direction": "write",
          "role": "lcd_command_or_address_write",
          "register": "R4",
          "summary": "LCD command/address write to E-clock H'F200"
        }
      ]
    },
    {
      "address": 16224,
      "address_region": "program_or_external",
      "bytes": "2010",
      "text": "BRA loc_3F72",
      "mnemonic": "BRA",
      "operands": "loc_3F72",
      "kind": "jump",
      "targets": [
        16242
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16219,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16226,
      "address_region": "program_or_external",
      "bytes": "15F2010094",
      "text": "MOVTPE.B R4, @H'F201",
      "mnemonic": "MOVTPE.B",
      "operands": "R4, @H'F201",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "note": "E-clock peripheral transfer",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61953,
          "name": null,
          "symbol": "mem_F201",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16226,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      },
      "lcd_driver": [
        {
          "address": 16226,
          "instruction": "MOVTPE.B R4, @H'F201",
          "lcd_address": 61953,
          "lcd_name": "lcd_data",
          "direction": "write",
          "role": "lcd_data_write",
          "register": "R4",
          "summary": "LCD data write to E-clock H'F201"
        }
      ]
    },
    {
      "address": 16231,
      "address_region": "program_or_external",
      "bytes": "1DFB0008",
      "text": "ADD:Q.W #1, @H'FB00",
      "mnemonic": "ADD:Q.W",
      "operands": "#1, @H'FB00",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64256,
          "name": null,
          "symbol": "ram_FB00",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16226,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16235,
      "address_region": "program_or_external",
      "bytes": "2005",
      "text": "BRA loc_3F72",
      "mnemonic": "BRA",
      "operands": "loc_3F72",
      "kind": "jump",
      "targets": [
        16242
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16226,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16237,
      "address_region": "program_or_external",
      "bytes": "15F2010084",
      "text": "MOVFPE.B @H'F201, R4",
      "mnemonic": "MOVFPE.B",
      "operands": "@H'F201, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "note": "E-clock peripheral transfer",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 61953,
          "name": null,
          "symbol": "mem_F201",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16237,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      },
      "lcd_driver": [
        {
          "address": 16237,
          "instruction": "MOVFPE.B @H'F201, R4",
          "lcd_address": 61953,
          "lcd_name": "lcd_data",
          "direction": "read",
          "role": "lcd_data_read",
          "register": "R4",
          "summary": "LCD data read from E-clock H'F201"
        }
      ]
    },
    {
      "address": 16242,
      "address_region": "program_or_external",
      "bytes": "CF88",
      "text": "LDC.W @R7+, SR",
      "mnemonic": "LDC.W",
      "operands": "@R7+, SR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16242,
        "changes": [
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "SR unknown after memory load"
        ]
      }
    },
    {
      "address": 16244,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16242,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16246,
      "address_region": "program_or_external",
      "bytes": "582710",
      "text": "MOV:I.W #H'2710, R0",
      "mnemonic": "MOV:I.W",
      "operands": "#H'2710, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16246,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 10000,
              "hex": "0x2710",
              "width": 16,
              "source": "MOV:I.W #H'2710, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x2710"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 10000,
              "hex": "0x2710",
              "width": 16,
              "source": "MOV:I.W #H'2710, R0"
            }
          }
        }
      }
    },
    {
      "address": 16249,
      "address_region": "program_or_external",
      "bytes": "59C350",
      "text": "MOV:I.W #H'C350, R1",
      "mnemonic": "MOV:I.W",
      "operands": "#H'C350, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16246,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 50000,
              "hex": "0xC350",
              "width": 16,
              "source": "MOV:I.W #H'C350, R1"
            }
          }
        ],
        "notes": [
          "R1 = 0xC350"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 10000,
              "hex": "0x2710",
              "width": 16,
              "source": "MOV:I.W #H'2710, R0"
            },
            "R1": {
              "known": true,
              "value": 50000,
              "hex": "0xC350",
              "width": 16,
              "source": "MOV:I.W #H'C350, R1"
            }
          }
        }
      }
    },
    {
      "address": 16252,
      "address_region": "program_or_external",
      "bytes": "15FE82D7",
      "text": "BCLR.B #7, @P1DR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @P1DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65154,
          "name": "P1DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 7 of P1DR",
      "valid": true,
      "dataflow": {
        "block": 16252,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16256,
      "address_region": "program_or_external",
      "bytes": "01B8F9",
      "text": "SCB/F R0, loc_3F7C",
      "mnemonic": "SCB/F",
      "operands": "R0, loc_3F7C",
      "kind": "branch",
      "targets": [
        16252
      ],
      "cycles": {
        "false": 3,
        "count_minus_1": 4,
        "taken": 8,
        "base_taken": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16252,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16259,
      "address_region": "program_or_external",
      "bytes": "15FE82C7",
      "text": "BSET.B #7, @P1DR",
      "mnemonic": "BSET.B",
      "operands": "#7, @P1DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65154,
          "name": "P1DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 7 of P1DR",
      "valid": true,
      "dataflow": {
        "block": 16259,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16263,
      "address_region": "program_or_external",
      "bytes": "01B9F9",
      "text": "SCB/F R1, loc_3F83",
      "mnemonic": "SCB/F",
      "operands": "R1, loc_3F83",
      "kind": "branch",
      "targets": [
        16259
      ],
      "cycles": {
        "false": 3,
        "count_minus_1": 4,
        "taken": 9,
        "base_taken": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16259,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16266,
      "address_region": "program_or_external",
      "bytes": "A813",
      "text": "CLR.W R0",
      "mnemonic": "CLR.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16266,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 cleared"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R0"
            }
          }
        }
      }
    },
    {
      "address": 16268,
      "address_region": "program_or_external",
      "bytes": "F8E00013",
      "text": "CLR.W @(-H'2000,R0)",
      "mnemonic": "CLR.W",
      "operands": "@(-H'2000,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16268,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16272,
      "address_region": "program_or_external",
      "bytes": "F8E80013",
      "text": "CLR.W @(-H'1800,R0)",
      "mnemonic": "CLR.W",
      "operands": "@(-H'1800,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16268,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16276,
      "address_region": "program_or_external",
      "bytes": "F8F68013",
      "text": "CLR.W @(-H'0980,R0)",
      "mnemonic": "CLR.W",
      "operands": "@(-H'0980,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16268,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16280,
      "address_region": "program_or_external",
      "bytes": "A809",
      "text": "ADD:Q.W #2, R0",
      "mnemonic": "ADD:Q.W",
      "operands": "#2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16268,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16282,
      "address_region": "program_or_external",
      "bytes": "480800",
      "text": "CMP:I #H'0800, R0",
      "mnemonic": "CMP:I",
      "operands": "#H'0800, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16268,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16285,
      "address_region": "program_or_external",
      "bytes": "26ED",
      "text": "BNE loc_3F8C",
      "mnemonic": "BNE",
      "operands": "loc_3F8C",
      "kind": "branch",
      "targets": [
        16268
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16268,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16287,
      "address_region": "program_or_external",
      "bytes": "1E036A",
      "text": "BSR loc_430C",
      "mnemonic": "BSR",
      "operands": "loc_430C",
      "kind": "call",
      "targets": [
        17164
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16287,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16290,
      "address_region": "program_or_external",
      "bytes": "1E037F",
      "text": "BSR loc_4324",
      "mnemonic": "BSR",
      "operands": "loc_4324",
      "kind": "call",
      "targets": [
        17188
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16287,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16293,
      "address_region": "program_or_external",
      "bytes": "1E00EE",
      "text": "BSR loc_4096",
      "mnemonic": "BSR",
      "operands": "loc_4096",
      "kind": "call",
      "targets": [
        16534
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16287,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16296,
      "address_region": "program_or_external",
      "bytes": "1E0110",
      "text": "BSR loc_40BB",
      "mnemonic": "BSR",
      "operands": "loc_40BB",
      "kind": "call",
      "targets": [
        16571
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16287,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16299,
      "address_region": "program_or_external",
      "bytes": "1E0269",
      "text": "BSR loc_4217",
      "mnemonic": "BSR",
      "operands": "loc_4217",
      "kind": "call",
      "targets": [
        16919
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16287,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16302,
      "address_region": "program_or_external",
      "bytes": "1E039B",
      "text": "BSR loc_434C",
      "mnemonic": "BSR",
      "operands": "loc_434C",
      "kind": "call",
      "targets": [
        17228
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16287,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16305,
      "address_region": "program_or_external",
      "bytes": "1DFEEC075A00",
      "text": "MOV:G.W #H'5A00, @WDT_TCSR_R",
      "mnemonic": "MOV:G.W",
      "operands": "#H'5A00, @WDT_TCSR_R",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65260,
          "name": "WDT_TCSR_R",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "WDT_TCSR_R = H'5A00 (OVF=0 WT/IT=0 TME=0 CKS2=0 CKS1=0 CKS0=0; TCNT password H'5A, counter write H'00)",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16311,
      "address_region": "program_or_external",
      "bytes": "15F79413",
      "text": "CLR.B @H'F794",
      "mnemonic": "CLR.B",
      "operands": "@H'F794",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63380,
          "name": null,
          "symbol": "ram_F794",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16315,
      "address_region": "program_or_external",
      "bytes": "0E16",
      "text": "BSR loc_3FD3",
      "mnemonic": "BSR",
      "operands": "loc_3FD3",
      "kind": "call",
      "targets": [
        16339
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16317,
      "address_region": "program_or_external",
      "bytes": "1E7BEB",
      "text": "BSR loc_BBAB",
      "mnemonic": "BSR",
      "operands": "loc_BBAB",
      "kind": "call",
      "targets": [
        48043
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16320,
      "address_region": "program_or_external",
      "bytes": "0E2D",
      "text": "BSR loc_3FEF",
      "mnemonic": "BSR",
      "operands": "loc_3FEF",
      "kind": "call",
      "targets": [
        16367
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16322,
      "address_region": "program_or_external",
      "bytes": "1E0081",
      "text": "BSR loc_4046",
      "mnemonic": "BSR",
      "operands": "loc_4046",
      "kind": "call",
      "targets": [
        16454
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16325,
      "address_region": "program_or_external",
      "bytes": "1E7ED6",
      "text": "BSR loc_BE9E",
      "mnemonic": "BSR",
      "operands": "loc_BE9E",
      "kind": "call",
      "targets": [
        48798
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16328,
      "address_region": "program_or_external",
      "bytes": "1EE83B",
      "text": "BSR loc_2806",
      "mnemonic": "BSR",
      "operands": "loc_2806",
      "kind": "call",
      "targets": [
        10246
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16331,
      "address_region": "program_or_external",
      "bytes": "1EF962",
      "text": "BSR loc_3930",
      "mnemonic": "BSR",
      "operands": "loc_3930",
      "kind": "call",
      "targets": [
        14640
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16334,
      "address_region": "program_or_external",
      "bytes": "1ED60F",
      "text": "BSR loc_15E0",
      "mnemonic": "BSR",
      "operands": "loc_15E0",
      "kind": "call",
      "targets": [
        5600
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16337,
      "address_region": "program_or_external",
      "bytes": "20DE",
      "text": "BRA loc_3FB1",
      "mnemonic": "BRA",
      "operands": "loc_3FB1",
      "kind": "jump",
      "targets": [
        16305
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16305,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16339,
      "address_region": "program_or_external",
      "bytes": "15FAA216",
      "text": "TST.B @H'FAA2",
      "mnemonic": "TST.B",
      "operands": "@H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16339,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16343,
      "address_region": "program_or_external",
      "bytes": "2615",
      "text": "BNE loc_3FEE",
      "mnemonic": "BNE",
      "operands": "loc_3FEE",
      "kind": "branch",
      "targets": [
        16366
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16339,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16345,
      "address_region": "program_or_external",
      "bytes": "15FAA5F7",
      "text": "BTST.B #7, @H'FAA5",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FAA5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64165,
          "name": null,
          "symbol": "ram_FAA5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16345,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16349,
      "address_region": "program_or_external",
      "bytes": "2706",
      "text": "BEQ loc_3FE5",
      "mnemonic": "BEQ",
      "operands": "loc_3FE5",
      "kind": "branch",
      "targets": [
        16357
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16345,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16351,
      "address_region": "program_or_external",
      "bytes": "15F9C316",
      "text": "TST.B @H'F9C3",
      "mnemonic": "TST.B",
      "operands": "@H'F9C3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16351,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16355,
      "address_region": "program_or_external",
      "bytes": "2609",
      "text": "BNE loc_3FEE",
      "mnemonic": "BNE",
      "operands": "loc_3FEE",
      "kind": "branch",
      "targets": [
        16366
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16351,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16357,
      "address_region": "program_or_external",
      "bytes": "15F9C016",
      "text": "TST.B @H'F9C0",
      "mnemonic": "TST.B",
      "operands": "@H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16357,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16361,
      "address_region": "program_or_external",
      "bytes": "2603",
      "text": "BNE loc_3FEE",
      "mnemonic": "BNE",
      "operands": "loc_3FEE",
      "kind": "branch",
      "targets": [
        16366
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16357,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16363,
      "address_region": "program_or_external",
      "bytes": "1E7B04",
      "text": "BSR loc_BAF2",
      "mnemonic": "BSR",
      "operands": "loc_BAF2",
      "kind": "call",
      "targets": [
        47858
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16363,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
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            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "DP",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
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            "kind": "control",
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              "known": false,
              "reason": "block_entry"
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            "after": {
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              "reason": "call"
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          }
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        ]
      }
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      "address": 16366,
      "address_region": "program_or_external",
      "bytes": "19",
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        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
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        "block": 16366,
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      }
    },
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      "address": 16367,
      "address_region": "program_or_external",
      "bytes": "15F9C516",
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        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63941,
          "name": null,
          "symbol": "ram_F9C5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
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              "known": false,
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          }
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      "address": 16371,
      "address_region": "program_or_external",
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        "alignment_adjustment_taken": 1,
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        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
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      "valid": true,
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      }
    },
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      "address": 16373,
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      "bytes": "15F9B513",
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        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
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          "kind": "ram"
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      ],
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          }
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        "notes": []
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    },
    {
      "address": 16377,
      "address_region": "program_or_external",
      "bytes": "15F9B013",
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        "source": "manual Appendix A.4, tables A-7/A-8",
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      },
      "references": [
        {
          "address": 63920,
          "name": null,
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      ],
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        "notes": []
      }
    },
    {
      "address": 16381,
      "address_region": "program_or_external",
      "bytes": "15FAA5D7",
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        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64165,
          "name": null,
          "symbol": "ram_FAA5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
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      }
    },
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      "address_region": "program_or_external",
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      "text": "BEQ loc_400B",
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      "valid": true,
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              "reason": "call"
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          }
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      "address": 16389,
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      },
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      }
    },
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        {
          "address": 64165,
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        "assumption": "on-chip instruction fetch/operand access, no external wait states"
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        {
          "address": 63280,
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          "kind": "ram"
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      "address": 16400,
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      "references": [
        {
          "address": 63318,
          "name": null,
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          "kind": "ram"
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      ],
      "comment": "",
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    },
    {
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        "assumption": "on-chip instruction fetch/operand access, no external wait states"
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          "address": 63319,
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          "kind": "ram"
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      ],
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    },
    {
      "address": 16408,
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          "address": 63320,
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      ],
      "comment": "",
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      }
    },
    {
      "address": 16412,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63321,
          "name": null,
          "symbol": "ram_F759",
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          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
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      }
    },
    {
      "address": 16416,
      "address_region": "program_or_external",
      "bytes": "1DF73213",
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        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
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        "block": 16396,
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        "notes": []
      }
    },
    {
      "address": 16420,
      "address_region": "program_or_external",
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        "base_cycles": 8,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63324,
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          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
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        "notes": []
      }
    },
    {
      "address": 16424,
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      "bytes": "15FB0313",
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
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          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
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        "notes": []
      }
    },
    {
      "address": 16428,
      "address_region": "program_or_external",
      "bytes": "1DE04613",
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57414,
          "name": null,
          "symbol": "mem_E046",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
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        "notes": []
      }
    },
    {
      "address": 16432,
      "address_region": "program_or_external",
      "bytes": "1DF76A13",
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      "mnemonic": "CLR.W",
      "operands": "@H'F76A",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63338,
          "name": null,
          "symbol": "ram_F76A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16396,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16436,
      "address_region": "program_or_external",
      "bytes": "15F79113",
      "text": "CLR.B @H'F791",
      "mnemonic": "CLR.B",
      "operands": "@H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16396,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16440,
      "address_region": "program_or_external",
      "bytes": "15F79513",
      "text": "CLR.B @H'F795",
      "mnemonic": "CLR.B",
      "operands": "@H'F795",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63381,
          "name": null,
          "symbol": "ram_F795",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16396,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16444,
      "address_region": "program_or_external",
      "bytes": "15F76E13",
      "text": "CLR.B @H'F76E",
      "mnemonic": "CLR.B",
      "operands": "@H'F76E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63342,
          "name": null,
          "symbol": "ram_F76E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16396,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16448,
      "address_region": "program_or_external",
      "bytes": "0E33",
      "text": "BSR loc_4075",
      "mnemonic": "BSR",
      "operands": "loc_4075",
      "kind": "call",
      "targets": [
        16501
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16396,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16450,
      "address_region": "program_or_external",
      "bytes": "1E01D2",
      "text": "BSR loc_4217",
      "mnemonic": "BSR",
      "operands": "loc_4217",
      "kind": "call",
      "targets": [
        16919
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16396,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16453,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16396,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16454,
      "address_region": "program_or_external",
      "bytes": "15F9C416",
      "text": "TST.B @H'F9C4",
      "mnemonic": "TST.B",
      "operands": "@H'F9C4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63940,
          "name": null,
          "symbol": "ram_F9C4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16454,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16458,
      "address_region": "program_or_external",
      "bytes": "260C",
      "text": "BNE loc_4058",
      "mnemonic": "BNE",
      "operands": "loc_4058",
      "kind": "branch",
      "targets": [
        16472
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16454,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16460,
      "address_region": "program_or_external",
      "bytes": "15FAA5F7",
      "text": "BTST.B #7, @H'FAA5",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FAA5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64165,
          "name": null,
          "symbol": "ram_FAA5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16460,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16464,
      "address_region": "program_or_external",
      "bytes": "2707",
      "text": "BEQ loc_4059",
      "mnemonic": "BEQ",
      "operands": "loc_4059",
      "kind": "branch",
      "targets": [
        16473
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16460,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16466,
      "address_region": "program_or_external",
      "bytes": "15F9C316",
      "text": "TST.B @H'F9C3",
      "mnemonic": "TST.B",
      "operands": "@H'F9C3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16466,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16470,
      "address_region": "program_or_external",
      "bytes": "2701",
      "text": "BEQ loc_4059",
      "mnemonic": "BEQ",
      "operands": "loc_4059",
      "kind": "branch",
      "targets": [
        16473
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16466,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16472,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16472,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16473,
      "address_region": "program_or_external",
      "bytes": "15F9B082",
      "text": "MOV:G.B @H'F9B0, R2",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B0, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63920,
          "name": null,
          "symbol": "ram_F9B0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16473,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R2 unknown after memory load"
        ]
      }
    },
    {
      "address": 16477,
      "address_region": "program_or_external",
      "bytes": "A212",
      "text": "EXTU.B R2",
      "mnemonic": "EXTU.B",
      "operands": "R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16473,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R2"
        ]
      }
    },
    {
      "address": 16479,
      "address_region": "program_or_external",
      "bytes": "15F9B572",
      "text": "CMP:G.B @H'F9B5, R2",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F9B5, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16473,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16483,
      "address_region": "program_or_external",
      "bytes": "260F",
      "text": "BNE loc_4074",
      "mnemonic": "BNE",
      "operands": "loc_4074",
      "kind": "branch",
      "targets": [
        16500
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16473,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16485,
      "address_region": "program_or_external",
      "bytes": "A21A",
      "text": "SHLL.B R2",
      "mnemonic": "SHLL.B",
      "operands": "R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16485,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R2"
        ]
      }
    },
    {
      "address": 16487,
      "address_region": "program_or_external",
      "bytes": "FAF8700600",
      "text": "MOV:G.W #H'00, @(-H'0790,R2)",
      "mnemonic": "MOV:G.W",
      "operands": "#H'00, @(-H'0790,R2)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16485,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16492,
      "address_region": "program_or_external",
      "bytes": "15F9B008",
      "text": "ADD:Q.B #1, @H'F9B0",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F9B0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63920,
          "name": null,
          "symbol": "ram_F9B0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16485,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16496,
      "address_region": "program_or_external",
      "bytes": "15F9B0D7",
      "text": "BCLR.B #7, @H'F9B0",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F9B0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63920,
          "name": null,
          "symbol": "ram_F9B0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16485,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16500,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16500,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16501,
      "address_region": "program_or_external",
      "bytes": "A813",
      "text": "CLR.W R0",
      "mnemonic": "CLR.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16501,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 cleared"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R0"
            }
          }
        }
      }
    },
    {
      "address": 16503,
      "address_region": "program_or_external",
      "bytes": "F8E00013",
      "text": "CLR.W @(-H'2000,R0)",
      "mnemonic": "CLR.W",
      "operands": "@(-H'2000,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16503,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16507,
      "address_region": "program_or_external",
      "bytes": "F8E40013",
      "text": "CLR.W @(-H'1C00,R0)",
      "mnemonic": "CLR.W",
      "operands": "@(-H'1C00,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16503,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16511,
      "address_region": "program_or_external",
      "bytes": "F8E80013",
      "text": "CLR.W @(-H'1800,R0)",
      "mnemonic": "CLR.W",
      "operands": "@(-H'1800,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16503,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16515,
      "address_region": "program_or_external",
      "bytes": "480200",
      "text": "CMP:I #H'0200, R0",
      "mnemonic": "CMP:I",
      "operands": "#H'0200, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16503,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16518,
      "address_region": "program_or_external",
      "bytes": "2404",
      "text": "BCC loc_408C",
      "mnemonic": "BCC",
      "operands": "loc_408C",
      "kind": "branch",
      "targets": [
        16524
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16503,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16520,
      "address_region": "program_or_external",
      "bytes": "F8EC0013",
      "text": "CLR.W @(-H'1400,R0)",
      "mnemonic": "CLR.W",
      "operands": "@(-H'1400,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16520,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16524,
      "address_region": "program_or_external",
      "bytes": "A809",
      "text": "ADD:Q.W #2, R0",
      "mnemonic": "ADD:Q.W",
      "operands": "#2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16524,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16526,
      "address_region": "program_or_external",
      "bytes": "480400",
      "text": "CMP:I #H'0400, R0",
      "mnemonic": "CMP:I",
      "operands": "#H'0400, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16524,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16529,
      "address_region": "program_or_external",
      "bytes": "26E4",
      "text": "BNE loc_4077",
      "mnemonic": "BNE",
      "operands": "loc_4077",
      "kind": "branch",
      "targets": [
        16503
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16524,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16531,
      "address_region": "program_or_external",
      "bytes": "0E01",
      "text": "BSR loc_4096",
      "mnemonic": "BSR",
      "operands": "loc_4096",
      "kind": "call",
      "targets": [
        16534
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16531,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16533,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16531,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16534,
      "address_region": "program_or_external",
      "bytes": "1DE000070080",
      "text": "MOV:G.W #H'0080, @H'E000",
      "mnemonic": "MOV:G.W",
      "operands": "#H'0080, @H'E000",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57344,
          "name": null,
          "symbol": "mem_E000",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16534,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16540,
      "address_region": "program_or_external",
      "bytes": "1DE006078000",
      "text": "MOV:G.W #H'8000, @H'E006",
      "mnemonic": "MOV:G.W",
      "operands": "#H'8000, @H'E006",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57350,
          "name": null,
          "symbol": "mem_E006",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16534,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16546,
      "address_region": "program_or_external",
      "bytes": "1DE08007FFFF",
      "text": "MOV:G.W #H'FFFF, @H'E080",
      "mnemonic": "MOV:G.W",
      "operands": "#H'FFFF, @H'E080",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57472,
          "name": null,
          "symbol": "mem_E080",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16534,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16552,
      "address_region": "program_or_external",
      "bytes": "1DE800070080",
      "text": "MOV:G.W #H'0080, @H'E800",
      "mnemonic": "MOV:G.W",
      "operands": "#H'0080, @H'E800",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 59392,
          "name": null,
          "symbol": "mem_E800",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16534,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16558,
      "address_region": "program_or_external",
      "bytes": "1DE806078000",
      "text": "MOV:G.W #H'8000, @H'E806",
      "mnemonic": "MOV:G.W",
      "operands": "#H'8000, @H'E806",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 59398,
          "name": null,
          "symbol": "mem_E806",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16534,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16564,
      "address_region": "program_or_external",
      "bytes": "1DE88007FFFF",
      "text": "MOV:G.W #H'FFFF, @H'E880",
      "mnemonic": "MOV:G.W",
      "operands": "#H'FFFF, @H'E880",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 59520,
          "name": null,
          "symbol": "mem_E880",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16534,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16570,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16534,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16571,
      "address_region": "program_or_external",
      "bytes": "580040",
      "text": "MOV:I.W #H'0040, R0",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0040, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16571,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 64,
              "hex": "0x0040",
              "width": 16,
              "source": "MOV:I.W #H'0040, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x0040"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 64,
              "hex": "0x0040",
              "width": 16,
              "source": "MOV:I.W #H'0040, R0"
            }
          }
        }
      }
    },
    {
      "address": 16574,
      "address_region": "program_or_external",
      "bytes": "F8F86E07FFFF",
      "text": "MOV:G.W #H'FFFF, @(-H'0792,R0)",
      "mnemonic": "MOV:G.W",
      "operands": "#H'FFFF, @(-H'0792,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16574,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16580,
      "address_region": "program_or_external",
      "bytes": "F8F8AE07FFFF",
      "text": "MOV:G.W #H'FFFF, @(-H'0752,R0)",
      "mnemonic": "MOV:G.W",
      "operands": "#H'FFFF, @(-H'0752,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16574,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16586,
      "address_region": "program_or_external",
      "bytes": "F8F8EE07FFFF",
      "text": "MOV:G.W #H'FFFF, @(-H'0712,R0)",
      "mnemonic": "MOV:G.W",
      "operands": "#H'FFFF, @(-H'0712,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16574,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16592,
      "address_region": "program_or_external",
      "bytes": "F8F92E07FFFF",
      "text": "MOV:G.W #H'FFFF, @(-H'06D2,R0)",
      "mnemonic": "MOV:G.W",
      "operands": "#H'FFFF, @(-H'06D2,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16574,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16598,
      "address_region": "program_or_external",
      "bytes": "F8F96E07FFFF",
      "text": "MOV:G.W #H'FFFF, @(-H'0692,R0)",
      "mnemonic": "MOV:G.W",
      "operands": "#H'FFFF, @(-H'0692,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16574,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16604,
      "address_region": "program_or_external",
      "bytes": "A80D",
      "text": "ADD:Q.W #-2, R0",
      "mnemonic": "ADD:Q.W",
      "operands": "#-2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16574,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16606,
      "address_region": "program_or_external",
      "bytes": "26DE",
      "text": "BNE loc_40BE",
      "mnemonic": "BNE",
      "operands": "loc_40BE",
      "kind": "branch",
      "targets": [
        16574
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16574,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16608,
      "address_region": "program_or_external",
      "bytes": "15F9C40614",
      "text": "MOV:G.B #H'14, @H'F9C4",
      "mnemonic": "MOV:G.B",
      "operands": "#H'14, @H'F9C4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63940,
          "name": null,
          "symbol": "ram_F9C4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16608,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16613,
      "address_region": "program_or_external",
      "bytes": "15F6F70680",
      "text": "MOV:G.B #H'80, @H'F6F7",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F6F7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63223,
          "name": null,
          "symbol": "ram_F6F7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16608,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16618,
      "address_region": "program_or_external",
      "bytes": "15F6F80680",
      "text": "MOV:G.B #H'80, @H'F6F8",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F6F8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63224,
          "name": null,
          "symbol": "ram_F6F8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16608,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16623,
      "address_region": "program_or_external",
      "bytes": "15F6F90680",
      "text": "MOV:G.B #H'80, @H'F6F9",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F6F9",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63225,
          "name": null,
          "symbol": "ram_F6F9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16608,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16628,
      "address_region": "program_or_external",
      "bytes": "15FE8EF7",
      "text": "BTST.B #7, @P7DR",
      "mnemonic": "BTST.B",
      "operands": "#7, @P7DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65166,
          "name": "P7DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16608,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16632,
      "address_region": "program_or_external",
      "bytes": "2709",
      "text": "BEQ loc_4103",
      "mnemonic": "BEQ",
      "operands": "loc_4103",
      "kind": "branch",
      "targets": [
        16643
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16608,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16634,
      "address_region": "program_or_external",
      "bytes": "1DF402056B6F",
      "text": "CMP:G.W #H'6B6F, @H'F402",
      "mnemonic": "CMP:G.W",
      "operands": "#H'6B6F, @H'F402",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62466,
          "name": null,
          "symbol": "mem_F402",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16634,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16640,
      "address_region": "program_or_external",
      "bytes": "3700AD",
      "text": "BEQ loc_41B0",
      "mnemonic": "BEQ",
      "operands": "loc_41B0",
      "kind": "branch",
      "targets": [
        16816
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16634,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16643,
      "address_region": "program_or_external",
      "bytes": "580100",
      "text": "MOV:I.W #H'0100, R0",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0100, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16643,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 256,
              "hex": "0x0100",
              "width": 16,
              "source": "MOV:I.W #H'0100, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x0100"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 256,
              "hex": "0x0100",
              "width": 16,
              "source": "MOV:I.W #H'0100, R0"
            }
          }
        }
      }
    },
    {
      "address": 16646,
      "address_region": "program_or_external",
      "bytes": "A80D",
      "text": "ADD:Q.W #-2, R0",
      "mnemonic": "ADD:Q.W",
      "operands": "#-2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16648,
      "address_region": "program_or_external",
      "bytes": "F8C96485",
      "text": "MOV:G.W @(-H'369C,R0), R5",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'369C,R0), R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R5 unknown after memory load"
        ]
      }
    },
    {
      "address": 16652,
      "address_region": "program_or_external",
      "bytes": "F8F40095",
      "text": "MOV:G.W R5, @(-H'0C00,R0)",
      "mnemonic": "MOV:G.W",
      "operands": "R5, @(-H'0C00,R0)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16656,
      "address_region": "program_or_external",
      "bytes": "BF90",
      "text": "MOV:G.W R0, @-R7",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @-R7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 5,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16658,
      "address_region": "program_or_external",
      "bytes": "A884",
      "text": "MOV:G.W R0, R4",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R4 unknown after MOV source"
        ]
      }
    },
    {
      "address": 16660,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "addressing_side_effect"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16663,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16667,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16670,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16674,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
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      ],
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        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
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              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16677,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16681,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16684,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16688,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
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      ],
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        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16691,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
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              "known": false,
              "reason": "call"
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            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16695,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
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      ],
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        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
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              "known": false,
              "reason": "unknown_operand"
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "CCR",
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              "reason": "flags"
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            "after": {
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              "reason": "call"
            }
          }
        ],
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        ]
      }
    },
    {
      "address": 16698,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
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        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
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            "kind": "register",
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              "reason": "call"
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              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
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              "reason": "call"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16702,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
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      ],
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        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
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              "reason": "unknown_operand"
            },
            "after": {
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          },
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "flags"
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            "after": {
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              "reason": "call"
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          }
        ],
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        ]
      }
    },
    {
      "address": 16705,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
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        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "dataflow": {
        "block": 16646,
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            "kind": "register",
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              "reason": "call"
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              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
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              "reason": "call"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16709,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
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        "base_cycles": 9,
        "alignment_adjustment": 1,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "dataflow": {
        "block": 16646,
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            "kind": "register",
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              "known": false,
              "reason": "unknown_operand"
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "flags"
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              "reason": "call"
            }
          }
        ],
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      }
    },
    {
      "address": 16712,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
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      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "valid": true,
      "dataflow": {
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              "reason": "call"
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              "reason": "unknown_operand"
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          },
          {
            "kind": "control",
            "name": "CCR",
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              "reason": "call"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16716,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
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      ],
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        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
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      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
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            "kind": "register",
            "name": "R4",
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              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
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          },
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "flags"
            },
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              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16719,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
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        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
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            "kind": "register",
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              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "call"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16723,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
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        "base_cycles": 9,
        "alignment_adjustment": 1,
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        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
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      "valid": true,
      "dataflow": {
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        "changes": [
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            "kind": "register",
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              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
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              "reason": "call"
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          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
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            "after": {
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              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16726,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
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        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16730,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16733,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16737,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16740,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16744,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16747,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16751,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16754,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16758,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16761,
      "address_region": "program_or_external",
      "bytes": "0C010024",
      "text": "ADD:G.W #H'0100, R4",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16765,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16768,
      "address_region": "program_or_external",
      "bytes": "CF80",
      "text": "MOV:G.W @R7+, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@R7+, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 5,
        "base_cycles": 5,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 16770,
      "address_region": "program_or_external",
      "bytes": "2682",
      "text": "BNE loc_4106",
      "mnemonic": "BNE",
      "operands": "loc_4106",
      "kind": "branch",
      "targets": [
        16646
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16646,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16772,
      "address_region": "program_or_external",
      "bytes": "58000F",
      "text": "MOV:I.W #H'000F, R0",
      "mnemonic": "MOV:I.W",
      "operands": "#H'000F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16772,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 15,
              "hex": "0x000F",
              "width": 16,
              "source": "MOV:I.W #H'000F, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x000F"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 15,
              "hex": "0x000F",
              "width": 16,
              "source": "MOV:I.W #H'000F, R0"
            }
          }
        }
      }
    },
    {
      "address": 16775,
      "address_region": "program_or_external",
      "bytes": "BF90",
      "text": "MOV:G.W R0, @-R7",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @-R7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 5,
        "base_cycles": 5,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16777,
      "address_region": "program_or_external",
      "bytes": "A884",
      "text": "MOV:G.W R0, R4",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R4 unknown after MOV source"
        ]
      }
    },
    {
      "address": 16779,
      "address_region": "program_or_external",
      "bytes": "A410",
      "text": "SWAP.B R4",
      "mnemonic": "SWAP.B",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 16781,
      "address_region": "program_or_external",
      "bytes": "5D2020",
      "text": "MOV:I.W #H'2020, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'2020, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x2020"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            }
          }
        }
      }
    },
    {
      "address": 16784,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "addressing_side_effect"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16787,
      "address_region": "program_or_external",
      "bytes": "AC09",
      "text": "ADD:Q.W #2, R4",
      "mnemonic": "ADD:Q.W",
      "operands": "#2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16789,
      "address_region": "program_or_external",
      "bytes": "5D2020",
      "text": "MOV:I.W #H'2020, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'2020, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x2020"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            }
          }
        }
      }
    },
    {
      "address": 16792,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16795,
      "address_region": "program_or_external",
      "bytes": "AC09",
      "text": "ADD:Q.W #2, R4",
      "mnemonic": "ADD:Q.W",
      "operands": "#2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16797,
      "address_region": "program_or_external",
      "bytes": "5D2020",
      "text": "MOV:I.W #H'2020, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'2020, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x2020"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            }
          }
        }
      }
    },
    {
      "address": 16800,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16803,
      "address_region": "program_or_external",
      "bytes": "AC09",
      "text": "ADD:Q.W #2, R4",
      "mnemonic": "ADD:Q.W",
      "operands": "#2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16805,
      "address_region": "program_or_external",
      "bytes": "5D2020",
      "text": "MOV:I.W #H'2020, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'2020, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x2020"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            }
          }
        }
      }
    },
    {
      "address": 16808,
      "address_region": "program_or_external",
      "bytes": "18BFE0",
      "text": "JSR @loc_BFE0",
      "mnemonic": "JSR",
      "operands": "@loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 8224,
              "hex": "0x2020",
              "width": 16,
              "source": "MOV:I.W #H'2020, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16811,
      "address_region": "program_or_external",
      "bytes": "CF80",
      "text": "MOV:G.W @R7+, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@R7+, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 5,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 16813,
      "address_region": "program_or_external",
      "bytes": "01B8D7",
      "text": "SCB/F R0, loc_4187",
      "mnemonic": "SCB/F",
      "operands": "R0, loc_4187",
      "kind": "branch",
      "targets": [
        16775
      ],
      "cycles": {
        "false": 3,
        "count_minus_1": 4,
        "taken": 9,
        "base_taken": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16775,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16816,
      "address_region": "program_or_external",
      "bytes": "2020",
      "text": "BRA loc_41D2",
      "mnemonic": "BRA",
      "operands": "loc_41D2",
      "kind": "jump",
      "targets": [
        16850
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16816,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16850,
      "address_region": "program_or_external",
      "bytes": "58000F",
      "text": "MOV:I.W #H'000F, R0",
      "mnemonic": "MOV:I.W",
      "operands": "#H'000F, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16850,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 15,
              "hex": "0x000F",
              "width": 16,
              "source": "MOV:I.W #H'000F, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x000F"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 15,
              "hex": "0x000F",
              "width": 16,
              "source": "MOV:I.W #H'000F, R0"
            }
          }
        }
      }
    },
    {
      "address": 16853,
      "address_region": "program_or_external",
      "bytes": "A881",
      "text": "MOV:G.W R0, R1",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after MOV source"
        ]
      }
    },
    {
      "address": 16855,
      "address_region": "program_or_external",
      "bytes": "A11A",
      "text": "SHLL.B R1",
      "mnemonic": "SHLL.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 16857,
      "address_region": "program_or_external",
      "bytes": "A11A",
      "text": "SHLL.B R1",
      "mnemonic": "SHLL.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 16859,
      "address_region": "program_or_external",
      "bytes": "A11A",
      "text": "SHLL.B R1",
      "mnemonic": "SHLL.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 16861,
      "address_region": "program_or_external",
      "bytes": "A884",
      "text": "MOV:G.W R0, R4",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R4 unknown after MOV source"
        ]
      }
    },
    {
      "address": 16863,
      "address_region": "program_or_external",
      "bytes": "A410",
      "text": "SWAP.B R4",
      "mnemonic": "SWAP.B",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 16865,
      "address_region": "program_or_external",
      "bytes": "1203",
      "text": "STM.W {R0,R1}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R1}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "note": "6+3n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16867,
      "address_region": "program_or_external",
      "bytes": "18BFFE",
      "text": "JSR @loc_BFFE",
      "mnemonic": "JSR",
      "operands": "@loc_BFFE",
      "kind": "call",
      "targets": [
        49150
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16870,
      "address_region": "program_or_external",
      "bytes": "0203",
      "text": "LDM.W @SP+, {R0,R1}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R1}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "note": "6+4n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0, R1"
        ]
      }
    },
    {
      "address": 16872,
      "address_region": "program_or_external",
      "bytes": "F9F7B095",
      "text": "MOV:G.W R5, @(-H'0850,R1)",
      "mnemonic": "MOV:G.W",
      "operands": "R5, @(-H'0850,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16876,
      "address_region": "program_or_external",
      "bytes": "AC09",
      "text": "ADD:Q.W #2, R4",
      "mnemonic": "ADD:Q.W",
      "operands": "#2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16878,
      "address_region": "program_or_external",
      "bytes": "1203",
      "text": "STM.W {R0,R1}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R1}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "note": "6+3n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16880,
      "address_region": "program_or_external",
      "bytes": "18BFFE",
      "text": "JSR @loc_BFFE",
      "mnemonic": "JSR",
      "operands": "@loc_BFFE",
      "kind": "call",
      "targets": [
        49150
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:LDM.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:LDM.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16883,
      "address_region": "program_or_external",
      "bytes": "0203",
      "text": "LDM.W @SP+, {R0,R1}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R1}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "note": "6+4n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0, R1"
        ]
      }
    },
    {
      "address": 16885,
      "address_region": "program_or_external",
      "bytes": "F9F7B295",
      "text": "MOV:G.W R5, @(-H'084E,R1)",
      "mnemonic": "MOV:G.W",
      "operands": "R5, @(-H'084E,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16889,
      "address_region": "program_or_external",
      "bytes": "AC09",
      "text": "ADD:Q.W #2, R4",
      "mnemonic": "ADD:Q.W",
      "operands": "#2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16891,
      "address_region": "program_or_external",
      "bytes": "1203",
      "text": "STM.W {R0,R1}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R1}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "note": "6+3n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16893,
      "address_region": "program_or_external",
      "bytes": "18BFFE",
      "text": "JSR @loc_BFFE",
      "mnemonic": "JSR",
      "operands": "@loc_BFFE",
      "kind": "call",
      "targets": [
        49150
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:LDM.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:LDM.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16896,
      "address_region": "program_or_external",
      "bytes": "0203",
      "text": "LDM.W @SP+, {R0,R1}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R1}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "note": "6+4n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0, R1"
        ]
      }
    },
    {
      "address": 16898,
      "address_region": "program_or_external",
      "bytes": "F9F7B495",
      "text": "MOV:G.W R5, @(-H'084C,R1)",
      "mnemonic": "MOV:G.W",
      "operands": "R5, @(-H'084C,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16902,
      "address_region": "program_or_external",
      "bytes": "AC09",
      "text": "ADD:Q.W #2, R4",
      "mnemonic": "ADD:Q.W",
      "operands": "#2, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 16904,
      "address_region": "program_or_external",
      "bytes": "1203",
      "text": "STM.W {R0,R1}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R1}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "note": "6+3n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16906,
      "address_region": "program_or_external",
      "bytes": "18BFFE",
      "text": "JSR @loc_BFFE",
      "mnemonic": "JSR",
      "operands": "@loc_BFFE",
      "kind": "call",
      "targets": [
        49150
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:LDM.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:LDM.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 16909,
      "address_region": "program_or_external",
      "bytes": "0203",
      "text": "LDM.W @SP+, {R0,R1}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R1}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "note": "6+4n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0, R1"
        ]
      }
    },
    {
      "address": 16911,
      "address_region": "program_or_external",
      "bytes": "F9F7B695",
      "text": "MOV:G.W R5, @(-H'084A,R1)",
      "mnemonic": "MOV:G.W",
      "operands": "R5, @(-H'084A,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16915,
      "address_region": "program_or_external",
      "bytes": "01B8BF",
      "text": "SCB/F R0, loc_41D5",
      "mnemonic": "SCB/F",
      "operands": "R0, loc_41D5",
      "kind": "branch",
      "targets": [
        16853
      ],
      "cycles": {
        "false": 3,
        "count_minus_1": 4,
        "taken": 9,
        "base_taken": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16853,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16918,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16918,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16919,
      "address_region": "program_or_external",
      "bytes": "15F79813",
      "text": "CLR.B @H'F798",
      "mnemonic": "CLR.B",
      "operands": "@H'F798",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63384,
          "name": null,
          "symbol": "ram_F798",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 16923,
      "address_region": "program_or_external",
      "bytes": "15F731C7",
      "text": "BSET.B #7, @H'F731",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16927,
      "address_region": "program_or_external",
      "bytes": "15FE82D2",
      "text": "BCLR.B #2, @P1DR",
      "mnemonic": "BCLR.B",
      "operands": "#2, @P1DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65154,
          "name": "P1DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 2 of P1DR",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16931,
      "address_region": "program_or_external",
      "bytes": "1DF700072424",
      "text": "MOV:G.W #H'2424, @H'F700",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2424, @H'F700",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63232,
          "name": null,
          "symbol": "ram_F700",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16937,
      "address_region": "program_or_external",
      "bytes": "1DF702072424",
      "text": "MOV:G.W #H'2424, @H'F702",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2424, @H'F702",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63234,
          "name": null,
          "symbol": "ram_F702",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16943,
      "address_region": "program_or_external",
      "bytes": "1DF704072424",
      "text": "MOV:G.W #H'2424, @H'F704",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2424, @H'F704",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63236,
          "name": null,
          "symbol": "ram_F704",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16949,
      "address_region": "program_or_external",
      "bytes": "1DF706072424",
      "text": "MOV:G.W #H'2424, @H'F706",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2424, @H'F706",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63238,
          "name": null,
          "symbol": "ram_F706",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16955,
      "address_region": "program_or_external",
      "bytes": "15F708067F",
      "text": "MOV:G.B #H'7F, @H'F708",
      "mnemonic": "MOV:G.B",
      "operands": "#H'7F, @H'F708",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63240,
          "name": null,
          "symbol": "ram_F708",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16960,
      "address_region": "program_or_external",
      "bytes": "15F7090624",
      "text": "MOV:G.B #H'24, @H'F709",
      "mnemonic": "MOV:G.B",
      "operands": "#H'24, @H'F709",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63241,
          "name": null,
          "symbol": "ram_F709",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16965,
      "address_region": "program_or_external",
      "bytes": "1DF70A072424",
      "text": "MOV:G.W #H'2424, @H'F70A",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2424, @H'F70A",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63242,
          "name": null,
          "symbol": "ram_F70A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16971,
      "address_region": "program_or_external",
      "bytes": "15F71013",
      "text": "CLR.B @H'F710",
      "mnemonic": "CLR.B",
      "operands": "@H'F710",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63248,
          "name": null,
          "symbol": "ram_F710",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16975,
      "address_region": "program_or_external",
      "bytes": "15F71113",
      "text": "CLR.B @H'F711",
      "mnemonic": "CLR.B",
      "operands": "@H'F711",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63249,
          "name": null,
          "symbol": "ram_F711",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16979,
      "address_region": "program_or_external",
      "bytes": "15F71213",
      "text": "CLR.B @H'F712",
      "mnemonic": "CLR.B",
      "operands": "@H'F712",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63250,
          "name": null,
          "symbol": "ram_F712",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16983,
      "address_region": "program_or_external",
      "bytes": "15F71313",
      "text": "CLR.B @H'F713",
      "mnemonic": "CLR.B",
      "operands": "@H'F713",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63251,
          "name": null,
          "symbol": "ram_F713",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16987,
      "address_region": "program_or_external",
      "bytes": "15F71413",
      "text": "CLR.B @H'F714",
      "mnemonic": "CLR.B",
      "operands": "@H'F714",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63252,
          "name": null,
          "symbol": "ram_F714",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16991,
      "address_region": "program_or_external",
      "bytes": "15F71513",
      "text": "CLR.B @H'F715",
      "mnemonic": "CLR.B",
      "operands": "@H'F715",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63253,
          "name": null,
          "symbol": "ram_F715",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16995,
      "address_region": "program_or_external",
      "bytes": "15F71613",
      "text": "CLR.B @H'F716",
      "mnemonic": "CLR.B",
      "operands": "@H'F716",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63254,
          "name": null,
          "symbol": "ram_F716",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 16999,
      "address_region": "program_or_external",
      "bytes": "15F71713",
      "text": "CLR.B @H'F717",
      "mnemonic": "CLR.B",
      "operands": "@H'F717",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63255,
          "name": null,
          "symbol": "ram_F717",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17003,
      "address_region": "program_or_external",
      "bytes": "15F71806FF",
      "text": "MOV:G.B #H'FF, @H'F718",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @H'F718",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63256,
          "name": null,
          "symbol": "ram_F718",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17008,
      "address_region": "program_or_external",
      "bytes": "15F71906FF",
      "text": "MOV:G.B #H'FF, @H'F719",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @H'F719",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63257,
          "name": null,
          "symbol": "ram_F719",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17013,
      "address_region": "program_or_external",
      "bytes": "15F71A06FF",
      "text": "MOV:G.B #H'FF, @H'F71A",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @H'F71A",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63258,
          "name": null,
          "symbol": "ram_F71A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17018,
      "address_region": "program_or_external",
      "bytes": "15F71B06FF",
      "text": "MOV:G.B #H'FF, @H'F71B",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @H'F71B",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63259,
          "name": null,
          "symbol": "ram_F71B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17023,
      "address_region": "program_or_external",
      "bytes": "15F71C06FF",
      "text": "MOV:G.B #H'FF, @H'F71C",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @H'F71C",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63260,
          "name": null,
          "symbol": "ram_F71C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17028,
      "address_region": "program_or_external",
      "bytes": "15F71D06FF",
      "text": "MOV:G.B #H'FF, @H'F71D",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @H'F71D",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63261,
          "name": null,
          "symbol": "ram_F71D",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17033,
      "address_region": "program_or_external",
      "bytes": "15F71E06FF",
      "text": "MOV:G.B #H'FF, @H'F71E",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @H'F71E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63262,
          "name": null,
          "symbol": "ram_F71E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17038,
      "address_region": "program_or_external",
      "bytes": "15F71F06FF",
      "text": "MOV:G.B #H'FF, @H'F71F",
      "mnemonic": "MOV:G.B",
      "operands": "#H'FF, @H'F71F",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63263,
          "name": null,
          "symbol": "ram_F71F",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17043,
      "address_region": "program_or_external",
      "bytes": "1DFAF0072043",
      "text": "MOV:G.W #H'2043, @H'FAF0",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2043, @H'FAF0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64240,
          "name": null,
          "symbol": "ram_FAF0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17049,
      "address_region": "program_or_external",
      "bytes": "1DFAF2074F4E",
      "text": "MOV:G.W #H'4F4E, @H'FAF2",
      "mnemonic": "MOV:G.W",
      "operands": "#H'4F4E, @H'FAF2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64242,
          "name": null,
          "symbol": "ram_FAF2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17055,
      "address_region": "program_or_external",
      "bytes": "1DFAF4074E45",
      "text": "MOV:G.W #H'4E45, @H'FAF4",
      "mnemonic": "MOV:G.W",
      "operands": "#H'4E45, @H'FAF4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64244,
          "name": null,
          "symbol": "ram_FAF4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17061,
      "address_region": "program_or_external",
      "bytes": "1DFAF6074354",
      "text": "MOV:G.W #H'4354, @H'FAF6",
      "mnemonic": "MOV:G.W",
      "operands": "#H'4354, @H'FAF6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64246,
          "name": null,
          "symbol": "ram_FAF6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17067,
      "address_region": "program_or_external",
      "bytes": "1DFAF8073A4E",
      "text": "MOV:G.W #H'3A4E, @H'FAF8",
      "mnemonic": "MOV:G.W",
      "operands": "#H'3A4E, @H'FAF8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64248,
          "name": null,
          "symbol": "ram_FAF8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17073,
      "address_region": "program_or_external",
      "bytes": "1DFAFA074F54",
      "text": "MOV:G.W #H'4F54, @H'FAFA",
      "mnemonic": "MOV:G.W",
      "operands": "#H'4F54, @H'FAFA",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64250,
          "name": null,
          "symbol": "ram_FAFA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17079,
      "address_region": "program_or_external",
      "bytes": "1DFAFC072041",
      "text": "MOV:G.W #H'2041, @H'FAFC",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2041, @H'FAFC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64252,
          "name": null,
          "symbol": "ram_FAFC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17085,
      "address_region": "program_or_external",
      "bytes": "1DFAFE074354",
      "text": "MOV:G.W #H'4354, @H'FAFE",
      "mnemonic": "MOV:G.W",
      "operands": "#H'4354, @H'FAFE",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64254,
          "name": null,
          "symbol": "ram_FAFE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17091,
      "address_region": "program_or_external",
      "bytes": "5D0000",
      "text": "MOV:I.W #H'0000, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0000, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0000"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R5"
            }
          }
        }
      }
    },
    {
      "address": 17094,
      "address_region": "program_or_external",
      "bytes": "1EFC03",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17097,
      "address_region": "program_or_external",
      "bytes": "1DFAF0072020",
      "text": "MOV:G.W #H'2020, @H'FAF0",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2020, @H'FAF0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64240,
          "name": null,
          "symbol": "ram_FAF0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17103,
      "address_region": "program_or_external",
      "bytes": "1DFAF2072020",
      "text": "MOV:G.W #H'2020, @H'FAF2",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2020, @H'FAF2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64242,
          "name": null,
          "symbol": "ram_FAF2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17109,
      "address_region": "program_or_external",
      "bytes": "1DFAF4072020",
      "text": "MOV:G.W #H'2020, @H'FAF4",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2020, @H'FAF4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64244,
          "name": null,
          "symbol": "ram_FAF4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17115,
      "address_region": "program_or_external",
      "bytes": "1DFAF6072020",
      "text": "MOV:G.W #H'2020, @H'FAF6",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2020, @H'FAF6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64246,
          "name": null,
          "symbol": "ram_FAF6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17121,
      "address_region": "program_or_external",
      "bytes": "1DFAF8072020",
      "text": "MOV:G.W #H'2020, @H'FAF8",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2020, @H'FAF8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64248,
          "name": null,
          "symbol": "ram_FAF8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17127,
      "address_region": "program_or_external",
      "bytes": "1DFAFA072020",
      "text": "MOV:G.W #H'2020, @H'FAFA",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2020, @H'FAFA",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64250,
          "name": null,
          "symbol": "ram_FAFA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17133,
      "address_region": "program_or_external",
      "bytes": "1DFAFC072020",
      "text": "MOV:G.W #H'2020, @H'FAFC",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2020, @H'FAFC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64252,
          "name": null,
          "symbol": "ram_FAFC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17139,
      "address_region": "program_or_external",
      "bytes": "1DFAFE072020",
      "text": "MOV:G.W #H'2020, @H'FAFE",
      "mnemonic": "MOV:G.W",
      "operands": "#H'2020, @H'FAFE",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64254,
          "name": null,
          "symbol": "ram_FAFE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17145,
      "address_region": "program_or_external",
      "bytes": "5D0001",
      "text": "MOV:I.W #H'0001, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0001, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0001"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R5"
            }
          }
        }
      }
    },
    {
      "address": 17148,
      "address_region": "program_or_external",
      "bytes": "1EFBCD",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17151,
      "address_region": "program_or_external",
      "bytes": "5D0002",
      "text": "MOV:I.W #H'0002, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0002, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R5"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 = 0x0002"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R5"
            }
          }
        }
      }
    },
    {
      "address": 17154,
      "address_region": "program_or_external",
      "bytes": "1EFBC7",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17157,
      "address_region": "program_or_external",
      "bytes": "5D0003",
      "text": "MOV:I.W #H'0003, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0003, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 3,
              "hex": "0x0003",
              "width": 16,
              "source": "MOV:I.W #H'0003, R5"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 = 0x0003"
        ],
        "known_after": {
          "registers": {
            "R5": {
              "known": true,
              "value": 3,
              "hex": "0x0003",
              "width": 16,
              "source": "MOV:I.W #H'0003, R5"
            }
          }
        }
      }
    },
    {
      "address": 17160,
      "address_region": "program_or_external",
      "bytes": "1EFBC1",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 3,
              "hex": "0x0003",
              "width": 16,
              "source": "MOV:I.W #H'0003, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17163,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 16919,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17164,
      "address_region": "program_or_external",
      "bytes": "15FE8BD0",
      "text": "BCLR.B #0, @P6DR",
      "mnemonic": "BCLR.B",
      "operands": "#0, @P6DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65163,
          "name": "P6DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 0 of P6DR",
      "valid": true,
      "dataflow": {
        "block": 17164,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17168,
      "address_region": "program_or_external",
      "bytes": "15F55506AA",
      "text": "MOV:G.B #H'AA, @H'F555",
      "mnemonic": "MOV:G.B",
      "operands": "#H'AA, @H'F555",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62805,
          "name": null,
          "symbol": "mem_F555",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17164,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17173,
      "address_region": "program_or_external",
      "bytes": "15F4AA0655",
      "text": "MOV:G.B #H'55, @H'F4AA",
      "mnemonic": "MOV:G.B",
      "operands": "#H'55, @H'F4AA",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62634,
          "name": null,
          "symbol": "mem_F4AA",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17164,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17178,
      "address_region": "program_or_external",
      "bytes": "15F55506CC",
      "text": "MOV:G.B #H'CC, @H'F555",
      "mnemonic": "MOV:G.B",
      "operands": "#H'CC, @H'F555",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 62805,
          "name": null,
          "symbol": "mem_F555",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17164,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17183,
      "address_region": "program_or_external",
      "bytes": "15FE8BC0",
      "text": "BSET.B #0, @P6DR",
      "mnemonic": "BSET.B",
      "operands": "#0, @P6DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65163,
          "name": "P6DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 0 of P6DR",
      "valid": true,
      "dataflow": {
        "block": 17164,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17187,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17164,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17188,
      "address_region": "program_or_external",
      "bytes": "5C0038",
      "text": "MOV:I.W #H'0038, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0038, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 56,
              "hex": "0x0038",
              "width": 16,
              "source": "MOV:I.W #H'0038, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0038"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 56,
              "hex": "0x0038",
              "width": 16,
              "source": "MOV:I.W #H'0038, R4"
            }
          }
        }
      }
    },
    {
      "address": 17191,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 56,
              "hex": "0x0038",
              "width": 16,
              "source": "MOV:I.W #H'0038, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 17194,
      "address_region": "program_or_external",
      "bytes": "1EFB9F",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 56,
              "hex": "0x0038",
              "width": 16,
              "source": "MOV:I.W #H'0038, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17197,
      "address_region": "program_or_external",
      "bytes": "5C0001",
      "text": "MOV:I.W #H'0001, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0001, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0001"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            }
          }
        }
      }
    },
    {
      "address": 17200,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 17203,
      "address_region": "program_or_external",
      "bytes": "1EFB96",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17206,
      "address_region": "program_or_external",
      "bytes": "5C000E",
      "text": "MOV:I.W #H'000E, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'000E, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 14,
              "hex": "0x000E",
              "width": 16,
              "source": "MOV:I.W #H'000E, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x000E"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 14,
              "hex": "0x000E",
              "width": 16,
              "source": "MOV:I.W #H'000E, R4"
            }
          }
        }
      }
    },
    {
      "address": 17209,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 14,
              "hex": "0x000E",
              "width": 16,
              "source": "MOV:I.W #H'000E, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 17212,
      "address_region": "program_or_external",
      "bytes": "1EFB8D",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 14,
              "hex": "0x000E",
              "width": 16,
              "source": "MOV:I.W #H'000E, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17215,
      "address_region": "program_or_external",
      "bytes": "5C0006",
      "text": "MOV:I.W #H'0006, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0006, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 6,
              "hex": "0x0006",
              "width": 16,
              "source": "MOV:I.W #H'0006, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0006"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 6,
              "hex": "0x0006",
              "width": 16,
              "source": "MOV:I.W #H'0006, R4"
            }
          }
        }
      }
    },
    {
      "address": 17218,
      "address_region": "program_or_external",
      "bytes": "5D0004",
      "text": "MOV:I.W #H'0004, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0004, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x0004"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 6,
              "hex": "0x0006",
              "width": 16,
              "source": "MOV:I.W #H'0006, R4"
            },
            "R5": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            }
          }
        }
      }
    },
    {
      "address": 17221,
      "address_region": "program_or_external",
      "bytes": "1EFB84",
      "text": "BSR loc_3ECC",
      "mnemonic": "BSR",
      "operands": "loc_3ECC",
      "kind": "call",
      "targets": [
        16076
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": true,
              "value": 6,
              "hex": "0x0006",
              "width": 16,
              "source": "MOV:I.W #H'0006, R4"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": true,
              "value": 4,
              "hex": "0x0004",
              "width": 16,
              "source": "MOV:I.W #H'0004, R5"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17224,
      "address_region": "program_or_external",
      "bytes": "1ECD83",
      "text": "BSR loc_10CE",
      "mnemonic": "BSR",
      "operands": "loc_10CE",
      "kind": "call",
      "targets": [
        4302
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17227,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17188,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17228,
      "address_region": "program_or_external",
      "bytes": "15FF000670",
      "text": "MOV:G.B #H'70, @IPRA",
      "mnemonic": "MOV:G.B",
      "operands": "#H'70, @IPRA",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65280,
          "name": "IPRA",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "IPRA = H'70 (irq0 priority=7; irq1 priority=0)",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17233,
      "address_region": "program_or_external",
      "bytes": "15FF010644",
      "text": "MOV:G.B #H'44, @IPRB",
      "mnemonic": "MOV:G.B",
      "operands": "#H'44, @IPRB",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65281,
          "name": "IPRB",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "IPRB = H'44 (irq2/irq3 priority=4; irq4/irq5 priority=4)",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17238,
      "address_region": "program_or_external",
      "bytes": "15FF020666",
      "text": "MOV:G.B #H'66, @IPRC",
      "mnemonic": "MOV:G.B",
      "operands": "#H'66, @IPRC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65282,
          "name": "IPRC",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "IPRC = H'66 (FRT1 priority=6; FRT2 priority=6)",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17243,
      "address_region": "program_or_external",
      "bytes": "15FF030600",
      "text": "MOV:G.B #H'00, @IPRD",
      "mnemonic": "MOV:G.B",
      "operands": "#H'00, @IPRD",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65283,
          "name": "IPRD",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "IPRD = H'00 (FRT3 priority=0; 8-bit timer priority=0)",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17248,
      "address_region": "program_or_external",
      "bytes": "15FF040650",
      "text": "MOV:G.B #H'50, @IPRE",
      "mnemonic": "MOV:G.B",
      "operands": "#H'50, @IPRE",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65284,
          "name": "IPRE",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "IPRE = H'50 (SCI1 priority=5; SCI2 priority=0)",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17253,
      "address_region": "program_or_external",
      "bytes": "15FF050640",
      "text": "MOV:G.B #H'40, @IPRF",
      "mnemonic": "MOV:G.B",
      "operands": "#H'40, @IPRF",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65285,
          "name": "IPRF",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "IPRF = H'40 (A/D priority=4)",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17258,
      "address_region": "program_or_external",
      "bytes": "15FEDAC6",
      "text": "BSET.B #6, @SCI1_SCR",
      "mnemonic": "BSET.B",
      "operands": "#6, @SCI1_SCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65242,
          "name": "SCI1_SCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set RIE (bit 6) of SCI1_SCR",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 17258,
            "instruction": "BSET.B #6, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "BSET",
            "value": 124,
            "value_hex": "H'7C"
          }
        ]
      },
      "sci_protocol": [
        {
          "address": 17258,
          "instruction": "BSET.B #6, @SCI1_SCR",
          "action": "enable_rx_eri_interrupts",
          "channel": "SCI1",
          "register": "SCR",
          "register_address": 65242,
          "register_address_hex": "H'FEDA",
          "comment": "enable SCI1 receive and receive-error interrupts (RIE)",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 6,
          "bit_name": "RIE",
          "enabled": true,
          "interrupt_source": "RXI and ERI"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 17258,
            "instruction": "BSET.B #6, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 124,
            "value_hex": "H'7C",
            "scr": {
              "value": 124,
              "value_hex": "H'7C",
              "tie": false,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17262,
      "address_region": "program_or_external",
      "bytes": "15FE90C5",
      "text": "BSET.B #5, @FRT1_TCR",
      "mnemonic": "BSET.B",
      "operands": "#5, @FRT1_TCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65168,
          "name": "FRT1_TCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set OCIEA (bit 5) of FRT1_TCR",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17266,
      "address_region": "program_or_external",
      "bytes": "15FEA0C5",
      "text": "BSET.B #5, @FRT2_TCR",
      "mnemonic": "BSET.B",
      "operands": "#5, @FRT2_TCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65184,
          "name": "FRT2_TCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set OCIEA (bit 5) of FRT2_TCR",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17270,
      "address_region": "program_or_external",
      "bytes": "15FEE8C6",
      "text": "BSET.B #6, @ADCSR",
      "mnemonic": "BSET.B",
      "operands": "#6, @ADCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65256,
          "name": "ADCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set ADIE (bit 6) of ADCSR",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17274,
      "address_region": "program_or_external",
      "bytes": "15FEFDC4",
      "text": "BSET.B #4, @SYSCR2",
      "mnemonic": "BSET.B",
      "operands": "#4, @SYSCR2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65277,
          "name": "SYSCR2",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set IRQ3E (bit 4) of SYSCR2",
      "valid": true,
      "board_profile": {
        "accesses": [
          {
            "address": 17274,
            "instruction": "BSET.B #4, @SYSCR2",
            "register": "SYSCR2",
            "register_address": 65277,
            "access": "write",
            "p9sci2e": false,
            "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96",
            "value": 148,
            "value_hex": "H'94"
          }
        ],
        "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96"
      },
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17278,
      "address_region": "program_or_external",
      "bytes": "15FEFDC5",
      "text": "BSET.B #5, @SYSCR2",
      "mnemonic": "BSET.B",
      "operands": "#5, @SYSCR2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65277,
          "name": "SYSCR2",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set IRQ4E (bit 5) of SYSCR2",
      "valid": true,
      "board_profile": {
        "accesses": [
          {
            "address": 17278,
            "instruction": "BSET.B #5, @SYSCR2",
            "register": "SYSCR2",
            "register_address": 65277,
            "access": "write",
            "p9sci2e": false,
            "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96",
            "value": 180,
            "value_hex": "H'B4"
          }
        ],
        "comment": "SYSCR2 write leaves P9SCI2E=0; SCI2 pins are disabled, so SCI2 is not the traced MAX202 path; traced RS232/MAX202 remains SCI1 P95/P96"
      },
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17282,
      "address_region": "program_or_external",
      "bytes": "15FE8EF6",
      "text": "BTST.B #6, @P7DR",
      "mnemonic": "BTST.B",
      "operands": "#6, @P7DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65166,
          "name": "P7DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17286,
      "address_region": "program_or_external",
      "bytes": "2706",
      "text": "BEQ loc_438E",
      "mnemonic": "BEQ",
      "operands": "loc_438E",
      "kind": "branch",
      "targets": [
        17294
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17228,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17288,
      "address_region": "program_or_external",
      "bytes": "1DFEEC07A53F",
      "text": "MOV:G.W #H'A53F, @WDT_TCSR_R",
      "mnemonic": "MOV:G.W",
      "operands": "#H'A53F, @WDT_TCSR_R",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65260,
          "name": "WDT_TCSR_R",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)",
      "valid": true,
      "dataflow": {
        "block": 17288,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17294,
      "address_region": "program_or_external",
      "bytes": "0C030088",
      "text": "LDC.W #H'0300, SR",
      "mnemonic": "LDC.W",
      "operands": "#H'0300, SR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17294,
        "changes": [
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 768,
              "hex": "0x0300",
              "width": 16,
              "source": "LDC.W #H'0300, SR"
            }
          }
        ],
        "notes": [
          "SR = 0x0300"
        ],
        "known_after": {
          "control": {
            "SR": {
              "known": true,
              "value": 768,
              "hex": "0x0300",
              "width": 16,
              "source": "LDC.W #H'0300, SR"
            }
          }
        }
      }
    },
    {
      "address": 17298,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17294,
        "changes": [],
        "notes": [],
        "known_after": {
          "control": {
            "SR": {
              "known": true,
              "value": 768,
              "hex": "0x0300",
              "width": 16,
              "source": "LDC.W #H'0300, SR"
            }
          }
        }
      }
    },
    {
      "address": 17299,
      "address_region": "program_or_external",
      "bytes": "0A",
      "text": "RTE",
      "mnemonic": "RTE",
      "operands": "",
      "kind": "rte",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "base_cycles": 13,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17299,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17300,
      "address_region": "program_or_external",
      "bytes": "15F7310401",
      "text": "CMP:G.B #H'01, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'01, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17300,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17305,
      "address_region": "program_or_external",
      "bytes": "320086",
      "text": "BHI loc_4422",
      "mnemonic": "BHI",
      "operands": "loc_4422",
      "kind": "branch",
      "targets": [
        17442
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17300,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17308,
      "address_region": "program_or_external",
      "bytes": "15FB03F7",
      "text": "BTST.B #7, @H'FB03",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FB03",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
          "name": null,
          "symbol": "ram_FB03",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17308,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17312,
      "address_region": "program_or_external",
      "bytes": "36007F",
      "text": "BNE loc_4422",
      "mnemonic": "BNE",
      "operands": "loc_4422",
      "kind": "branch",
      "targets": [
        17442
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17308,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17315,
      "address_region": "program_or_external",
      "bytes": "1DF73683",
      "text": "MOV:G.W @H'F736, R3",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F736, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63286,
          "name": null,
          "symbol": "ram_F736",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17315,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R3 unknown after memory load"
        ]
      }
    },
    {
      "address": 17319,
      "address_region": "program_or_external",
      "bytes": "370078",
      "text": "BEQ loc_4422",
      "mnemonic": "BEQ",
      "operands": "loc_4422",
      "kind": "branch",
      "targets": [
        17442
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17315,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17322,
      "address_region": "program_or_external",
      "bytes": "1DF69E84",
      "text": "MOV:G.W @H'F69E, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F69E, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63134,
          "name": null,
          "symbol": "ram_F69E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17322,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 17326,
      "address_region": "program_or_external",
      "bytes": "1DF6BE34",
      "text": "SUB.W @H'F6BE, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6BE, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63166,
          "name": null,
          "symbol": "ram_F6BE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17322,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 17330,
      "address_region": "program_or_external",
      "bytes": "ABDF",
      "text": "BCLR.W #15, R3",
      "mnemonic": "BCLR.W",
      "operands": "#15, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17322,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17332,
      "address_region": "program_or_external",
      "bytes": "2619",
      "text": "BNE loc_43CF",
      "mnemonic": "BNE",
      "operands": "loc_43CF",
      "kind": "branch",
      "targets": [
        17359
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17322,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17334,
      "address_region": "program_or_external",
      "bytes": "ABDE",
      "text": "BCLR.W #14, R3",
      "mnemonic": "BCLR.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17334,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17336,
      "address_region": "program_or_external",
      "bytes": "2621",
      "text": "BNE loc_43DB",
      "mnemonic": "BNE",
      "operands": "loc_43DB",
      "kind": "branch",
      "targets": [
        17371
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17334,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17338,
      "address_region": "program_or_external",
      "bytes": "ABDD",
      "text": "BCLR.W #13, R3",
      "mnemonic": "BCLR.W",
      "operands": "#13, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17338,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17340,
      "address_region": "program_or_external",
      "bytes": "2629",
      "text": "BNE loc_43E7",
      "mnemonic": "BNE",
      "operands": "loc_43E7",
      "kind": "branch",
      "targets": [
        17383
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17338,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17342,
      "address_region": "program_or_external",
      "bytes": "ABDC",
      "text": "BCLR.W #12, R3",
      "mnemonic": "BCLR.W",
      "operands": "#12, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17342,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17344,
      "address_region": "program_or_external",
      "bytes": "2631",
      "text": "BNE loc_43F3",
      "mnemonic": "BNE",
      "operands": "loc_43F3",
      "kind": "branch",
      "targets": [
        17395
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17342,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17346,
      "address_region": "program_or_external",
      "bytes": "ABDB",
      "text": "BCLR.W #11, R3",
      "mnemonic": "BCLR.W",
      "operands": "#11, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17346,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17348,
      "address_region": "program_or_external",
      "bytes": "2639",
      "text": "BNE loc_43FF",
      "mnemonic": "BNE",
      "operands": "loc_43FF",
      "kind": "branch",
      "targets": [
        17407
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17346,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17350,
      "address_region": "program_or_external",
      "bytes": "ABDA",
      "text": "BCLR.W #10, R3",
      "mnemonic": "BCLR.W",
      "operands": "#10, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17350,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17352,
      "address_region": "program_or_external",
      "bytes": "2643",
      "text": "BNE loc_440D",
      "mnemonic": "BNE",
      "operands": "loc_440D",
      "kind": "branch",
      "targets": [
        17421
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17350,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17354,
      "address_region": "program_or_external",
      "bytes": "1ED5D5",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17354,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17357,
      "address_region": "program_or_external",
      "bytes": "2053",
      "text": "BRA loc_4422",
      "mnemonic": "BRA",
      "operands": "loc_4422",
      "kind": "jump",
      "targets": [
        17442
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17354,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17359,
      "address_region": "program_or_external",
      "bytes": "0E5E",
      "text": "BSR loc_442F",
      "mnemonic": "BSR",
      "operands": "loc_442F",
      "kind": "call",
      "targets": [
        17455
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17359,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17361,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
      "kind": "normal",
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      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17390,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17393,
      "address_region": "program_or_external",
      "bytes": "202F",
      "text": "BRA loc_4422",
      "mnemonic": "BRA",
      "operands": "loc_4422",
      "kind": "jump",
      "targets": [
        17442
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17393,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17395,
      "address_region": "program_or_external",
      "bytes": "0E3A",
      "text": "BSR loc_442F",
      "mnemonic": "BSR",
      "operands": "loc_442F",
      "kind": "call",
      "targets": [
        17455
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17395,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17397,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17395,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17400,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_43FD",
      "mnemonic": "BEQ",
      "operands": "loc_43FD",
      "kind": "branch",
      "targets": [
        17405
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17395,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17402,
      "address_region": "program_or_external",
      "bytes": "1ED70E",
      "text": "BSR loc_1B0B",
      "mnemonic": "BSR",
      "operands": "loc_1B0B",
      "kind": "call",
      "targets": [
        6923
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17402,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17405,
      "address_region": "program_or_external",
      "bytes": "2023",
      "text": "BRA loc_4422",
      "mnemonic": "BRA",
      "operands": "loc_4422",
      "kind": "jump",
      "targets": [
        17442
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17405,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17407,
      "address_region": "program_or_external",
      "bytes": "15F7700680",
      "text": "MOV:G.B #H'80, @H'F770",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F770",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63344,
          "name": null,
          "symbol": "ram_F770",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17407,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17412,
      "address_region": "program_or_external",
      "bytes": "1DF77294",
      "text": "MOV:G.W R4, @H'F772",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F772",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63346,
          "name": null,
          "symbol": "ram_F772",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17407,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17416,
      "address_region": "program_or_external",
      "bytes": "1E04EF",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17407,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17419,
      "address_region": "program_or_external",
      "bytes": "2015",
      "text": "BRA loc_4422",
      "mnemonic": "BRA",
      "operands": "loc_4422",
      "kind": "jump",
      "targets": [
        17442
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17407,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17421,
      "address_region": "program_or_external",
      "bytes": "0E20",
      "text": "BSR loc_442F",
      "mnemonic": "BSR",
      "operands": "loc_442F",
      "kind": "call",
      "targets": [
        17455
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17421,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17423,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17421,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17426,
      "address_region": "program_or_external",
      "bytes": "270C",
      "text": "BEQ loc_4420",
      "mnemonic": "BEQ",
      "operands": "loc_4420",
      "kind": "branch",
      "targets": [
        17440
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17421,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17428,
      "address_region": "program_or_external",
      "bytes": "15F7700680",
      "text": "MOV:G.B #H'80, @H'F770",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F770",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63344,
          "name": null,
          "symbol": "ram_F770",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17428,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17433,
      "address_region": "program_or_external",
      "bytes": "1DF77294",
      "text": "MOV:G.W R4, @H'F772",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F772",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63346,
          "name": null,
          "symbol": "ram_F772",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17428,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17437,
      "address_region": "program_or_external",
      "bytes": "1E04DA",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17428,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17440,
      "address_region": "program_or_external",
      "bytes": "2000",
      "text": "BRA loc_4422",
      "mnemonic": "BRA",
      "operands": "loc_4422",
      "kind": "jump",
      "targets": [
        17442
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17440,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17442,
      "address_region": "program_or_external",
      "bytes": "1DF69E84",
      "text": "MOV:G.W @H'F69E, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F69E, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63134,
          "name": null,
          "symbol": "ram_F69E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17442,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 17446,
      "address_region": "program_or_external",
      "bytes": "1DF6BE94",
      "text": "MOV:G.W R4, @H'F6BE",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6BE",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63166,
          "name": null,
          "symbol": "ram_F6BE",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17442,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17450,
      "address_region": "program_or_external",
      "bytes": "15FB0213",
      "text": "CLR.B @H'FB02",
      "mnemonic": "CLR.B",
      "operands": "@H'FB02",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64258,
          "name": null,
          "symbol": "ram_FB02",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17442,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17454,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17442,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17455,
      "address_region": "program_or_external",
      "bytes": "15F6F724",
      "text": "ADD:G.B @H'F6F7, R4",
      "mnemonic": "ADD:G.B",
      "operands": "@H'F6F7, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63223,
          "name": null,
          "symbol": "ram_F6F7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17455,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 17459,
      "address_region": "program_or_external",
      "bytes": "4488",
      "text": "CMP:E #H'88, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'88, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17455,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17461,
      "address_region": "program_or_external",
      "bytes": "240D",
      "text": "BCC loc_4444",
      "mnemonic": "BCC",
      "operands": "loc_4444",
      "kind": "branch",
      "targets": [
        17476
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17455,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17463,
      "address_region": "program_or_external",
      "bytes": "4478",
      "text": "CMP:E #H'78, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'78, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17463,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17465,
      "address_region": "program_or_external",
      "bytes": "2313",
      "text": "BLS loc_444E",
      "mnemonic": "BLS",
      "operands": "loc_444E",
      "kind": "branch",
      "targets": [
        17486
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17463,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17467,
      "address_region": "program_or_external",
      "bytes": "15F6F794",
      "text": "MOV:G.B R4, @H'F6F7",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6F7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63223,
          "name": null,
          "symbol": "ram_F6F7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17467,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17471,
      "address_region": "program_or_external",
      "bytes": "5C0002",
      "text": "MOV:I.W #H'0002, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17467,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x0002"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R4"
            }
          }
        }
      }
    },
    {
      "address": 17474,
      "address_region": "program_or_external",
      "bytes": "2012",
      "text": "BRA loc_4456",
      "mnemonic": "BRA",
      "operands": "loc_4456",
      "kind": "jump",
      "targets": [
        17494
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17467,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R4"
            }
          }
        }
      }
    },
    {
      "address": 17476,
      "address_region": "program_or_external",
      "bytes": "15F6F70680",
      "text": "MOV:G.B #H'80, @H'F6F7",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F6F7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63223,
          "name": null,
          "symbol": "ram_F6F7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17476,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17481,
      "address_region": "program_or_external",
      "bytes": "5C0000",
      "text": "MOV:I.W #H'0000, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0000, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17476,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x0000"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        }
      }
    },
    {
      "address": 17484,
      "address_region": "program_or_external",
      "bytes": "2008",
      "text": "BRA loc_4456",
      "mnemonic": "BRA",
      "operands": "loc_4456",
      "kind": "jump",
      "targets": [
        17494
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17476,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        }
      }
    },
    {
      "address": 17486,
      "address_region": "program_or_external",
      "bytes": "15F6F70680",
      "text": "MOV:G.B #H'80, @H'F6F7",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F6F7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63223,
          "name": null,
          "symbol": "ram_F6F7",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17486,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17491,
      "address_region": "program_or_external",
      "bytes": "5C0001",
      "text": "MOV:I.W #H'0001, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0001, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17486,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x0001"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            }
          }
        }
      }
    },
    {
      "address": 17494,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17494,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17495,
      "address_region": "program_or_external",
      "bytes": "15F7310401",
      "text": "CMP:G.B #H'01, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'01, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17495,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17500,
      "address_region": "program_or_external",
      "bytes": "320086",
      "text": "BHI loc_44E5",
      "mnemonic": "BHI",
      "operands": "loc_44E5",
      "kind": "branch",
      "targets": [
        17637
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17495,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17503,
      "address_region": "program_or_external",
      "bytes": "15FB03F7",
      "text": "BTST.B #7, @H'FB03",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FB03",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
          "name": null,
          "symbol": "ram_FB03",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17503,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17507,
      "address_region": "program_or_external",
      "bytes": "36007F",
      "text": "BNE loc_44E5",
      "mnemonic": "BNE",
      "operands": "loc_44E5",
      "kind": "branch",
      "targets": [
        17637
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17503,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17510,
      "address_region": "program_or_external",
      "bytes": "1DF73883",
      "text": "MOV:G.W @H'F738, R3",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F738, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63288,
          "name": null,
          "symbol": "ram_F738",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17510,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R3 unknown after memory load"
        ]
      }
    },
    {
      "address": 17514,
      "address_region": "program_or_external",
      "bytes": "370078",
      "text": "BEQ loc_44E5",
      "mnemonic": "BEQ",
      "operands": "loc_44E5",
      "kind": "branch",
      "targets": [
        17637
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17510,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17517,
      "address_region": "program_or_external",
      "bytes": "1DF69C84",
      "text": "MOV:G.W @H'F69C, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F69C, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63132,
          "name": null,
          "symbol": "ram_F69C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17517,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 17521,
      "address_region": "program_or_external",
      "bytes": "1DF6BC34",
      "text": "SUB.W @H'F6BC, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6BC, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63164,
          "name": null,
          "symbol": "ram_F6BC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17517,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 17525,
      "address_region": "program_or_external",
      "bytes": "ABDF",
      "text": "BCLR.W #15, R3",
      "mnemonic": "BCLR.W",
      "operands": "#15, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17517,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17527,
      "address_region": "program_or_external",
      "bytes": "2619",
      "text": "BNE loc_4492",
      "mnemonic": "BNE",
      "operands": "loc_4492",
      "kind": "branch",
      "targets": [
        17554
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17517,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17529,
      "address_region": "program_or_external",
      "bytes": "ABDE",
      "text": "BCLR.W #14, R3",
      "mnemonic": "BCLR.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17529,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17531,
      "address_region": "program_or_external",
      "bytes": "2621",
      "text": "BNE loc_449E",
      "mnemonic": "BNE",
      "operands": "loc_449E",
      "kind": "branch",
      "targets": [
        17566
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17529,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17533,
      "address_region": "program_or_external",
      "bytes": "ABDD",
      "text": "BCLR.W #13, R3",
      "mnemonic": "BCLR.W",
      "operands": "#13, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17533,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17535,
      "address_region": "program_or_external",
      "bytes": "2629",
      "text": "BNE loc_44AA",
      "mnemonic": "BNE",
      "operands": "loc_44AA",
      "kind": "branch",
      "targets": [
        17578
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17533,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17537,
      "address_region": "program_or_external",
      "bytes": "ABDC",
      "text": "BCLR.W #12, R3",
      "mnemonic": "BCLR.W",
      "operands": "#12, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17537,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17539,
      "address_region": "program_or_external",
      "bytes": "2631",
      "text": "BNE loc_44B6",
      "mnemonic": "BNE",
      "operands": "loc_44B6",
      "kind": "branch",
      "targets": [
        17590
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17537,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17541,
      "address_region": "program_or_external",
      "bytes": "ABDB",
      "text": "BCLR.W #11, R3",
      "mnemonic": "BCLR.W",
      "operands": "#11, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17541,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
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          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17543,
      "address_region": "program_or_external",
      "bytes": "2639",
      "text": "BNE loc_44C2",
      "mnemonic": "BNE",
      "operands": "loc_44C2",
      "kind": "branch",
      "targets": [
        17602
      ],
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        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
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        "block": 17541,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17545,
      "address_region": "program_or_external",
      "bytes": "ABDA",
      "text": "BCLR.W #10, R3",
      "mnemonic": "BCLR.W",
      "operands": "#10, R3",
      "kind": "normal",
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      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17545,
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            "kind": "register",
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              "reason": "unsupported:BCLR.W"
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          {
            "kind": "control",
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              "known": false,
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              "known": false,
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          }
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          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17547,
      "address_region": "program_or_external",
      "bytes": "2643",
      "text": "BNE loc_44D0",
      "mnemonic": "BNE",
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      "kind": "branch",
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        17616
      ],
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        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "valid": true,
      "dataflow": {
        "block": 17545,
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      }
    },
    {
      "address": 17549,
      "address_region": "program_or_external",
      "bytes": "1ED512",
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      "operands": "loc_19A2",
      "kind": "call",
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        6562
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        "alignment_adjustment": 1,
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        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
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          },
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          },
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            "kind": "register",
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          },
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            "kind": "control",
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              "reason": "call"
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          },
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            "kind": "control",
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              "known": false,
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          },
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            "kind": "control",
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          },
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          },
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          }
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      }
    },
    {
      "address": 17552,
      "address_region": "program_or_external",
      "bytes": "2053",
      "text": "BRA loc_44E5",
      "mnemonic": "BRA",
      "operands": "loc_44E5",
      "kind": "jump",
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        "base_taken": 7,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      }
    },
    {
      "address": 17554,
      "address_region": "program_or_external",
      "bytes": "0E5E",
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        "source": "manual Appendix A.4, tables A-7/A-8",
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            "kind": "control",
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          },
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              "reason": "call"
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          }
        ],
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        ]
      }
    },
    {
      "address": 17556,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      "dataflow": {
        "block": 17554,
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            "kind": "control",
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          }
        ],
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      }
    },
    {
      "address": 17559,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_449C",
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
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    },
    {
      "address": 17561,
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      "bytes": "1ED599",
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        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
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      },
      "references": [],
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          },
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            "kind": "control",
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          }
        ],
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      }
    },
    {
      "address": 17564,
      "address_region": "program_or_external",
      "bytes": "2047",
      "text": "BRA loc_44E5",
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      "operands": "loc_44E5",
      "kind": "jump",
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        17637
      ],
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      },
      "references": [],
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      }
    },
    {
      "address": 17566,
      "address_region": "program_or_external",
      "bytes": "0E52",
      "text": "BSR loc_44F2",
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      "operands": "loc_44F2",
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        17650
      ],
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        "source": "manual Appendix A.4, tables A-7/A-8",
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          },
          {
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          },
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          },
          {
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              "reason": "call"
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          },
          {
            "kind": "control",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
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              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
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          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17568,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17566,
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          {
            "kind": "control",
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              "reason": "call"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17571,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_44A8",
      "mnemonic": "BEQ",
      "operands": "loc_44A8",
      "kind": "branch",
      "targets": [
        17576
      ],
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        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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        "block": 17566,
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      }
    },
    {
      "address": 17573,
      "address_region": "program_or_external",
      "bytes": "1ED5F4",
      "text": "BSR loc_1A9C",
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      "operands": "loc_1A9C",
      "kind": "call",
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        6812
      ],
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        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
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          },
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          },
          {
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          },
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            "kind": "control",
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          },
          {
            "kind": "control",
            "name": "EP",
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              "known": false,
              "reason": "block_entry"
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            }
          },
          {
            "kind": "control",
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              "reason": "call"
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          },
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          },
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              "reason": "call"
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          }
        ],
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        ]
      }
    },
    {
      "address": 17576,
      "address_region": "program_or_external",
      "bytes": "203B",
      "text": "BRA loc_44E5",
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      "operands": "loc_44E5",
      "kind": "jump",
      "targets": [
        17637
      ],
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        "taken": 7,
        "base_taken": 7,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
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      }
    },
    {
      "address": 17578,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
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          },
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            "kind": "control",
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          },
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          },
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          },
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              "reason": "call"
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          }
        ],
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        ]
      }
    },
    {
      "address": 17580,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
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        "source": "manual Appendix A.4, tables A-7/A-8",
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      "references": [],
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      "dataflow": {
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          }
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      }
    },
    {
      "address": 17583,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_44B4",
      "mnemonic": "BEQ",
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        "assumption": "on-chip instruction fetch/operand access, no external wait states"
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    },
    {
      "address": 17585,
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
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              "reason": "call"
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          },
          {
            "kind": "register",
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          },
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          },
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          },
          {
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          },
          {
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          },
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              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17588,
      "address_region": "program_or_external",
      "bytes": "202F",
      "text": "BRA loc_44E5",
      "mnemonic": "BRA",
      "operands": "loc_44E5",
      "kind": "jump",
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      ],
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        "source": "manual Appendix A.4, tables A-7/A-8",
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      },
      "references": [],
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      }
    },
    {
      "address": 17590,
      "address_region": "program_or_external",
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      "operands": "loc_44F2",
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      ],
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
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          },
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          },
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          },
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          },
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          },
          {
            "kind": "control",
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              "reason": "call"
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          },
          {
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            "after": {
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          },
          {
            "kind": "control",
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              "reason": "call"
            }
          }
        ],
        "notes": [
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        ]
      }
    },
    {
      "address": 17592,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
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      },
      "references": [],
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      "dataflow": {
        "block": 17590,
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            "kind": "control",
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              "reason": "call"
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            "after": {
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              "reason": "flags"
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          }
        ],
        "notes": []
      }
    },
    {
      "address": 17595,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_44C0",
      "mnemonic": "BEQ",
      "operands": "loc_44C0",
      "kind": "branch",
      "targets": [
        17600
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17590,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17597,
      "address_region": "program_or_external",
      "bytes": "1ED64B",
      "text": "BSR loc_1B0B",
      "mnemonic": "BSR",
      "operands": "loc_1B0B",
      "kind": "call",
      "targets": [
        6923
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17597,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17600,
      "address_region": "program_or_external",
      "bytes": "2023",
      "text": "BRA loc_44E5",
      "mnemonic": "BRA",
      "operands": "loc_44E5",
      "kind": "jump",
      "targets": [
        17637
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17600,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17602,
      "address_region": "program_or_external",
      "bytes": "15F7700640",
      "text": "MOV:G.B #H'40, @H'F770",
      "mnemonic": "MOV:G.B",
      "operands": "#H'40, @H'F770",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63344,
          "name": null,
          "symbol": "ram_F770",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17602,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17607,
      "address_region": "program_or_external",
      "bytes": "1DF77294",
      "text": "MOV:G.W R4, @H'F772",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F772",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63346,
          "name": null,
          "symbol": "ram_F772",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17602,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17611,
      "address_region": "program_or_external",
      "bytes": "1E042C",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17602,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17614,
      "address_region": "program_or_external",
      "bytes": "2015",
      "text": "BRA loc_44E5",
      "mnemonic": "BRA",
      "operands": "loc_44E5",
      "kind": "jump",
      "targets": [
        17637
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17602,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17616,
      "address_region": "program_or_external",
      "bytes": "0E20",
      "text": "BSR loc_44F2",
      "mnemonic": "BSR",
      "operands": "loc_44F2",
      "kind": "call",
      "targets": [
        17650
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17616,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17618,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17616,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17621,
      "address_region": "program_or_external",
      "bytes": "270C",
      "text": "BEQ loc_44E3",
      "mnemonic": "BEQ",
      "operands": "loc_44E3",
      "kind": "branch",
      "targets": [
        17635
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17616,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17623,
      "address_region": "program_or_external",
      "bytes": "15F7700640",
      "text": "MOV:G.B #H'40, @H'F770",
      "mnemonic": "MOV:G.B",
      "operands": "#H'40, @H'F770",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63344,
          "name": null,
          "symbol": "ram_F770",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17623,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17628,
      "address_region": "program_or_external",
      "bytes": "1DF77294",
      "text": "MOV:G.W R4, @H'F772",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F772",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63346,
          "name": null,
          "symbol": "ram_F772",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17623,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17632,
      "address_region": "program_or_external",
      "bytes": "1E0417",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17623,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17635,
      "address_region": "program_or_external",
      "bytes": "2000",
      "text": "BRA loc_44E5",
      "mnemonic": "BRA",
      "operands": "loc_44E5",
      "kind": "jump",
      "targets": [
        17637
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17635,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17637,
      "address_region": "program_or_external",
      "bytes": "1DF69C84",
      "text": "MOV:G.W @H'F69C, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F69C, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63132,
          "name": null,
          "symbol": "ram_F69C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17637,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 17641,
      "address_region": "program_or_external",
      "bytes": "1DF6BC94",
      "text": "MOV:G.W R4, @H'F6BC",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6BC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63164,
          "name": null,
          "symbol": "ram_F6BC",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17637,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17645,
      "address_region": "program_or_external",
      "bytes": "15FB0213",
      "text": "CLR.B @H'FB02",
      "mnemonic": "CLR.B",
      "operands": "@H'FB02",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64258,
          "name": null,
          "symbol": "ram_FB02",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17637,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17649,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17637,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17650,
      "address_region": "program_or_external",
      "bytes": "15F6F824",
      "text": "ADD:G.B @H'F6F8, R4",
      "mnemonic": "ADD:G.B",
      "operands": "@H'F6F8, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63224,
          "name": null,
          "symbol": "ram_F6F8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17650,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 17654,
      "address_region": "program_or_external",
      "bytes": "4488",
      "text": "CMP:E #H'88, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'88, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17650,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17656,
      "address_region": "program_or_external",
      "bytes": "240D",
      "text": "BCC loc_4507",
      "mnemonic": "BCC",
      "operands": "loc_4507",
      "kind": "branch",
      "targets": [
        17671
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17650,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17658,
      "address_region": "program_or_external",
      "bytes": "4478",
      "text": "CMP:E #H'78, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'78, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17658,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17660,
      "address_region": "program_or_external",
      "bytes": "2313",
      "text": "BLS loc_4511",
      "mnemonic": "BLS",
      "operands": "loc_4511",
      "kind": "branch",
      "targets": [
        17681
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17658,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17662,
      "address_region": "program_or_external",
      "bytes": "15F6F894",
      "text": "MOV:G.B R4, @H'F6F8",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6F8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63224,
          "name": null,
          "symbol": "ram_F6F8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17662,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17666,
      "address_region": "program_or_external",
      "bytes": "5C0002",
      "text": "MOV:I.W #H'0002, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17662,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x0002"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R4"
            }
          }
        }
      }
    },
    {
      "address": 17669,
      "address_region": "program_or_external",
      "bytes": "2012",
      "text": "BRA loc_4519",
      "mnemonic": "BRA",
      "operands": "loc_4519",
      "kind": "jump",
      "targets": [
        17689
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17662,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R4"
            }
          }
        }
      }
    },
    {
      "address": 17671,
      "address_region": "program_or_external",
      "bytes": "15F6F80680",
      "text": "MOV:G.B #H'80, @H'F6F8",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F6F8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63224,
          "name": null,
          "symbol": "ram_F6F8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17671,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17676,
      "address_region": "program_or_external",
      "bytes": "5C0000",
      "text": "MOV:I.W #H'0000, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0000, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17671,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x0000"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        }
      }
    },
    {
      "address": 17679,
      "address_region": "program_or_external",
      "bytes": "2008",
      "text": "BRA loc_4519",
      "mnemonic": "BRA",
      "operands": "loc_4519",
      "kind": "jump",
      "targets": [
        17689
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17671,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        }
      }
    },
    {
      "address": 17681,
      "address_region": "program_or_external",
      "bytes": "15F6F80680",
      "text": "MOV:G.B #H'80, @H'F6F8",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F6F8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63224,
          "name": null,
          "symbol": "ram_F6F8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17681,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17686,
      "address_region": "program_or_external",
      "bytes": "5C0001",
      "text": "MOV:I.W #H'0001, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0001, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17681,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x0001"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            }
          }
        }
      }
    },
    {
      "address": 17689,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17689,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17690,
      "address_region": "program_or_external",
      "bytes": "15F7310401",
      "text": "CMP:G.B #H'01, @H'F731",
      "mnemonic": "CMP:G.B",
      "operands": "#H'01, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17690,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17695,
      "address_region": "program_or_external",
      "bytes": "320086",
      "text": "BHI loc_45A8",
      "mnemonic": "BHI",
      "operands": "loc_45A8",
      "kind": "branch",
      "targets": [
        17832
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17690,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17698,
      "address_region": "program_or_external",
      "bytes": "15FB03F7",
      "text": "BTST.B #7, @H'FB03",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FB03",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
          "name": null,
          "symbol": "ram_FB03",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17698,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17702,
      "address_region": "program_or_external",
      "bytes": "36007F",
      "text": "BNE loc_45A8",
      "mnemonic": "BNE",
      "operands": "loc_45A8",
      "kind": "branch",
      "targets": [
        17832
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17698,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17705,
      "address_region": "program_or_external",
      "bytes": "1DF73A83",
      "text": "MOV:G.W @H'F73A, R3",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F73A, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63290,
          "name": null,
          "symbol": "ram_F73A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17705,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R3 unknown after memory load"
        ]
      }
    },
    {
      "address": 17709,
      "address_region": "program_or_external",
      "bytes": "370078",
      "text": "BEQ loc_45A8",
      "mnemonic": "BEQ",
      "operands": "loc_45A8",
      "kind": "branch",
      "targets": [
        17832
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17705,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17712,
      "address_region": "program_or_external",
      "bytes": "1DF69A84",
      "text": "MOV:G.W @H'F69A, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F69A, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63130,
          "name": null,
          "symbol": "ram_F69A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17712,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 17716,
      "address_region": "program_or_external",
      "bytes": "1DF6BA34",
      "text": "SUB.W @H'F6BA, R4",
      "mnemonic": "SUB.W",
      "operands": "@H'F6BA, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63162,
          "name": null,
          "symbol": "ram_F6BA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17712,
        "changes": [],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 17720,
      "address_region": "program_or_external",
      "bytes": "ABDF",
      "text": "BCLR.W #15, R3",
      "mnemonic": "BCLR.W",
      "operands": "#15, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17712,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17722,
      "address_region": "program_or_external",
      "bytes": "2619",
      "text": "BNE loc_4555",
      "mnemonic": "BNE",
      "operands": "loc_4555",
      "kind": "branch",
      "targets": [
        17749
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17712,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17724,
      "address_region": "program_or_external",
      "bytes": "ABDE",
      "text": "BCLR.W #14, R3",
      "mnemonic": "BCLR.W",
      "operands": "#14, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17724,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17726,
      "address_region": "program_or_external",
      "bytes": "2621",
      "text": "BNE loc_4561",
      "mnemonic": "BNE",
      "operands": "loc_4561",
      "kind": "branch",
      "targets": [
        17761
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17724,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17728,
      "address_region": "program_or_external",
      "bytes": "ABDD",
      "text": "BCLR.W #13, R3",
      "mnemonic": "BCLR.W",
      "operands": "#13, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17728,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17730,
      "address_region": "program_or_external",
      "bytes": "2629",
      "text": "BNE loc_456D",
      "mnemonic": "BNE",
      "operands": "loc_456D",
      "kind": "branch",
      "targets": [
        17773
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17728,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17732,
      "address_region": "program_or_external",
      "bytes": "ABDC",
      "text": "BCLR.W #12, R3",
      "mnemonic": "BCLR.W",
      "operands": "#12, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17732,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17734,
      "address_region": "program_or_external",
      "bytes": "2631",
      "text": "BNE loc_4579",
      "mnemonic": "BNE",
      "operands": "loc_4579",
      "kind": "branch",
      "targets": [
        17785
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17732,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17736,
      "address_region": "program_or_external",
      "bytes": "ABDB",
      "text": "BCLR.W #11, R3",
      "mnemonic": "BCLR.W",
      "operands": "#11, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17736,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17738,
      "address_region": "program_or_external",
      "bytes": "2639",
      "text": "BNE loc_4585",
      "mnemonic": "BNE",
      "operands": "loc_4585",
      "kind": "branch",
      "targets": [
        17797
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17736,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17740,
      "address_region": "program_or_external",
      "bytes": "ABDA",
      "text": "BCLR.W #10, R3",
      "mnemonic": "BCLR.W",
      "operands": "#10, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17740,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 17742,
      "address_region": "program_or_external",
      "bytes": "2643",
      "text": "BNE loc_4593",
      "mnemonic": "BNE",
      "operands": "loc_4593",
      "kind": "branch",
      "targets": [
        17811
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17740,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17744,
      "address_region": "program_or_external",
      "bytes": "1ED44F",
      "text": "BSR loc_19A2",
      "mnemonic": "BSR",
      "operands": "loc_19A2",
      "kind": "call",
      "targets": [
        6562
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17744,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17747,
      "address_region": "program_or_external",
      "bytes": "2053",
      "text": "BRA loc_45A8",
      "mnemonic": "BRA",
      "operands": "loc_45A8",
      "kind": "jump",
      "targets": [
        17832
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17744,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17749,
      "address_region": "program_or_external",
      "bytes": "0E5E",
      "text": "BSR loc_45B5",
      "mnemonic": "BSR",
      "operands": "loc_45B5",
      "kind": "call",
      "targets": [
        17845
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17749,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
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              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17775,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17773,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17778,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_4577",
      "mnemonic": "BEQ",
      "operands": "loc_4577",
      "kind": "branch",
      "targets": [
        17783
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17773,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17780,
      "address_region": "program_or_external",
      "bytes": "1ED56D",
      "text": "BSR loc_1AE4",
      "mnemonic": "BSR",
      "operands": "loc_1AE4",
      "kind": "call",
      "targets": [
        6884
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17780,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17783,
      "address_region": "program_or_external",
      "bytes": "202F",
      "text": "BRA loc_45A8",
      "mnemonic": "BRA",
      "operands": "loc_45A8",
      "kind": "jump",
      "targets": [
        17832
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17783,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17785,
      "address_region": "program_or_external",
      "bytes": "0E3A",
      "text": "BSR loc_45B5",
      "mnemonic": "BSR",
      "operands": "loc_45B5",
      "kind": "call",
      "targets": [
        17845
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17785,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17787,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17785,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17790,
      "address_region": "program_or_external",
      "bytes": "2703",
      "text": "BEQ loc_4583",
      "mnemonic": "BEQ",
      "operands": "loc_4583",
      "kind": "branch",
      "targets": [
        17795
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17785,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17792,
      "address_region": "program_or_external",
      "bytes": "1ED588",
      "text": "BSR loc_1B0B",
      "mnemonic": "BSR",
      "operands": "loc_1B0B",
      "kind": "call",
      "targets": [
        6923
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17792,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17795,
      "address_region": "program_or_external",
      "bytes": "2023",
      "text": "BRA loc_45A8",
      "mnemonic": "BRA",
      "operands": "loc_45A8",
      "kind": "jump",
      "targets": [
        17832
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17795,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17797,
      "address_region": "program_or_external",
      "bytes": "15F7700620",
      "text": "MOV:G.B #H'20, @H'F770",
      "mnemonic": "MOV:G.B",
      "operands": "#H'20, @H'F770",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63344,
          "name": null,
          "symbol": "ram_F770",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17797,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17802,
      "address_region": "program_or_external",
      "bytes": "1DF77294",
      "text": "MOV:G.W R4, @H'F772",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F772",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63346,
          "name": null,
          "symbol": "ram_F772",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17797,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17806,
      "address_region": "program_or_external",
      "bytes": "1E0369",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17797,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17809,
      "address_region": "program_or_external",
      "bytes": "2015",
      "text": "BRA loc_45A8",
      "mnemonic": "BRA",
      "operands": "loc_45A8",
      "kind": "jump",
      "targets": [
        17832
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17797,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17811,
      "address_region": "program_or_external",
      "bytes": "0E20",
      "text": "BSR loc_45B5",
      "mnemonic": "BSR",
      "operands": "loc_45B5",
      "kind": "call",
      "targets": [
        17845
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17811,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17813,
      "address_region": "program_or_external",
      "bytes": "4C0002",
      "text": "CMP:I #H'0002, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17811,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17816,
      "address_region": "program_or_external",
      "bytes": "270C",
      "text": "BEQ loc_45A6",
      "mnemonic": "BEQ",
      "operands": "loc_45A6",
      "kind": "branch",
      "targets": [
        17830
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17811,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17818,
      "address_region": "program_or_external",
      "bytes": "15F7700620",
      "text": "MOV:G.B #H'20, @H'F770",
      "mnemonic": "MOV:G.B",
      "operands": "#H'20, @H'F770",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63344,
          "name": null,
          "symbol": "ram_F770",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17818,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17823,
      "address_region": "program_or_external",
      "bytes": "1DF77294",
      "text": "MOV:G.W R4, @H'F772",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F772",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63346,
          "name": null,
          "symbol": "ram_F772",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17818,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17827,
      "address_region": "program_or_external",
      "bytes": "1E0354",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17818,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 17830,
      "address_region": "program_or_external",
      "bytes": "2000",
      "text": "BRA loc_45A8",
      "mnemonic": "BRA",
      "operands": "loc_45A8",
      "kind": "jump",
      "targets": [
        17832
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17830,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17832,
      "address_region": "program_or_external",
      "bytes": "1DF69A84",
      "text": "MOV:G.W @H'F69A, R4",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F69A, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63130,
          "name": null,
          "symbol": "ram_F69A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17832,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 17836,
      "address_region": "program_or_external",
      "bytes": "1DF6BA94",
      "text": "MOV:G.W R4, @H'F6BA",
      "mnemonic": "MOV:G.W",
      "operands": "R4, @H'F6BA",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63162,
          "name": null,
          "symbol": "ram_F6BA",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17832,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17840,
      "address_region": "program_or_external",
      "bytes": "15FB0213",
      "text": "CLR.B @H'FB02",
      "mnemonic": "CLR.B",
      "operands": "@H'FB02",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64258,
          "name": null,
          "symbol": "ram_FB02",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17832,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17844,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17832,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17845,
      "address_region": "program_or_external",
      "bytes": "15F6F924",
      "text": "ADD:G.B @H'F6F9, R4",
      "mnemonic": "ADD:G.B",
      "operands": "@H'F6F9, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63225,
          "name": null,
          "symbol": "ram_F6F9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17845,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after arithmetic memory source"
        ]
      }
    },
    {
      "address": 17849,
      "address_region": "program_or_external",
      "bytes": "4488",
      "text": "CMP:E #H'88, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'88, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17845,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17851,
      "address_region": "program_or_external",
      "bytes": "240D",
      "text": "BCC loc_45CA",
      "mnemonic": "BCC",
      "operands": "loc_45CA",
      "kind": "branch",
      "targets": [
        17866
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17845,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17853,
      "address_region": "program_or_external",
      "bytes": "4478",
      "text": "CMP:E #H'78, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'78, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17853,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17855,
      "address_region": "program_or_external",
      "bytes": "2313",
      "text": "BLS loc_45D4",
      "mnemonic": "BLS",
      "operands": "loc_45D4",
      "kind": "branch",
      "targets": [
        17876
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17853,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 17857,
      "address_region": "program_or_external",
      "bytes": "15F6F994",
      "text": "MOV:G.B R4, @H'F6F9",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F6F9",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63225,
          "name": null,
          "symbol": "ram_F6F9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17857,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17861,
      "address_region": "program_or_external",
      "bytes": "5C0002",
      "text": "MOV:I.W #H'0002, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0002, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17857,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x0002"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R4"
            }
          }
        }
      }
    },
    {
      "address": 17864,
      "address_region": "program_or_external",
      "bytes": "2012",
      "text": "BRA loc_45DC",
      "mnemonic": "BRA",
      "operands": "loc_45DC",
      "kind": "jump",
      "targets": [
        17884
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17857,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 2,
              "hex": "0x0002",
              "width": 16,
              "source": "MOV:I.W #H'0002, R4"
            }
          }
        }
      }
    },
    {
      "address": 17866,
      "address_region": "program_or_external",
      "bytes": "15F6F90680",
      "text": "MOV:G.B #H'80, @H'F6F9",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F6F9",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63225,
          "name": null,
          "symbol": "ram_F6F9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17866,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17871,
      "address_region": "program_or_external",
      "bytes": "5C0000",
      "text": "MOV:I.W #H'0000, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0000, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17866,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x0000"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        }
      }
    },
    {
      "address": 17874,
      "address_region": "program_or_external",
      "bytes": "2008",
      "text": "BRA loc_45DC",
      "mnemonic": "BRA",
      "operands": "loc_45DC",
      "kind": "jump",
      "targets": [
        17884
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17866,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        }
      }
    },
    {
      "address": 17876,
      "address_region": "program_or_external",
      "bytes": "15F6F90680",
      "text": "MOV:G.B #H'80, @H'F6F9",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F6F9",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63225,
          "name": null,
          "symbol": "ram_F6F9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17876,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 17881,
      "address_region": "program_or_external",
      "bytes": "5C0001",
      "text": "MOV:I.W #H'0001, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0001, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17876,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            }
          }
        ],
        "notes": [
          "R4 = 0x0001"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 1,
              "hex": "0x0001",
              "width": 16,
              "source": "MOV:I.W #H'0001, R4"
            }
          }
        }
      }
    },
    {
      "address": 17884,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 17884,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 18671,
      "address_region": "program_or_external",
      "bytes": "1DF73480",
      "text": "MOV:G.W @H'F734, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F734, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63284,
          "name": null,
          "symbol": "ram_F734",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18671,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 18675,
      "address_region": "program_or_external",
      "bytes": "1DF73290",
      "text": "MOV:G.W R0, @H'F732",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F732",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18671,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 18679,
      "address_region": "program_or_external",
      "bytes": "0E01",
      "text": "BSR loc_48FA",
      "mnemonic": "BSR",
      "operands": "loc_48FA",
      "kind": "call",
      "targets": [
        18682
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18671,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 18681,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18671,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 18682,
      "address_region": "program_or_external",
      "bytes": "15FB03F7",
      "text": "BTST.B #7, @H'FB03",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FB03",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
          "name": null,
          "symbol": "ram_FB03",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18682,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 18686,
      "address_region": "program_or_external",
      "bytes": "2629",
      "text": "BNE loc_4929",
      "mnemonic": "BNE",
      "operands": "loc_4929",
      "kind": "branch",
      "targets": [
        18729
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18682,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 18688,
      "address_region": "program_or_external",
      "bytes": "15F732041A",
      "text": "CMP:G.B #H'1A, @H'F732",
      "mnemonic": "CMP:G.B",
      "operands": "#H'1A, @H'F732",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18688,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 18693,
      "address_region": "program_or_external",
      "bytes": "2722",
      "text": "BEQ loc_4929",
      "mnemonic": "BEQ",
      "operands": "loc_4929",
      "kind": "branch",
      "targets": [
        18729
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18688,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 18695,
      "address_region": "program_or_external",
      "bytes": "1DF732051900",
      "text": "CMP:G.W #H'1900, @H'F732",
      "mnemonic": "CMP:G.W",
      "operands": "#H'1900, @H'F732",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18695,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 18701,
      "address_region": "program_or_external",
      "bytes": "271A",
      "text": "BEQ loc_4929",
      "mnemonic": "BEQ",
      "operands": "loc_4929",
      "kind": "branch",
      "targets": [
        18729
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18695,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 18703,
      "address_region": "program_or_external",
      "bytes": "1DE1ECFD",
      "text": "BTST.W #13, @H'E1EC",
      "mnemonic": "BTST.W",
      "operands": "#13, @H'E1EC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57836,
          "name": null,
          "symbol": "mem_E1EC",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18703,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 18707,
      "address_region": "program_or_external",
      "bytes": "2714",
      "text": "BEQ loc_4929",
      "mnemonic": "BEQ",
      "operands": "loc_4929",
      "kind": "branch",
      "targets": [
        18729
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18703,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 18709,
      "address_region": "program_or_external",
      "bytes": "1DE1EC80",
      "text": "MOV:G.W @H'E1EC, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'E1EC, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 57836,
          "name": null,
          "symbol": "mem_E1EC",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18709,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 18713,
      "address_region": "program_or_external",
      "bytes": "0C9FFF50",
      "text": "AND.W #H'9FFF, R0",
      "mnemonic": "AND.W",
      "operands": "#H'9FFF, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18709,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 18717,
      "address_region": "program_or_external",
      "bytes": "1DE9EC90",
      "text": "MOV:G.W R0, @H'E9EC",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'E9EC",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 59884,
          "name": null,
          "symbol": "mem_E9EC",
          "region": "program_or_external",
          "kind": "program"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18709,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 18721,
      "address_region": "program_or_external",
      "bytes": "5280",
      "text": "MOV:E.B #H'80, R2",
      "mnemonic": "MOV:E.B",
      "operands": "#H'80, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18709,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        ],
        "notes": [
          "R2 = 0x80"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            }
          }
        }
      }
    },
    {
      "address": 18723,
      "address_region": "program_or_external",
      "bytes": "5B00F6",
      "text": "MOV:I.W #H'00F6, R3",
      "mnemonic": "MOV:I.W",
      "operands": "#H'00F6, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18709,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 246,
              "hex": "0x00F6",
              "width": 16,
              "source": "MOV:I.W #H'00F6, R3"
            }
          }
        ],
        "notes": [
          "R3 = 0x00F6"
        ],
        "known_after": {
          "registers": {
            "R2": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            },
            "R3": {
              "known": true,
              "value": 246,
              "hex": "0x00F6",
              "width": 16,
              "source": "MOV:I.W #H'00F6, R3"
            }
          }
        }
      }
    },
    {
      "address": 18726,
      "address_region": "program_or_external",
      "bytes": "1EF52B",
      "text": "BSR loc_3E54",
      "mnemonic": "BSR",
      "operands": "loc_3E54",
      "kind": "call",
      "targets": [
        15956
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18709,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R2"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": true,
              "value": 246,
              "hex": "0x00F6",
              "width": 16,
              "source": "MOV:I.W #H'00F6, R3"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 18729,
      "address_region": "program_or_external",
      "bytes": "15F76EF6",
      "text": "BTST.B #6, @H'F76E",
      "mnemonic": "BTST.B",
      "operands": "#6, @H'F76E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63342,
          "name": null,
          "symbol": "ram_F76E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18729,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 18733,
      "address_region": "program_or_external",
      "bytes": "260E",
      "text": "BNE loc_493D",
      "mnemonic": "BNE",
      "operands": "loc_493D",
      "kind": "branch",
      "targets": [
        18749
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18729,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 18735,
      "address_region": "program_or_external",
      "bytes": "15F73280",
      "text": "MOV:G.B @H'F732, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F732, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63282,
          "name": null,
          "symbol": "ram_F732",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18735,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 18739,
      "address_region": "program_or_external",
      "bytes": "A012",
      "text": "EXTU.B R0",
      "mnemonic": "EXTU.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18735,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 18741,
      "address_region": "program_or_external",
      "bytes": "A01A",
      "text": "SHLL.B R0",
      "mnemonic": "SHLL.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18735,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 18743,
      "address_region": "program_or_external",
      "bytes": "F8493E80",
      "text": "MOV:G.W @(H'493E,R0), R0",
      "mnemonic": "MOV:G.W",
      "operands": "@(H'493E,R0), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18735,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 18747,
      "address_region": "program_or_external",
      "bytes": "11D8",
      "text": "JSR @R0",
      "mnemonic": "JSR",
      "operands": "@R0",
      "kind": "call",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "indirect_flow": {
        "address": 18747,
        "instruction": "JSR @R0",
        "kind": "call",
        "target_register": "R0",
        "confidence": "table_load",
        "table": {
          "base": 18750,
          "index_register": "R0",
          "target_register": "R0",
          "load_address": 18743,
          "load_instruction": "MOV:G.W @(H'493E,R0), R0",
          "entry_size": 2,
          "entry_count": 52,
          "decoded_target_count": 0,
          "entries": [
            {
              "index": 0,
              "entry_address": 18750,
              "target": 25193,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 1,
              "entry_address": 18752,
              "target": 25372,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 2,
              "entry_address": 18754,
              "target": 25318,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 3,
              "entry_address": 18756,
              "target": 25292,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 4,
              "entry_address": 18758,
              "target": 25268,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 5,
              "entry_address": 18760,
              "target": 25248,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 6,
              "entry_address": 18762,
              "target": 25224,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 7,
              "entry_address": 18764,
              "target": 25205,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 8,
              "entry_address": 18766,
              "target": 25192,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 9,
              "entry_address": 18768,
              "target": 33086,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 10,
              "entry_address": 18770,
              "target": 33062,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 11,
              "entry_address": 18772,
              "target": 33042,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 12,
              "entry_address": 18774,
              "target": 33022,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 13,
              "entry_address": 18776,
              "target": 33002,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 14,
              "entry_address": 18778,
              "target": 32974,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 15,
              "entry_address": 18780,
              "target": 32938,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 16,
              "entry_address": 18782,
              "target": 25192,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 17,
              "entry_address": 18784,
              "target": 37844,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 18,
              "entry_address": 18786,
              "target": 37822,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 19,
              "entry_address": 18788,
              "target": 25192,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 20,
              "entry_address": 18790,
              "target": 37802,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 21,
              "entry_address": 18792,
              "target": 37778,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 22,
              "entry_address": 18794,
              "target": 37756,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 23,
              "entry_address": 18796,
              "target": 37722,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 24,
              "entry_address": 18798,
              "target": 37670,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 25,
              "entry_address": 18800,
              "target": 37642,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 26,
              "entry_address": 18802,
              "target": 37618,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 27,
              "entry_address": 18804,
              "target": 37614,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 28,
              "entry_address": 18806,
              "target": 37580,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 29,
              "entry_address": 18808,
              "target": 5627,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 30,
              "entry_address": 18810,
              "target": 983,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 31,
              "entry_address": 18812,
              "target": 9736,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 32,
              "entry_address": 18814,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 33,
              "entry_address": 18816,
              "target": 12928,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 34,
              "entry_address": 18818,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 35,
              "entry_address": 18820,
              "target": 13456,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 36,
              "entry_address": 18822,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 37,
              "entry_address": 18824,
              "target": 12807,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 38,
              "entry_address": 18826,
              "target": 6912,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 39,
              "entry_address": 18828,
              "target": 7935,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 40,
              "entry_address": 18830,
              "target": 27417,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 41,
              "entry_address": 18832,
              "target": 5627,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 42,
              "entry_address": 18834,
              "target": 983,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 43,
              "entry_address": 18836,
              "target": 9736,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 44,
              "entry_address": 18838,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 45,
              "entry_address": 18840,
              "target": 12928,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 46,
              "entry_address": 18842,
              "target": 7671,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 47,
              "entry_address": 18844,
              "target": 13456,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 48,
              "entry_address": 18846,
              "target": 5623,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 49,
              "entry_address": 18848,
              "target": 12804,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 50,
              "entry_address": 18850,
              "target": 6695,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            },
            {
              "index": 51,
              "entry_address": 18852,
              "target": 1565,
              "target_label": null,
              "target_region": "program_or_external",
              "decoded_code": false
            }
          ]
        },
        "summary": "JSR @R0 uses R0 loaded from pointer table H'493E via R0 (0/52 decoded targets)"
      },
      "dataflow": {
        "block": 18735,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 18749,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 18749,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25094,
      "address_region": "program_or_external",
      "bytes": "0C01FF55",
      "text": "AND.W #H'01FF, R5",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25094,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R5"
        ]
      }
    },
    {
      "address": 25098,
      "address_region": "program_or_external",
      "bytes": "4D007F",
      "text": "CMP:I #H'007F, R5",
      "mnemonic": "CMP:I",
      "operands": "#H'007F, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25094,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25101,
      "address_region": "program_or_external",
      "bytes": "2307",
      "text": "BLS loc_6216",
      "mnemonic": "BLS",
      "operands": "loc_6216",
      "kind": "branch",
      "targets": [
        25110
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25094,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25103,
      "address_region": "program_or_external",
      "bytes": "4D017F",
      "text": "CMP:I #H'017F, R5",
      "mnemonic": "CMP:I",
      "operands": "#H'017F, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25103,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 25106,
      "address_region": "program_or_external",
      "bytes": "2304",
      "text": "BLS loc_6218",
      "mnemonic": "BLS",
      "operands": "loc_6218",
      "kind": "branch",
      "targets": [
        25112
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25103,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25108,
      "address_region": "program_or_external",
      "bytes": "200C",
      "text": "BRA loc_6222",
      "mnemonic": "BRA",
      "operands": "loc_6222",
      "kind": "jump",
      "targets": [
        25122
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25108,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25110,
      "address_region": "program_or_external",
      "bytes": "2012",
      "text": "BRA loc_622A",
      "mnemonic": "BRA",
      "operands": "loc_622A",
      "kind": "jump",
      "targets": [
        25130
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25110,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25112,
      "address_region": "program_or_external",
      "bytes": "0C008035",
      "text": "SUB.W #H'0080, R5",
      "mnemonic": "SUB.W",
      "operands": "#H'0080, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25112,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 25116,
      "address_region": "program_or_external",
      "bytes": "0C010025",
      "text": "ADD:G.W #H'0100, R5",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0100, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25112,
        "changes": [],
        "notes": [
          "R5 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 25120,
      "address_region": "program_or_external",
      "bytes": "2008",
      "text": "BRA loc_622A",
      "mnemonic": "BRA",
      "operands": "loc_622A",
      "kind": "jump",
      "targets": [
        25130
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25112,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25122,
      "address_region": "program_or_external",
      "bytes": "0C018035",
      "text": "SUB.W #H'0180, R5",
      "mnemonic": "SUB.W",
      "operands": "#H'0180, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25122,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 25126,
      "address_region": "program_or_external",
      "bytes": "0C020025",
      "text": "ADD:G.W #H'0200, R5",
      "mnemonic": "ADD:G.W",
      "operands": "#H'0200, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25122,
        "changes": [],
        "notes": [
          "R5 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 25130,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25130,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25131,
      "address_region": "program_or_external",
      "bytes": "AD84",
      "text": "MOV:G.W R5, R4",
      "mnemonic": "MOV:G.W",
      "operands": "R5, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25131,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after MOV source"
        ]
      }
    },
    {
      "address": 25133,
      "address_region": "program_or_external",
      "bytes": "A512",
      "text": "EXTU.B R5",
      "mnemonic": "EXTU.B",
      "operands": "R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25131,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R5"
        ]
      }
    },
    {
      "address": 25135,
      "address_region": "program_or_external",
      "bytes": "A410",
      "text": "SWAP.B R4",
      "mnemonic": "SWAP.B",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25131,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 25137,
      "address_region": "program_or_external",
      "bytes": "040754",
      "text": "AND.B #H'07, R4",
      "mnemonic": "AND.B",
      "operands": "#H'07, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25131,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 25140,
      "address_region": "program_or_external",
      "bytes": "4400",
      "text": "CMP:E #H'00, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'00, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25131,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25142,
      "address_region": "program_or_external",
      "bytes": "270C",
      "text": "BEQ loc_6244",
      "mnemonic": "BEQ",
      "operands": "loc_6244",
      "kind": "branch",
      "targets": [
        25156
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25131,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25144,
      "address_region": "program_or_external",
      "bytes": "4401",
      "text": "CMP:E #H'01, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'01, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25144,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 25146,
      "address_region": "program_or_external",
      "bytes": "2711",
      "text": "BEQ loc_624D",
      "mnemonic": "BEQ",
      "operands": "loc_624D",
      "kind": "branch",
      "targets": [
        25165
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25144,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25148,
      "address_region": "program_or_external",
      "bytes": "4402",
      "text": "CMP:E #H'02, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'02, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25148,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 25150,
      "address_region": "program_or_external",
      "bytes": "2716",
      "text": "BEQ loc_6256",
      "mnemonic": "BEQ",
      "operands": "loc_6256",
      "kind": "branch",
      "targets": [
        25174
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25148,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25152,
      "address_region": "program_or_external",
      "bytes": "4403",
      "text": "CMP:E #H'03, R4",
      "mnemonic": "CMP:E",
      "operands": "#H'03, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25152,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 25154,
      "address_region": "program_or_external",
      "bytes": "271B",
      "text": "BEQ loc_625F",
      "mnemonic": "BEQ",
      "operands": "loc_625F",
      "kind": "branch",
      "targets": [
        25183
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25152,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25156,
      "address_region": "program_or_external",
      "bytes": "457F",
      "text": "CMP:E #H'7F, R5",
      "mnemonic": "CMP:E",
      "operands": "#H'7F, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25156,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 25158,
      "address_region": "program_or_external",
      "bytes": "2217",
      "text": "BHI loc_625F",
      "mnemonic": "BHI",
      "operands": "loc_625F",
      "kind": "branch",
      "targets": [
        25183
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25156,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25160,
      "address_region": "program_or_external",
      "bytes": "5C0000",
      "text": "MOV:I.W #H'0000, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0000, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25160,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0000"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        }
      }
    },
    {
      "address": 25163,
      "address_region": "program_or_external",
      "bytes": "2017",
      "text": "BRA loc_6264",
      "mnemonic": "BRA",
      "operands": "loc_6264",
      "kind": "jump",
      "targets": [
        25188
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25160,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "MOV:I.W #H'0000, R4"
            }
          }
        }
      }
    },
    {
      "address": 25165,
      "address_region": "program_or_external",
      "bytes": "45FF",
      "text": "CMP:E #H'FF, R5",
      "mnemonic": "CMP:E",
      "operands": "#H'FF, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25165,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 25167,
      "address_region": "program_or_external",
      "bytes": "220E",
      "text": "BHI loc_625F",
      "mnemonic": "BHI",
      "operands": "loc_625F",
      "kind": "branch",
      "targets": [
        25183
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25165,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25169,
      "address_region": "program_or_external",
      "bytes": "5C0080",
      "text": "MOV:I.W #H'0080, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0080, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25169,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0080"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R4"
            }
          }
        }
      }
    },
    {
      "address": 25172,
      "address_region": "program_or_external",
      "bytes": "200E",
      "text": "BRA loc_6264",
      "mnemonic": "BRA",
      "operands": "loc_6264",
      "kind": "jump",
      "targets": [
        25188
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25169,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 128,
              "hex": "0x0080",
              "width": 16,
              "source": "MOV:I.W #H'0080, R4"
            }
          }
        }
      }
    },
    {
      "address": 25174,
      "address_region": "program_or_external",
      "bytes": "457F",
      "text": "CMP:E #H'7F, R5",
      "mnemonic": "CMP:E",
      "operands": "#H'7F, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25174,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 25176,
      "address_region": "program_or_external",
      "bytes": "2205",
      "text": "BHI loc_625F",
      "mnemonic": "BHI",
      "operands": "loc_625F",
      "kind": "branch",
      "targets": [
        25183
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25174,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 25178,
      "address_region": "program_or_external",
      "bytes": "5C0180",
      "text": "MOV:I.W #H'0180, R4",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0180, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25178,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 384,
              "hex": "0x0180",
              "width": 16,
              "source": "MOV:I.W #H'0180, R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 = 0x0180"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 384,
              "hex": "0x0180",
              "width": 16,
              "source": "MOV:I.W #H'0180, R4"
            }
          }
        }
      }
    },
    {
      "address": 25181,
      "address_region": "program_or_external",
      "bytes": "2005",
      "text": "BRA loc_6264",
      "mnemonic": "BRA",
      "operands": "loc_6264",
      "kind": "jump",
      "targets": [
        25188
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25178,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 384,
              "hex": "0x0180",
              "width": 16,
              "source": "MOV:I.W #H'0180, R4"
            }
          }
        }
      }
    },
    {
      "address": 25183,
      "address_region": "program_or_external",
      "bytes": "AC13",
      "text": "CLR.W R4",
      "mnemonic": "CLR.W",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25183,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R4"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 cleared"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R4"
            }
          }
        }
      }
    },
    {
      "address": 25185,
      "address_region": "program_or_external",
      "bytes": "5D01FF",
      "text": "MOV:I.W #H'01FF, R5",
      "mnemonic": "MOV:I.W",
      "operands": "#H'01FF, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25183,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 511,
              "hex": "0x01FF",
              "width": 16,
              "source": "MOV:I.W #H'01FF, R5"
            }
          }
        ],
        "notes": [
          "R5 = 0x01FF"
        ],
        "known_after": {
          "registers": {
            "R4": {
              "known": true,
              "value": 0,
              "hex": "0x0000",
              "width": 16,
              "source": "CLR.W R4"
            },
            "R5": {
              "known": true,
              "value": 511,
              "hex": "0x01FF",
              "width": 16,
              "source": "MOV:I.W #H'01FF, R5"
            }
          }
        }
      }
    },
    {
      "address": 25188,
      "address_region": "program_or_external",
      "bytes": "AC25",
      "text": "ADD:G.W R4, R5",
      "mnemonic": "ADD:G.W",
      "operands": "R4, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25188,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 25190,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 25188,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47654,
      "address_region": "program_or_external",
      "bytes": "15F9C016",
      "text": "TST.B @H'F9C0",
      "mnemonic": "TST.B",
      "operands": "@H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47654,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47658,
      "address_region": "program_or_external",
      "bytes": "26FA",
      "text": "BNE loc_BA26",
      "mnemonic": "BNE",
      "operands": "loc_BA26",
      "kind": "branch",
      "targets": [
        47654
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47654,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47660,
      "address_region": "program_or_external",
      "bytes": "15F9C00664",
      "text": "MOV:G.B #H'64, @H'F9C0",
      "mnemonic": "MOV:G.B",
      "operands": "#H'64, @H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47660,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47665,
      "address_region": "program_or_external",
      "bytes": "15F9C40607",
      "text": "MOV:G.B #H'07, @H'F9C4",
      "mnemonic": "MOV:G.B",
      "operands": "#H'07, @H'F9C4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63940,
          "name": null,
          "symbol": "ram_F9C4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47670,
      "address_region": "program_or_external",
      "bytes": "1DF85080",
      "text": "MOV:G.W @H'F850, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F850, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63568,
          "name": null,
          "symbol": "ram_F850",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47660,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 47674,
      "address_region": "program_or_external",
      "bytes": "1DF85890",
      "text": "MOV:G.W R0, @H'F858",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F858",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63576,
          "name": null,
          "symbol": "ram_F858",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47674,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47678,
      "address_region": "program_or_external",
      "bytes": "1DF85280",
      "text": "MOV:G.W @H'F852, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F852, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63570,
          "name": null,
          "symbol": "ram_F852",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 47682,
      "address_region": "program_or_external",
      "bytes": "1DF85A90",
      "text": "MOV:G.W R0, @H'F85A",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F85A",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63578,
          "name": null,
          "symbol": "ram_F85A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47682,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47686,
      "address_region": "program_or_external",
      "bytes": "15F85480",
      "text": "MOV:G.B @H'F854, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F854, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63572,
          "name": null,
          "symbol": "ram_F854",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 47690,
      "address_region": "program_or_external",
      "bytes": "15F85C90",
      "text": "MOV:G.B R0, @H'F85C",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F85C",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63580,
          "name": null,
          "symbol": "ram_F85C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47690,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47694,
      "address_region": "program_or_external",
      "bytes": "505A",
      "text": "MOV:E.B #H'5A, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'5A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47694,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_checksum_seed",
          "evidence_summary": "candidate TX checksum starts from seed H'005A",
          "evidence_addresses": [
            47694
          ],
          "evidence_addresses_hex": [
            "H'BA4E"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX checksum starts from seed H'005A; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": true,
              "value": 90,
              "hex": "0x5A",
              "width": 8,
              "source": "MOV:E.B #H'5A, R0"
            }
          }
        ],
        "notes": [
          "R0 = 0x5A"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 90,
              "hex": "0x5A",
              "width": 8,
              "source": "MOV:E.B #H'5A, R0"
            }
          }
        }
      }
    },
    {
      "address": 47696,
      "address_region": "program_or_external",
      "bytes": "15F85860",
      "text": "XOR.B @H'F858, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F858, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63576,
          "name": null,
          "symbol": "ram_F858",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47696,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        },
        {
          "address": 47696,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "xor_checksum_chain",
          "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte",
          "evidence_addresses": [
            47696,
            47700,
            47704,
            47708,
            47712,
            47716
          ],
          "evidence_addresses_hex": [
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": true,
              "value": 90,
              "hex": "0x5A",
              "width": 8,
              "source": "MOV:E.B #H'5A, R0"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 47700,
      "address_region": "program_or_external",
      "bytes": "15F85960",
      "text": "XOR.B @H'F859, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F859, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63577,
          "name": null,
          "symbol": "ram_F859",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47700,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        },
        {
          "address": 47700,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "xor_checksum_chain",
          "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte",
          "evidence_addresses": [
            47696,
            47700,
            47704,
            47708,
            47712,
            47716
          ],
          "evidence_addresses_hex": [
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 47704,
      "address_region": "program_or_external",
      "bytes": "15F85A60",
      "text": "XOR.B @H'F85A, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F85A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63578,
          "name": null,
          "symbol": "ram_F85A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47704,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        },
        {
          "address": 47704,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "xor_checksum_chain",
          "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte",
          "evidence_addresses": [
            47696,
            47700,
            47704,
            47708,
            47712,
            47716
          ],
          "evidence_addresses_hex": [
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 47708,
      "address_region": "program_or_external",
      "bytes": "15F85B60",
      "text": "XOR.B @H'F85B, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F85B, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63579,
          "name": null,
          "symbol": "ram_F85B",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47708,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        },
        {
          "address": 47708,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "xor_checksum_chain",
          "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte",
          "evidence_addresses": [
            47696,
            47700,
            47704,
            47708,
            47712,
            47716
          ],
          "evidence_addresses_hex": [
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 47712,
      "address_region": "program_or_external",
      "bytes": "15F85C60",
      "text": "XOR.B @H'F85C, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F85C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63580,
          "name": null,
          "symbol": "ram_F85C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47712,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        },
        {
          "address": 47712,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "xor_checksum_chain",
          "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte",
          "evidence_addresses": [
            47696,
            47700,
            47704,
            47708,
            47712,
            47716
          ],
          "evidence_addresses_hex": [
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 47716,
      "address_region": "program_or_external",
      "bytes": "15F85D90",
      "text": "MOV:G.B R0, @H'F85D",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F85D",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63581,
          "name": null,
          "symbol": "ram_F85D",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47716,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        },
        {
          "address": 47716,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "checksum_byte",
          "evidence_summary": "candidate checksum byte write targets H'F85D",
          "evidence_addresses": [
            47716
          ],
          "evidence_addresses_hex": [
            "H'BA64"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate checksum byte write targets H'F85D; confidence high"
        },
        {
          "address": 47716,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "xor_checksum_chain",
          "evidence_summary": "XOR chain appears to feed the H'F85D checksum byte",
          "evidence_addresses": [
            47696,
            47700,
            47704,
            47708,
            47712,
            47716
          ],
          "evidence_addresses_hex": [
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: XOR chain appears to feed the H'F85D checksum byte; confidence high"
        }
      ],
      "dataflow": {
        "block": 47660,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47720,
      "address_region": "program_or_external",
      "bytes": "15FEDCF7",
      "text": "BTST.B #7, @SCI1_SSR",
      "mnemonic": "BTST.B",
      "operands": "#7, @SCI1_SSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65244,
          "name": "SCI1_SSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47720,
          "instruction": "BTST.B #7, @SCI1_SSR",
          "action": "wait_for_tdre",
          "channel": "SCI1",
          "register": "SSR",
          "register_address": 65244,
          "register_address_hex": "H'FEDC",
          "comment": "wait for SCI1 transmit data register empty (TDRE=1)",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 7,
          "flag": "TDRE",
          "branch_address": 47724,
          "branch_target": 47720
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47720,
            "instruction": "BTST.B #7, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "read",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "dataflow": {
        "block": 47720,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47724,
      "address_region": "program_or_external",
      "bytes": "27FA",
      "text": "BEQ loc_BA68",
      "mnemonic": "BEQ",
      "operands": "loc_BA68",
      "kind": "branch",
      "targets": [
        47720
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47724,
          "instruction": "BEQ loc_BA68",
          "action": "tdre_wait_branch",
          "channel": "SCI1",
          "register": "SSR",
          "register_address": 65244,
          "register_address_hex": "H'FEDC",
          "comment": "repeat SCI1 transmit-empty wait while TDRE=0",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 7,
          "flag": "TDRE",
          "test_address": 47720,
          "branch_target": 47720
        }
      ],
      "dataflow": {
        "block": 47720,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47726,
      "address_region": "program_or_external",
      "bytes": "15F85880",
      "text": "MOV:G.B @H'F858, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F858, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63576,
          "name": null,
          "symbol": "ram_F858",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47726,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        },
        {
          "address": 47726,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "initial_send_from_buffer_start",
          "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858",
          "evidence_addresses": [
            47726,
            47730
          ],
          "evidence_addresses_hex": [
            "H'BA6E",
            "H'BA72"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high"
        }
      ],
      "dataflow": {
        "block": 47726,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 47730,
      "address_region": "program_or_external",
      "bytes": "15FEDB90",
      "text": "MOV:G.B R0, @SCI1_TDR",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @SCI1_TDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65243,
          "name": "SCI1_TDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SCI1_TDR",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47730,
          "instruction": "MOV:G.B R0, @SCI1_TDR",
          "action": "write_tdr",
          "channel": "SCI1",
          "register": "TDR",
          "register_address": 65243,
          "register_address_hex": "H'FEDB",
          "comment": "write RS232/SCI byte to SCI1 TDR for transmission",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ]
        }
      ],
      "serial_reconstruction": [
        {
          "address": 47730,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "initial_send_from_buffer_start",
          "evidence_summary": "initial SCI1 TDR send is supported by a read from H'F858",
          "evidence_addresses": [
            47726,
            47730
          ],
          "evidence_addresses_hex": [
            "H'BA6E",
            "H'BA72"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: initial SCI1 TDR send is supported by a read from H'F858; confidence high"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47730,
            "instruction": "MOV:G.B R0, @SCI1_TDR",
            "channel": "SCI1",
            "register": "TDR",
            "register_address": 65243,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
          }
        ],
        "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
      },
      "dataflow": {
        "block": 47726,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47734,
      "address_region": "program_or_external",
      "bytes": "15F9C20601",
      "text": "MOV:G.B #H'01, @H'F9C2",
      "mnemonic": "MOV:G.B",
      "operands": "#H'01, @H'F9C2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63938,
          "name": null,
          "symbol": "ram_F9C2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47734,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_index_initialized_to_one",
          "evidence_summary": "write evidence supports TX index H'F9C2 being initialized to 1",
          "evidence_addresses": [
            47734
          ],
          "evidence_addresses_hex": [
            "H'BA76"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: write evidence supports TX index H'F9C2 being initialized to 1; confidence high"
        }
      ],
      "dataflow": {
        "block": 47726,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47739,
      "address_region": "program_or_external",
      "bytes": "15FEDCD7",
      "text": "BCLR.B #7, @SCI1_SSR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @SCI1_SSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65244,
          "name": "SCI1_SSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear TDRE (bit 7) of SCI1_SSR",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47739,
          "instruction": "BCLR.B #7, @SCI1_SSR",
          "action": "clear_tdre",
          "channel": "SCI1",
          "register": "SSR",
          "register_address": 65244,
          "register_address_hex": "H'FEDC",
          "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 7,
          "flag": "TDRE",
          "description": "transmit data register empty"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47739,
            "instruction": "BCLR.B #7, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "dataflow": {
        "block": 47726,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47743,
      "address_region": "program_or_external",
      "bytes": "15FEDAC7",
      "text": "BSET.B #7, @SCI1_SCR",
      "mnemonic": "BSET.B",
      "operands": "#7, @SCI1_SCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65242,
          "name": "SCI1_SCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set TIE (bit 7) of SCI1_SCR",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 47743,
            "instruction": "BSET.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "BSET",
            "value": 252,
            "value_hex": "H'FC"
          }
        ]
      },
      "sci_protocol": [
        {
          "address": 47743,
          "instruction": "BSET.B #7, @SCI1_SCR",
          "action": "enable_tx_interrupt",
          "channel": "SCI1",
          "register": "SCR",
          "register_address": 65242,
          "register_address_hex": "H'FEDA",
          "comment": "enable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 7,
          "bit_name": "TIE",
          "enabled": true,
          "interrupt_source": "TXI"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47743,
            "instruction": "BSET.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 252,
            "value_hex": "H'FC",
            "scr": {
              "value": 252,
              "value_hex": "H'FC",
              "tie": true,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "dataflow": {
        "block": 47726,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47747,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47726,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47748,
      "address_region": "program_or_external",
      "bytes": "15FAA2F3",
      "text": "BTST.B #3, @H'FAA2",
      "mnemonic": "BTST.B",
      "operands": "#3, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47748,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47752,
      "address_region": "program_or_external",
      "bytes": "271F",
      "text": "BEQ loc_BAA9",
      "mnemonic": "BEQ",
      "operands": "loc_BAA9",
      "kind": "branch",
      "targets": [
        47785
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47748,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47754,
      "address_region": "program_or_external",
      "bytes": "15FAA5F7",
      "text": "BTST.B #7, @H'FAA5",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FAA5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64165,
          "name": null,
          "symbol": "ram_FAA5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47754,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47758,
      "address_region": "program_or_external",
      "bytes": "2719",
      "text": "BEQ loc_BAA9",
      "mnemonic": "BEQ",
      "operands": "loc_BAA9",
      "kind": "branch",
      "targets": [
        47785
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47754,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47760,
      "address_region": "program_or_external",
      "bytes": "15F9C316",
      "text": "TST.B @H'F9C3",
      "mnemonic": "TST.B",
      "operands": "@H'F9C3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47760,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47764,
      "address_region": "program_or_external",
      "bytes": "2713",
      "text": "BEQ loc_BAA9",
      "mnemonic": "BEQ",
      "operands": "loc_BAA9",
      "kind": "branch",
      "targets": [
        47785
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47760,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47766,
      "address_region": "program_or_external",
      "bytes": "15FAA2D3",
      "text": "BCLR.B #3, @H'FAA2",
      "mnemonic": "BCLR.B",
      "operands": "#3, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47766,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47770,
      "address_region": "program_or_external",
      "bytes": "15FAA313",
      "text": "CLR.B @H'FAA3",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64163,
          "name": null,
          "symbol": "ram_FAA3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47766,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47774,
      "address_region": "program_or_external",
      "bytes": "15FEDAD7",
      "text": "BCLR.B #7, @SCI1_SCR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @SCI1_SCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65242,
          "name": "SCI1_SCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear TIE (bit 7) of SCI1_SCR",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 47774,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "BCLR",
            "value": 124,
            "value_hex": "H'7C"
          }
        ]
      },
      "sci_protocol": [
        {
          "address": 47774,
          "instruction": "BCLR.B #7, @SCI1_SCR",
          "action": "disable_tx_interrupt",
          "channel": "SCI1",
          "register": "SCR",
          "register_address": 65242,
          "register_address_hex": "H'FEDA",
          "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 7,
          "bit_name": "TIE",
          "enabled": false,
          "interrupt_source": "TXI"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47774,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 124,
            "value_hex": "H'7C",
            "scr": {
              "value": 124,
              "value_hex": "H'7C",
              "tie": false,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "dataflow": {
        "block": 47766,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47778,
      "address_region": "program_or_external",
      "bytes": "15F9C0061F",
      "text": "MOV:G.B #H'1F, @H'F9C0",
      "mnemonic": "MOV:G.B",
      "operands": "#H'1F, @H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47766,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47783,
      "address_region": "program_or_external",
      "bytes": "2048",
      "text": "BRA loc_BAF1",
      "mnemonic": "BRA",
      "operands": "loc_BAF1",
      "kind": "jump",
      "targets": [
        47857
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47766,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47785,
      "address_region": "program_or_external",
      "bytes": "BF90",
      "text": "MOV:G.W R0, @-R7",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @-R7",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 5,
        "base_cycles": 5,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47785,
        "changes": [
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "addressing_side_effect"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47787,
      "address_region": "program_or_external",
      "bytes": "15F9C280",
      "text": "MOV:G.B @H'F9C2, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9C2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63938,
          "name": null,
          "symbol": "ram_F9C2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47787,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_isr_indexed_send",
          "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer",
          "evidence_addresses": [
            47787,
            47793,
            47797
          ],
          "evidence_addresses_hex": [
            "H'BAAB",
            "H'BAB1",
            "H'BAB5"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high"
        }
      ],
      "dataflow": {
        "block": 47785,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 47791,
      "address_region": "program_or_external",
      "bytes": "A012",
      "text": "EXTU.B R0",
      "mnemonic": "EXTU.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47785,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 47793,
      "address_region": "program_or_external",
      "bytes": "F0F85880",
      "text": "MOV:G.B @(-H'07A8,R0), R0",
      "mnemonic": "MOV:G.B",
      "operands": "@(-H'07A8,R0), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47793,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_isr_indexed_send",
          "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer",
          "evidence_addresses": [
            47787,
            47793,
            47797
          ],
          "evidence_addresses_hex": [
            "H'BAAB",
            "H'BAB1",
            "H'BAB5"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high"
        }
      ],
      "dataflow": {
        "block": 47785,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 47797,
      "address_region": "program_or_external",
      "bytes": "15FEDB90",
      "text": "MOV:G.B R0, @SCI1_TDR",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @SCI1_TDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65243,
          "name": "SCI1_TDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "SCI1_TDR",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47797,
          "instruction": "MOV:G.B R0, @SCI1_TDR",
          "action": "write_tdr",
          "channel": "SCI1",
          "register": "TDR",
          "register_address": 65243,
          "register_address_hex": "H'FEDB",
          "comment": "write RS232/SCI byte to SCI1 TDR for transmission",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ]
        }
      ],
      "serial_reconstruction": [
        {
          "address": 47797,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_isr_indexed_send",
          "evidence_summary": "candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer",
          "evidence_addresses": [
            47787,
            47793,
            47797
          ],
          "evidence_addresses_hex": [
            "H'BAAB",
            "H'BAB1",
            "H'BAB5"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR sends SCI1 TDR from indexed H'F858 buffer; confidence high"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47797,
            "instruction": "MOV:G.B R0, @SCI1_TDR",
            "channel": "SCI1",
            "register": "TDR",
            "register_address": 65243,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
          }
        ],
        "comment": "SCI1 TDR write transmits on traced RS232/MAX202 path: H8 pin 66 P95/TXD -> MAX202 pin 11"
      },
      "dataflow": {
        "block": 47785,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47801,
      "address_region": "program_or_external",
      "bytes": "CF80",
      "text": "MOV:G.W @R7+, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@R7+, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 5,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47785,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 47803,
      "address_region": "program_or_external",
      "bytes": "15FEDCD7",
      "text": "BCLR.B #7, @SCI1_SSR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @SCI1_SSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65244,
          "name": "SCI1_SSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear TDRE (bit 7) of SCI1_SSR",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47803,
          "instruction": "BCLR.B #7, @SCI1_SSR",
          "action": "clear_tdre",
          "channel": "SCI1",
          "register": "SSR",
          "register_address": 65244,
          "register_address_hex": "H'FEDC",
          "comment": "clear SCI1 TDRE after TDR write; TXI can fire again when hardware reasserts TDRE",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 7,
          "flag": "TDRE",
          "description": "transmit data register empty"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47803,
            "instruction": "BCLR.B #7, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "dataflow": {
        "block": 47785,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47807,
      "address_region": "program_or_external",
      "bytes": "15F9C208",
      "text": "ADD:Q.B #1, @H'F9C2",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F9C2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63938,
          "name": null,
          "symbol": "ram_F9C2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47807,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_index_increment",
          "evidence_summary": "candidate TX ISR increments TX index H'F9C2",
          "evidence_addresses": [
            47807
          ],
          "evidence_addresses_hex": [
            "H'BABF"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR increments TX index H'F9C2; confidence high"
        }
      ],
      "dataflow": {
        "block": 47785,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47811,
      "address_region": "program_or_external",
      "bytes": "15F9C20406",
      "text": "CMP:G.B #H'06, @H'F9C2",
      "mnemonic": "CMP:G.B",
      "operands": "#H'06, @H'F9C2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63938,
          "name": null,
          "symbol": "ram_F9C2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47811,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_index_compare_frame_length",
          "evidence_summary": "candidate TX ISR compares TX index to frame length 6",
          "evidence_addresses": [
            47811
          ],
          "evidence_addresses_hex": [
            "H'BAC3"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: candidate TX ISR compares TX index to frame length 6; confidence high"
        }
      ],
      "dataflow": {
        "block": 47785,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47816,
      "address_region": "program_or_external",
      "bytes": "2627",
      "text": "BNE loc_BAF1",
      "mnemonic": "BNE",
      "operands": "loc_BAF1",
      "kind": "branch",
      "targets": [
        47857
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47785,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47818,
      "address_region": "program_or_external",
      "bytes": "15FEDAD7",
      "text": "BCLR.B #7, @SCI1_SCR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @SCI1_SCR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65242,
          "name": "SCI1_SCR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear TIE (bit 7) of SCI1_SCR",
      "valid": true,
      "sci": {
        "writes": [
          {
            "address": 47818,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "operation": "BCLR",
            "value": 124,
            "value_hex": "H'7C"
          }
        ]
      },
      "sci_protocol": [
        {
          "address": 47818,
          "instruction": "BCLR.B #7, @SCI1_SCR",
          "action": "disable_tx_interrupt",
          "channel": "SCI1",
          "register": "SCR",
          "register_address": 65242,
          "register_address_hex": "H'FEDA",
          "comment": "disable SCI1 TX interrupt (TIE); gates TXI when hardware sets TDRE",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 7,
          "bit_name": "TIE",
          "enabled": false,
          "interrupt_source": "TXI"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47818,
            "instruction": "BCLR.B #7, @SCI1_SCR",
            "channel": "SCI1",
            "register": "SCR",
            "register_address": 65242,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)",
            "value": 124,
            "value_hex": "H'7C",
            "scr": {
              "value": 124,
              "value_hex": "H'7C",
              "tie": false,
              "rie": true,
              "tx_enabled": true,
              "rx_enabled": true
            }
          }
        ],
        "comment": "SCI1 SCR write TE=1 RE=1; TE/RE select the traced RS232/MAX202 pins (P95/TXD pin 66 to MAX202 pin 11, P96/RXD pin 67 to MAX202 pin 12)"
      },
      "dataflow": {
        "block": 47818,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47822,
      "address_region": "program_or_external",
      "bytes": "15F795F6",
      "text": "BTST.B #6, @H'F795",
      "mnemonic": "BTST.B",
      "operands": "#6, @H'F795",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63381,
          "name": null,
          "symbol": "ram_F795",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47818,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47826,
      "address_region": "program_or_external",
      "bytes": "2614",
      "text": "BNE loc_BAE8",
      "mnemonic": "BNE",
      "operands": "loc_BAE8",
      "kind": "branch",
      "targets": [
        47848
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47818,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47828,
      "address_region": "program_or_external",
      "bytes": "15F791F7",
      "text": "BTST.B #7, @H'F791",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F791",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63377,
          "name": null,
          "symbol": "ram_F791",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47828,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47832,
      "address_region": "program_or_external",
      "bytes": "2607",
      "text": "BNE loc_BAE1",
      "mnemonic": "BNE",
      "operands": "loc_BAE1",
      "kind": "branch",
      "targets": [
        47841
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47828,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47834,
      "address_region": "program_or_external",
      "bytes": "15F9C00609",
      "text": "MOV:G.B #H'09, @H'F9C0",
      "mnemonic": "MOV:G.B",
      "operands": "#H'09, @H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47834,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47839,
      "address_region": "program_or_external",
      "bytes": "200C",
      "text": "BRA loc_BAED",
      "mnemonic": "BRA",
      "operands": "loc_BAED",
      "kind": "jump",
      "targets": [
        47853
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47834,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47841,
      "address_region": "program_or_external",
      "bytes": "15F9C00609",
      "text": "MOV:G.B #H'09, @H'F9C0",
      "mnemonic": "MOV:G.B",
      "operands": "#H'09, @H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47841,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47846,
      "address_region": "program_or_external",
      "bytes": "2005",
      "text": "BRA loc_BAED",
      "mnemonic": "BRA",
      "operands": "loc_BAED",
      "kind": "jump",
      "targets": [
        47853
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47841,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47848,
      "address_region": "program_or_external",
      "bytes": "15F9C006F0",
      "text": "MOV:G.B #H'F0, @H'F9C0",
      "mnemonic": "MOV:G.B",
      "operands": "#H'F0, @H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47848,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47853,
      "address_region": "program_or_external",
      "bytes": "15F9C113",
      "text": "CLR.B @H'F9C1",
      "mnemonic": "CLR.B",
      "operands": "@H'F9C1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63937,
          "name": null,
          "symbol": "ram_F9C1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47853,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47857,
      "address_region": "program_or_external",
      "bytes": "0A",
      "text": "RTE",
      "mnemonic": "RTE",
      "operands": "",
      "kind": "rte",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "base_cycles": 13,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47857,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47858,
      "address_region": "program_or_external",
      "bytes": "15F9B581",
      "text": "MOV:G.B @H'F9B5, R1",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B5, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47858,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 47862,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47858,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 47864,
      "address_region": "program_or_external",
      "bytes": "15F9B071",
      "text": "CMP:G.B @H'F9B0, R1",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F9B0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63920,
          "name": null,
          "symbol": "ram_F9B0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47858,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47868,
      "address_region": "program_or_external",
      "bytes": "2602",
      "text": "BNE loc_BB00",
      "mnemonic": "BNE",
      "operands": "loc_BB00",
      "kind": "branch",
      "targets": [
        47872
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47858,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47870,
      "address_region": "program_or_external",
      "bytes": "2056",
      "text": "BRA loc_BB56",
      "mnemonic": "BRA",
      "operands": "loc_BB56",
      "kind": "jump",
      "targets": [
        47958
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47870,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47872,
      "address_region": "program_or_external",
      "bytes": "15FAA2C3",
      "text": "BSET.B #3, @H'FAA2",
      "mnemonic": "BSET.B",
      "operands": "#3, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47876,
      "address_region": "program_or_external",
      "bytes": "A980",
      "text": "MOV:G.W R1, R0",
      "mnemonic": "MOV:G.W",
      "operands": "R1, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 47878,
      "address_region": "program_or_external",
      "bytes": "A81A",
      "text": "SHLL.W R0",
      "mnemonic": "SHLL.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 47880,
      "address_region": "program_or_external",
      "bytes": "F8F87080",
      "text": "MOV:G.W @(-H'0790,R0), R0",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'0790,R0), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 47884,
      "address_region": "program_or_external",
      "bytes": "A885",
      "text": "MOV:G.W R0, R5",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R5 unknown after MOV source"
        ]
      }
    },
    {
      "address": 47886,
      "address_region": "program_or_external",
      "bytes": "1EA6F5",
      "text": "BSR loc_6206",
      "mnemonic": "BSR",
      "operands": "loc_6206",
      "kind": "call",
      "targets": [
        25094
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 47889,
      "address_region": "program_or_external",
      "bytes": "A881",
      "text": "MOV:G.W R0, R1",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after MOV source"
        ]
      }
    },
    {
      "address": 47891,
      "address_region": "program_or_external",
      "bytes": "A110",
      "text": "SWAP.B R1",
      "mnemonic": "SWAP.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 47893,
      "address_region": "program_or_external",
      "bytes": "A11B",
      "text": "SHLR.B R1",
      "mnemonic": "SHLR.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 47895,
      "address_region": "program_or_external",
      "bytes": "A182",
      "text": "MOV:G.B R1, R2",
      "mnemonic": "MOV:G.B",
      "operands": "R1, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R2 unknown after MOV source"
        ]
      }
    },
    {
      "address": 47897,
      "address_region": "program_or_external",
      "bytes": "040751",
      "text": "AND.B #H'07, R1",
      "mnemonic": "AND.B",
      "operands": "#H'07, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:SHLR.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 47900,
      "address_region": "program_or_external",
      "bytes": "15F85091",
      "text": "MOV:G.B R1, @H'F850",
      "mnemonic": "MOV:G.B",
      "operands": "R1, @H'F850",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63568,
          "name": null,
          "symbol": "ram_F850",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47904,
      "address_region": "program_or_external",
      "bytes": "15F85295",
      "text": "MOV:G.B R5, @H'F852",
      "mnemonic": "MOV:G.B",
      "operands": "R5, @H'F852",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63570,
          "name": null,
          "symbol": "ram_F852",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47908,
      "address_region": "program_or_external",
      "bytes": "A510",
      "text": "SWAP.B R5",
      "mnemonic": "SWAP.B",
      "operands": "R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R5"
        ]
      }
    },
    {
      "address": 47910,
      "address_region": "program_or_external",
      "bytes": "047852",
      "text": "AND.B #H'78, R2",
      "mnemonic": "AND.B",
      "operands": "#H'78, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R2"
        ]
      }
    },
    {
      "address": 47913,
      "address_region": "program_or_external",
      "bytes": "A245",
      "text": "OR.B R2, R5",
      "mnemonic": "OR.B",
      "operands": "R2, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R5"
        ]
      }
    },
    {
      "address": 47915,
      "address_region": "program_or_external",
      "bytes": "15F85195",
      "text": "MOV:G.B R5, @H'F851",
      "mnemonic": "MOV:G.B",
      "operands": "R5, @H'F851",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63569,
          "name": null,
          "symbol": "ram_F851",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47919,
      "address_region": "program_or_external",
      "bytes": "0C01FF50",
      "text": "AND.W #H'01FF, R0",
      "mnemonic": "AND.W",
      "operands": "#H'01FF, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 47923,
      "address_region": "program_or_external",
      "bytes": "A81A",
      "text": "SHLL.W R0",
      "mnemonic": "SHLL.W",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:AND.W"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 47925,
      "address_region": "program_or_external",
      "bytes": "F8E80084",
      "text": "MOV:G.W @(-H'1800,R0), R4",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'1800,R0), R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 47929,
      "address_region": "program_or_external",
      "bytes": "15F85494",
      "text": "MOV:G.B R4, @H'F854",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F854",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63572,
          "name": null,
          "symbol": "ram_F854",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47933,
      "address_region": "program_or_external",
      "bytes": "A410",
      "text": "SWAP.B R4",
      "mnemonic": "SWAP.B",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 47935,
      "address_region": "program_or_external",
      "bytes": "15F85394",
      "text": "MOV:G.B R4, @H'F853",
      "mnemonic": "MOV:G.B",
      "operands": "R4, @H'F853",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63571,
          "name": null,
          "symbol": "ram_F853",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47939,
      "address_region": "program_or_external",
      "bytes": "1EFEE0",
      "text": "BSR loc_BA26",
      "mnemonic": "BSR",
      "operands": "loc_BA26",
      "kind": "call",
      "targets": [
        47654
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "unsupported:OR.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 47942,
      "address_region": "program_or_external",
      "bytes": "1DF9C60701F4",
      "text": "MOV:G.W #H'01F4, @H'F9C6",
      "mnemonic": "MOV:G.W",
      "operands": "#H'01F4, @H'F9C6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63942,
          "name": null,
          "symbol": "ram_F9C6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47948,
      "address_region": "program_or_external",
      "bytes": "15F9C80614",
      "text": "MOV:G.B #H'14, @H'F9C8",
      "mnemonic": "MOV:G.B",
      "operands": "#H'14, @H'F9C8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63944,
          "name": null,
          "symbol": "ram_F9C8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47953,
      "address_region": "program_or_external",
      "bytes": "15FAA30680",
      "text": "MOV:G.B #H'80, @H'FAA3",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'FAA3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64163,
          "name": null,
          "symbol": "ram_FAA3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47872,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47958,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47958,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47959,
      "address_region": "program_or_external",
      "bytes": "15FAA4C7",
      "text": "BSET.B #7, @H'FAA4",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'FAA4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64164,
          "name": null,
          "symbol": "ram_FAA4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 47959,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_eri_falls_through_to_rxi",
          "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path",
          "evidence_addresses": [
            47959,
            47963,
            47967,
            47971,
            47977,
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB57",
            "H'BB5B",
            "H'BB5F",
            "H'BB63",
            "H'BB69",
            "H'BB6D"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high"
        }
      ],
      "dataflow": {
        "block": 47959,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47963,
      "address_region": "program_or_external",
      "bytes": "15FEDCD5",
      "text": "BCLR.B #5, @SCI1_SSR",
      "mnemonic": "BCLR.B",
      "operands": "#5, @SCI1_SSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65244,
          "name": "SCI1_SSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear ORER (bit 5) of SCI1_SSR",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47963,
          "instruction": "BCLR.B #5, @SCI1_SSR",
          "action": "clear_orer",
          "channel": "SCI1",
          "register": "SSR",
          "register_address": 65244,
          "register_address_hex": "H'FEDC",
          "comment": "clear SCI1 ORER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 5,
          "flag": "ORER",
          "description": "overrun error"
        }
      ],
      "serial_reconstruction": [
        {
          "address": 47963,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_eri_falls_through_to_rxi",
          "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path",
          "evidence_addresses": [
            47959,
            47963,
            47967,
            47971,
            47977,
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB57",
            "H'BB5B",
            "H'BB5F",
            "H'BB63",
            "H'BB69",
            "H'BB6D"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47963,
            "instruction": "BCLR.B #5, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "dataflow": {
        "block": 47959,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47967,
      "address_region": "program_or_external",
      "bytes": "15FEDCD4",
      "text": "BCLR.B #4, @SCI1_SSR",
      "mnemonic": "BCLR.B",
      "operands": "#4, @SCI1_SSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65244,
          "name": "SCI1_SSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear FER (bit 4) of SCI1_SSR",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47967,
          "instruction": "BCLR.B #4, @SCI1_SSR",
          "action": "clear_fer",
          "channel": "SCI1",
          "register": "SSR",
          "register_address": 65244,
          "register_address_hex": "H'FEDC",
          "comment": "clear SCI1 FER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 4,
          "flag": "FER",
          "description": "framing error"
        }
      ],
      "serial_reconstruction": [
        {
          "address": 47967,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_eri_falls_through_to_rxi",
          "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path",
          "evidence_addresses": [
            47959,
            47963,
            47967,
            47971,
            47977,
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB57",
            "H'BB5B",
            "H'BB5F",
            "H'BB63",
            "H'BB69",
            "H'BB6D"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47967,
            "instruction": "BCLR.B #4, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "dataflow": {
        "block": 47959,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47971,
      "address_region": "program_or_external",
      "bytes": "15FEDCD3",
      "text": "BCLR.B #3, @SCI1_SSR",
      "mnemonic": "BCLR.B",
      "operands": "#3, @SCI1_SSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65244,
          "name": "SCI1_SSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear PER (bit 3) of SCI1_SSR",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47971,
          "instruction": "BCLR.B #3, @SCI1_SSR",
          "action": "clear_per",
          "channel": "SCI1",
          "register": "SSR",
          "register_address": 65244,
          "register_address_hex": "H'FEDC",
          "comment": "clear SCI1 PER with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 3,
          "flag": "PER",
          "description": "parity error"
        }
      ],
      "serial_reconstruction": [
        {
          "address": 47971,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_eri_falls_through_to_rxi",
          "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path",
          "evidence_addresses": [
            47959,
            47963,
            47967,
            47971,
            47977,
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB57",
            "H'BB5B",
            "H'BB5F",
            "H'BB63",
            "H'BB69",
            "H'BB6D"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47971,
            "instruction": "BCLR.B #3, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "dataflow": {
        "block": 47959,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47975,
      "address_region": "program_or_external",
      "bytes": "1203",
      "text": "STM.W {R0,R1}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R1}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "note": "6+3n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47975,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47977,
      "address_region": "program_or_external",
      "bytes": "15FEDCD6",
      "text": "BCLR.B #6, @SCI1_SSR",
      "mnemonic": "BCLR.B",
      "operands": "#6, @SCI1_SSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65244,
          "name": "SCI1_SSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear RDRF (bit 6) of SCI1_SSR",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47977,
          "instruction": "BCLR.B #6, @SCI1_SSR",
          "action": "clear_rdrf",
          "channel": "SCI1",
          "register": "SSR",
          "register_address": 65244,
          "register_address_hex": "H'FEDC",
          "comment": "clear SCI1 RDRF with SSR R/(W)* semantics: write 0 clears latched hardware flag, write 1 preserves hardware-owned state",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ],
          "bit": 6,
          "flag": "RDRF",
          "description": "receive-data-full"
        }
      ],
      "serial_reconstruction": [
        {
          "address": 47977,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_rdrf_clear_before_rdr_read",
          "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence",
          "evidence_addresses": [
            47977,
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB69",
            "H'BB6D"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high"
        },
        {
          "address": 47977,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_eri_falls_through_to_rxi",
          "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path",
          "evidence_addresses": [
            47959,
            47963,
            47967,
            47971,
            47977,
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB57",
            "H'BB5B",
            "H'BB5F",
            "H'BB63",
            "H'BB69",
            "H'BB6D"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47977,
            "instruction": "BCLR.B #6, @SCI1_SSR",
            "channel": "SCI1",
            "register": "SSR",
            "register_address": 65244,
            "access": "write",
            "traced_to_max202": true,
            "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
          }
        ],
        "comment": "SCI1 SSR status for traced RS232/MAX202 path; TDRE/RDRF/error flags gate TDR/RDR use"
      },
      "dataflow": {
        "block": 47975,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47981,
      "address_region": "program_or_external",
      "bytes": "15FEDD80",
      "text": "MOV:G.B @SCI1_RDR, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@SCI1_RDR, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65245,
          "name": "SCI1_RDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "sci_protocol": [
        {
          "address": 47981,
          "instruction": "MOV:G.B @SCI1_RDR, R0",
          "action": "read_rdr",
          "channel": "SCI1",
          "register": "RDR",
          "register_address": 65245,
          "register_address_hex": "H'FEDD",
          "comment": "read SCI1 received byte from RDR",
          "manual": [
            "Manual/0900766b802125d0.md:15748 SCI register map for RDR/TDR/SCR/SSR",
            "Manual/0900766b802125d0.md:15794 RDR stores received data and is CPU-readable",
            "Manual/0900766b802125d0.md:15823 TDR holds the next byte to transmit",
            "Manual/0900766b802125d0.md:15976 SCR.TIE enables/disables TXI on TDRE",
            "Manual/0900766b802125d0.md:15993 SCR.RIE enables RXI and ERI",
            "Manual/0900766b802125d0.md:16008 SCR.TE enables the transmitter",
            "Manual/0900766b802125d0.md:16028 SCR.RE enables the receiver",
            "Manual/0900766b802125d0.md:16090 SSR flags are cleared by writing zero",
            "Manual/0900766b802125d0.md:16100 SSR.TDRE means TDR can accept the next byte",
            "Manual/0900766b802125d0.md:16116 SSR.RDRF means received data reached RDR",
            "Manual/0900766b802125d0.md:16127 SSR.ORER reports receive overrun",
            "Manual/0900766b802125d0.md:16140 SSR.FER reports framing errors",
            "Manual/0900766b802125d0.md:16147 SSR.PER reports parity errors"
          ]
        }
      ],
      "serial_reconstruction": [
        {
          "address": 47981,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_rdr_read",
          "evidence_summary": "SCI1 RX ISR reads a byte from SCI1_RDR",
          "evidence_addresses": [
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB6D"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 RX ISR reads a byte from SCI1_RDR; confidence high"
        },
        {
          "address": 47981,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_rdrf_clear_before_rdr_read",
          "evidence_summary": "ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence",
          "evidence_addresses": [
            47977,
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB69",
            "H'BB6D"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: ROM clears SCI1 SSR.RDRF before reading SCI1_RDR; preserve this observed ordering even though the manual describes the canonical RDR-read then RDRF-clear sequence; confidence high"
        },
        {
          "address": 47981,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_eri_falls_through_to_rxi",
          "evidence_summary": "SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path",
          "evidence_addresses": [
            47959,
            47963,
            47967,
            47971,
            47977,
            47981
          ],
          "evidence_addresses_hex": [
            "H'BB57",
            "H'BB5B",
            "H'BB5F",
            "H'BB63",
            "H'BB69",
            "H'BB6D"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: SCI1 ERI latches FAA4.bit7, clears ORER/FER/PER, then falls through into the same RXI byte-capture path; confidence high"
        }
      ],
      "board_profile": {
        "accesses": [
          {
            "address": 47981,
            "instruction": "MOV:G.B @SCI1_RDR, R0",
            "channel": "SCI1",
            "register": "RDR",
            "register_address": 65245,
            "access": "read",
            "traced_to_max202": true,
            "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD"
          }
        ],
        "comment": "SCI1 RDR read receives from traced RS232/MAX202 path: MAX202 pin 12 -> H8 pin 67 P96/RXD"
      },
      "dataflow": {
        "block": 47975,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 47985,
      "address_region": "program_or_external",
      "bytes": "15F9C116",
      "text": "TST.B @H'F9C1",
      "mnemonic": "TST.B",
      "operands": "@H'F9C1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63937,
          "name": null,
          "symbol": "ram_F9C1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47975,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47989,
      "address_region": "program_or_external",
      "bytes": "2606",
      "text": "BNE loc_BB7D",
      "mnemonic": "BNE",
      "operands": "loc_BB7D",
      "kind": "branch",
      "targets": [
        47997
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47975,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47991,
      "address_region": "program_or_external",
      "bytes": "15F9C313",
      "text": "CLR.B @H'F9C3",
      "mnemonic": "CLR.B",
      "operands": "@H'F9C3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47991,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 47995,
      "address_region": "program_or_external",
      "bytes": "200D",
      "text": "BRA loc_BB8A",
      "mnemonic": "BRA",
      "operands": "loc_BB8A",
      "kind": "jump",
      "targets": [
        48010
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47991,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 47997,
      "address_region": "program_or_external",
      "bytes": "15F9C30405",
      "text": "CMP:G.B #H'05, @H'F9C3",
      "mnemonic": "CMP:G.B",
      "operands": "#H'05, @H'F9C3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47997,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48002,
      "address_region": "program_or_external",
      "bytes": "2306",
      "text": "BLS loc_BB8A",
      "mnemonic": "BLS",
      "operands": "loc_BB8A",
      "kind": "branch",
      "targets": [
        48010
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 47997,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48004,
      "address_region": "program_or_external",
      "bytes": "15FAA413",
      "text": "CLR.B @H'FAA4",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64164,
          "name": null,
          "symbol": "ram_FAA4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48004,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48008,
      "address_region": "program_or_external",
      "bytes": "2019",
      "text": "BRA loc_BBA3",
      "mnemonic": "BRA",
      "operands": "loc_BBA3",
      "kind": "jump",
      "targets": [
        48035
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48004,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48010,
      "address_region": "program_or_external",
      "bytes": "15F9C381",
      "text": "MOV:G.B @H'F9C3, R1",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9C3, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48010,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 48014,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48010,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 48016,
      "address_region": "program_or_external",
      "bytes": "F1F86890",
      "text": "MOV:G.B R0, @(-H'0798,R1)",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @(-H'0798,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48016,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_indexed_store",
          "evidence_summary": "received bytes are stored into candidate capture buffer H'F868-H'F86D",
          "evidence_addresses": [
            48016
          ],
          "evidence_addresses_hex": [
            "H'BB90"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: received bytes are stored into candidate capture buffer H'F868-H'F86D; confidence high"
        }
      ],
      "dataflow": {
        "block": 48010,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48020,
      "address_region": "program_or_external",
      "bytes": "A108",
      "text": "ADD:Q.B #1, R1",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48020,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_index_increment_store",
          "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3",
          "evidence_addresses": [
            48020,
            48022
          ],
          "evidence_addresses_hex": [
            "H'BB94",
            "H'BB96"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high"
        }
      ],
      "dataflow": {
        "block": 48010,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R1 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 48022,
      "address_region": "program_or_external",
      "bytes": "15F9C391",
      "text": "MOV:G.B R1, @H'F9C3",
      "mnemonic": "MOV:G.B",
      "operands": "R1, @H'F9C3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48022,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_index_increment_store",
          "evidence_summary": "RX byte count/index is incremented and stored at H'F9C3",
          "evidence_addresses": [
            48020,
            48022
          ],
          "evidence_addresses_hex": [
            "H'BB94",
            "H'BB96"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX byte count/index is incremented and stored at H'F9C3; confidence high"
        }
      ],
      "dataflow": {
        "block": 48010,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48026,
      "address_region": "program_or_external",
      "bytes": "4106",
      "text": "CMP:E #H'06, R1",
      "mnemonic": "CMP:E",
      "operands": "#H'06, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48026,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_isr_compare_frame_length",
          "evidence_summary": "RX ISR compares incremented count to candidate frame length 6",
          "evidence_addresses": [
            48026
          ],
          "evidence_addresses_hex": [
            "H'BB9A"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR compares incremented count to candidate frame length 6; confidence high"
        }
      ],
      "dataflow": {
        "block": 48010,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48028,
      "address_region": "program_or_external",
      "bytes": "2605",
      "text": "BNE loc_BBA3",
      "mnemonic": "BNE",
      "operands": "loc_BBA3",
      "kind": "branch",
      "targets": [
        48035
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48010,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48030,
      "address_region": "program_or_external",
      "bytes": "15F9C50614",
      "text": "MOV:G.B #H'14, @H'F9C5",
      "mnemonic": "MOV:G.B",
      "operands": "#H'14, @H'F9C5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63941,
          "name": null,
          "symbol": "ram_F9C5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48030,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_complete_timer",
          "evidence_summary": "RX ISR sets H'F9C5 after count reaches 6",
          "evidence_addresses": [
            48030
          ],
          "evidence_addresses_hex": [
            "H'BB9E"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX ISR sets H'F9C5 after count reaches 6; confidence high"
        }
      ],
      "dataflow": {
        "block": 48030,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48035,
      "address_region": "program_or_external",
      "bytes": "15F9C10605",
      "text": "MOV:G.B #H'05, @H'F9C1",
      "mnemonic": "MOV:G.B",
      "operands": "#H'05, @H'F9C1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63937,
          "name": null,
          "symbol": "ram_F9C1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48035,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48040,
      "address_region": "program_or_external",
      "bytes": "0203",
      "text": "LDM.W @SP+, {R0,R1}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R1}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "note": "6+4n, n=2",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48035,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0, R1"
        ]
      }
    },
    {
      "address": 48042,
      "address_region": "program_or_external",
      "bytes": "0A",
      "text": "RTE",
      "mnemonic": "RTE",
      "operands": "",
      "kind": "rte",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 13,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48035,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48043,
      "address_region": "program_or_external",
      "bytes": "15F9C30406",
      "text": "CMP:G.B #H'06, @H'F9C3",
      "mnemonic": "CMP:G.B",
      "operands": "#H'06, @H'F9C3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48043,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_processor_requires_six_bytes",
          "evidence_summary": "RX processing path requires H'F9C3 to equal 6",
          "evidence_addresses": [
            48043
          ],
          "evidence_addresses_hex": [
            "H'BBAB"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing path requires H'F9C3 to equal 6; confidence high"
        }
      ],
      "dataflow": {
        "block": 48043,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48048,
      "address_region": "program_or_external",
      "bytes": "3602BC",
      "text": "BNE loc_BE6F",
      "mnemonic": "BNE",
      "operands": "loc_BE6F",
      "kind": "branch",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48043,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48051,
      "address_region": "program_or_external",
      "bytes": "1DF86880",
      "text": "MOV:G.W @H'F868, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F868, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63592,
          "name": null,
          "symbol": "ram_F868",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48051,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_copy_capture_to_frame_buffer",
          "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865",
          "evidence_addresses": [
            48051,
            48059,
            48067,
            48055,
            48063,
            48071
          ],
          "evidence_addresses_hex": [
            "H'BBB3",
            "H'BBBB",
            "H'BBC3",
            "H'BBB7",
            "H'BBBF",
            "H'BBC7"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48051,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48055,
      "address_region": "program_or_external",
      "bytes": "1DF86090",
      "text": "MOV:G.W R0, @H'F860",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F860",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63584,
          "name": null,
          "symbol": "ram_F860",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48055,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_copy_capture_to_frame_buffer",
          "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865",
          "evidence_addresses": [
            48051,
            48059,
            48067,
            48055,
            48063,
            48071
          ],
          "evidence_addresses_hex": [
            "H'BBB3",
            "H'BBBB",
            "H'BBC3",
            "H'BBB7",
            "H'BBBF",
            "H'BBC7"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48051,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48059,
      "address_region": "program_or_external",
      "bytes": "1DF86A80",
      "text": "MOV:G.W @H'F86A, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F86A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63594,
          "name": null,
          "symbol": "ram_F86A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48059,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_copy_capture_to_frame_buffer",
          "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865",
          "evidence_addresses": [
            48051,
            48059,
            48067,
            48055,
            48063,
            48071
          ],
          "evidence_addresses_hex": [
            "H'BBB3",
            "H'BBBB",
            "H'BBC3",
            "H'BBB7",
            "H'BBBF",
            "H'BBC7"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48051,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48063,
      "address_region": "program_or_external",
      "bytes": "1DF86290",
      "text": "MOV:G.W R0, @H'F862",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F862",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63586,
          "name": null,
          "symbol": "ram_F862",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48063,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_copy_capture_to_frame_buffer",
          "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865",
          "evidence_addresses": [
            48051,
            48059,
            48067,
            48055,
            48063,
            48071
          ],
          "evidence_addresses_hex": [
            "H'BBB3",
            "H'BBBB",
            "H'BBC3",
            "H'BBB7",
            "H'BBBF",
            "H'BBC7"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48051,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48067,
      "address_region": "program_or_external",
      "bytes": "1DF86C80",
      "text": "MOV:G.W @H'F86C, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F86C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63596,
          "name": null,
          "symbol": "ram_F86C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48067,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_copy_capture_to_frame_buffer",
          "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865",
          "evidence_addresses": [
            48051,
            48059,
            48067,
            48055,
            48063,
            48071
          ],
          "evidence_addresses_hex": [
            "H'BBB3",
            "H'BBBB",
            "H'BBC3",
            "H'BBB7",
            "H'BBBF",
            "H'BBC7"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48051,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48071,
      "address_region": "program_or_external",
      "bytes": "1DF86490",
      "text": "MOV:G.W R0, @H'F864",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F864",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63588,
          "name": null,
          "symbol": "ram_F864",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48071,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_copy_capture_to_frame_buffer",
          "evidence_summary": "RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865",
          "evidence_addresses": [
            48051,
            48059,
            48067,
            48055,
            48063,
            48071
          ],
          "evidence_addresses_hex": [
            "H'BBB3",
            "H'BBBB",
            "H'BBC3",
            "H'BBB7",
            "H'BBBF",
            "H'BBC7"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX processing copies candidate capture buffer H'F868-H'F86D to validation buffer H'F860-H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48051,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48075,
      "address_region": "program_or_external",
      "bytes": "15F9C313",
      "text": "CLR.B @H'F9C3",
      "mnemonic": "CLR.B",
      "operands": "@H'F9C3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48051,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48079,
      "address_region": "program_or_external",
      "bytes": "15FAA4F7",
      "text": "BTST.B #7, @H'FAA4",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FAA4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64164,
          "name": null,
          "symbol": "ram_FAA4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48051,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48083,
      "address_region": "program_or_external",
      "bytes": "360253",
      "text": "BNE loc_BE29",
      "mnemonic": "BNE",
      "operands": "loc_BE29",
      "kind": "branch",
      "targets": [
        48681
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48051,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48086,
      "address_region": "program_or_external",
      "bytes": "505A",
      "text": "MOV:E.B #H'5A, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'5A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48086,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_checksum_seed",
          "evidence_summary": "candidate RX checksum validation starts from seed H'005A",
          "evidence_addresses": [
            48086
          ],
          "evidence_addresses_hex": [
            "H'BBD6"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: candidate RX checksum validation starts from seed H'005A; confidence high"
        },
        {
          "address": 48086,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_xor_checksum_validation",
          "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865",
          "evidence_addresses": [
            48086,
            48088,
            48092,
            48096,
            48100,
            48104,
            48108
          ],
          "evidence_addresses_hex": [
            "H'BBD6",
            "H'BBD8",
            "H'BBDC",
            "H'BBE0",
            "H'BBE4",
            "H'BBE8",
            "H'BBEC"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48086,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 90,
              "hex": "0x5A",
              "width": 8,
              "source": "MOV:E.B #H'5A, R0"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 = 0x5A"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 90,
              "hex": "0x5A",
              "width": 8,
              "source": "MOV:E.B #H'5A, R0"
            }
          }
        }
      }
    },
    {
      "address": 48088,
      "address_region": "program_or_external",
      "bytes": "15F86060",
      "text": "XOR.B @H'F860, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F860, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63584,
          "name": null,
          "symbol": "ram_F860",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48088,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_xor_checksum_validation",
          "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865",
          "evidence_addresses": [
            48086,
            48088,
            48092,
            48096,
            48100,
            48104,
            48108
          ],
          "evidence_addresses_hex": [
            "H'BBD6",
            "H'BBD8",
            "H'BBDC",
            "H'BBE0",
            "H'BBE4",
            "H'BBE8",
            "H'BBEC"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48086,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": true,
              "value": 90,
              "hex": "0x5A",
              "width": 8,
              "source": "MOV:E.B #H'5A, R0"
            },
            "after": {
              "known": false,
              "reason": "unsupported:XOR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48092,
      "address_region": "program_or_external",
      "bytes": "15F86160",
      "text": "XOR.B @H'F861, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F861, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63585,
          "name": null,
          "symbol": "ram_F861",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48092,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_xor_checksum_validation",
          "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865",
          "evidence_addresses": [
            48086,
            48088,
            48092,
            48096,
            48100,
            48104,
            48108
          ],
          "evidence_addresses_hex": [
            "H'BBD6",
            "H'BBD8",
            "H'BBDC",
            "H'BBE0",
            "H'BBE4",
            "H'BBE8",
            "H'BBEC"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48086,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48096,
      "address_region": "program_or_external",
      "bytes": "15F86260",
      "text": "XOR.B @H'F862, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F862, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63586,
          "name": null,
          "symbol": "ram_F862",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48096,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_xor_checksum_validation",
          "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865",
          "evidence_addresses": [
            48086,
            48088,
            48092,
            48096,
            48100,
            48104,
            48108
          ],
          "evidence_addresses_hex": [
            "H'BBD6",
            "H'BBD8",
            "H'BBDC",
            "H'BBE0",
            "H'BBE4",
            "H'BBE8",
            "H'BBEC"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48086,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48100,
      "address_region": "program_or_external",
      "bytes": "15F86360",
      "text": "XOR.B @H'F863, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F863, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63587,
          "name": null,
          "symbol": "ram_F863",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48100,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_xor_checksum_validation",
          "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865",
          "evidence_addresses": [
            48086,
            48088,
            48092,
            48096,
            48100,
            48104,
            48108
          ],
          "evidence_addresses_hex": [
            "H'BBD6",
            "H'BBD8",
            "H'BBDC",
            "H'BBE0",
            "H'BBE4",
            "H'BBE8",
            "H'BBEC"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48086,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48104,
      "address_region": "program_or_external",
      "bytes": "15F86460",
      "text": "XOR.B @H'F864, R0",
      "mnemonic": "XOR.B",
      "operands": "@H'F864, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63588,
          "name": null,
          "symbol": "ram_F864",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48104,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_xor_checksum_validation",
          "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865",
          "evidence_addresses": [
            48086,
            48088,
            48092,
            48096,
            48100,
            48104,
            48108
          ],
          "evidence_addresses_hex": [
            "H'BBD6",
            "H'BBD8",
            "H'BBDC",
            "H'BBE0",
            "H'BBE4",
            "H'BBE8",
            "H'BBEC"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48086,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48108,
      "address_region": "program_or_external",
      "bytes": "15F86570",
      "text": "CMP:G.B @H'F865, R0",
      "mnemonic": "CMP:G.B",
      "operands": "@H'F865, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63589,
          "name": null,
          "symbol": "ram_F865",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48108,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "candidate_kind": "candidate_sci1_rx_frame",
          "evidence": "rx_xor_checksum_validation",
          "evidence_summary": "RX path XORs H'F860-H'F864 and compares the result with H'F865",
          "evidence_addresses": [
            48086,
            48088,
            48092,
            48096,
            48100,
            48104,
            48108
          ],
          "evidence_addresses_hex": [
            "H'BBD6",
            "H'BBD8",
            "H'BBDC",
            "H'BBE0",
            "H'BBE4",
            "H'BBE8",
            "H'BBEC"
          ],
          "confidence": "high",
          "confidence_score": 0.9,
          "comment": "candidate/evidence-supported SCI1 6-byte RX frame; capture H'F868-H'F86D, validate H'F860-H'F865, checksum H'F865 seeded by H'005A; evidence: RX path XORs H'F860-H'F864 and compares the result with H'F865; confidence high"
        }
      ],
      "dataflow": {
        "block": 48086,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48112,
      "address_region": "program_or_external",
      "bytes": "360236",
      "text": "BNE loc_BE29",
      "mnemonic": "BNE",
      "operands": "loc_BE29",
      "kind": "branch",
      "targets": [
        48681
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48086,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48115,
      "address_region": "program_or_external",
      "bytes": "15FAA613",
      "text": "CLR.B @H'FAA6",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64166,
          "name": null,
          "symbol": "ram_FAA6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48119,
      "address_region": "program_or_external",
      "bytes": "15F86185",
      "text": "MOV:G.B @H'F861, R5",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F861, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63585,
          "name": null,
          "symbol": "ram_F861",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R5 unknown after memory load"
        ]
      }
    },
    {
      "address": 48123,
      "address_region": "program_or_external",
      "bytes": "A510",
      "text": "SWAP.B R5",
      "mnemonic": "SWAP.B",
      "operands": "R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R5"
        ]
      }
    },
    {
      "address": 48125,
      "address_region": "program_or_external",
      "bytes": "15F86285",
      "text": "MOV:G.B @H'F862, R5",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F862, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63586,
          "name": null,
          "symbol": "ram_F862",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R5 unknown after memory load"
        ]
      }
    },
    {
      "address": 48129,
      "address_region": "program_or_external",
      "bytes": "1EA627",
      "text": "BSR loc_622B",
      "mnemonic": "BSR",
      "operands": "loc_622B",
      "kind": "call",
      "targets": [
        25131
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48132,
      "address_region": "program_or_external",
      "bytes": "AD84",
      "text": "MOV:G.W R5, R4",
      "mnemonic": "MOV:G.W",
      "operands": "R5, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after MOV source"
        ]
      }
    },
    {
      "address": 48134,
      "address_region": "program_or_external",
      "bytes": "AC1A",
      "text": "SHLL.W R4",
      "mnemonic": "SHLL.W",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 48136,
      "address_region": "program_or_external",
      "bytes": "15F86080",
      "text": "MOV:G.B @H'F860, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F860, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63584,
          "name": null,
          "symbol": "ram_F860",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48140,
      "address_region": "program_or_external",
      "bytes": "040750",
      "text": "AND.B #H'07, R0",
      "mnemonic": "AND.B",
      "operands": "#H'07, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48143,
      "address_region": "program_or_external",
      "bytes": "15FAA216",
      "text": "TST.B @H'FAA2",
      "mnemonic": "TST.B",
      "operands": "@H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48147,
      "address_region": "program_or_external",
      "bytes": "2625",
      "text": "BNE loc_BC3A",
      "mnemonic": "BNE",
      "operands": "loc_BC3A",
      "kind": "branch",
      "targets": [
        48186
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48115,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48149,
      "address_region": "program_or_external",
      "bytes": "15FAA2C7",
      "text": "BSET.B #7, @H'FAA2",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48149,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48153,
      "address_region": "program_or_external",
      "bytes": "15F861F7",
      "text": "BTST.B #7, @H'F861",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F861",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63585,
          "name": null,
          "symbol": "ram_F861",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48149,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48157,
      "address_region": "program_or_external",
      "bytes": "3600EB",
      "text": "BNE loc_BD0B",
      "mnemonic": "BNE",
      "operands": "loc_BD0B",
      "kind": "branch",
      "targets": [
        48395
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48149,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48160,
      "address_region": "program_or_external",
      "bytes": "4000",
      "text": "CMP:E #H'00, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'00, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48160,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48162,
      "address_region": "program_or_external",
      "bytes": "2745",
      "text": "BEQ loc_BC69",
      "mnemonic": "BEQ",
      "operands": "loc_BC69",
      "kind": "branch",
      "targets": [
        48233
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48160,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48164,
      "address_region": "program_or_external",
      "bytes": "4001",
      "text": "CMP:E #H'01, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'01, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48164,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48166,
      "address_region": "program_or_external",
      "bytes": "3700AE",
      "text": "BEQ loc_BCD7",
      "mnemonic": "BEQ",
      "operands": "loc_BCD7",
      "kind": "branch",
      "targets": [
        48343
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48164,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48169,
      "address_region": "program_or_external",
      "bytes": "4002",
      "text": "CMP:E #H'02, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'02, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48169,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48171,
      "address_region": "program_or_external",
      "bytes": "3700D6",
      "text": "BEQ loc_BD04",
      "mnemonic": "BEQ",
      "operands": "loc_BD04",
      "kind": "branch",
      "targets": [
        48388
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48169,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48174,
      "address_region": "program_or_external",
      "bytes": "4007",
      "text": "CMP:E #H'07, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'07, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48174,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48176,
      "address_region": "program_or_external",
      "bytes": "3701D2",
      "text": "BEQ loc_BE05",
      "mnemonic": "BEQ",
      "operands": "loc_BE05",
      "kind": "branch",
      "targets": [
        48645
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48174,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48179,
      "address_region": "program_or_external",
      "bytes": "15FAA213",
      "text": "CLR.B @H'FAA2",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48179,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48183,
      "address_region": "program_or_external",
      "bytes": "300235",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48179,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48186,
      "address_region": "program_or_external",
      "bytes": "A0F2",
      "text": "BTST.B #2, R0",
      "mnemonic": "BTST.B",
      "operands": "#2, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48186,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48188,
      "address_region": "program_or_external",
      "bytes": "271E",
      "text": "BEQ loc_BC5C",
      "mnemonic": "BEQ",
      "operands": "loc_BC5C",
      "kind": "branch",
      "targets": [
        48220
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48186,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48190,
      "address_region": "program_or_external",
      "bytes": "15F861F7",
      "text": "BTST.B #7, @H'F861",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F861",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63585,
          "name": null,
          "symbol": "ram_F861",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48190,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48194,
      "address_region": "program_or_external",
      "bytes": "3601E2",
      "text": "BNE loc_BE27",
      "mnemonic": "BNE",
      "operands": "loc_BE27",
      "kind": "branch",
      "targets": [
        48679
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48190,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48197,
      "address_region": "program_or_external",
      "bytes": "4004",
      "text": "CMP:E #H'04, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'04, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48197,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48199,
      "address_region": "program_or_external",
      "bytes": "3700C4",
      "text": "BEQ loc_BD0E",
      "mnemonic": "BEQ",
      "operands": "loc_BD0E",
      "kind": "branch",
      "targets": [
        48398
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48197,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48202,
      "address_region": "program_or_external",
      "bytes": "4005",
      "text": "CMP:E #H'05, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'05, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48202,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48204,
      "address_region": "program_or_external",
      "bytes": "370131",
      "text": "BEQ loc_BD80",
      "mnemonic": "BEQ",
      "operands": "loc_BD80",
      "kind": "branch",
      "targets": [
        48512
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48202,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48207,
      "address_region": "program_or_external",
      "bytes": "4006",
      "text": "CMP:E #H'06, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'06, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48207,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48209,
      "address_region": "program_or_external",
      "bytes": "370187",
      "text": "BEQ loc_BDDB",
      "mnemonic": "BEQ",
      "operands": "loc_BDDB",
      "kind": "branch",
      "targets": [
        48603
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48207,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48212,
      "address_region": "program_or_external",
      "bytes": "4007",
      "text": "CMP:E #H'07, R0",
      "mnemonic": "CMP:E",
      "operands": "#H'07, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48212,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48214,
      "address_region": "program_or_external",
      "bytes": "3701AC",
      "text": "BEQ loc_BE05",
      "mnemonic": "BEQ",
      "operands": "loc_BE05",
      "kind": "branch",
      "targets": [
        48645
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48212,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48217,
      "address_region": "program_or_external",
      "bytes": "300213",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48217,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48220,
      "address_region": "program_or_external",
      "bytes": "15FAA2D3",
      "text": "BCLR.B #3, @H'FAA2",
      "mnemonic": "BCLR.B",
      "operands": "#3, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48220,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48224,
      "address_region": "program_or_external",
      "bytes": "37020C",
      "text": "BEQ loc_BE6F",
      "mnemonic": "BEQ",
      "operands": "loc_BE6F",
      "kind": "branch",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48220,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48227,
      "address_region": "program_or_external",
      "bytes": "15FAA313",
      "text": "CLR.B @H'FAA3",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64163,
          "name": null,
          "symbol": "ram_FAA3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48227,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48231,
      "address_region": "program_or_external",
      "bytes": "20AC",
      "text": "BRA loc_BC15",
      "mnemonic": "BRA",
      "operands": "loc_BC15",
      "kind": "jump",
      "targets": [
        48149
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48227,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48233,
      "address_region": "program_or_external",
      "bytes": "AD16",
      "text": "TST.W R5",
      "mnemonic": "TST.W",
      "operands": "R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48233,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48235,
      "address_region": "program_or_external",
      "bytes": "261E",
      "text": "BNE loc_BC8B",
      "mnemonic": "BNE",
      "operands": "loc_BC8B",
      "kind": "branch",
      "targets": [
        48267
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48233,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48237,
      "address_region": "program_or_external",
      "bytes": "15F86380",
      "text": "MOV:G.B @H'F863, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F863, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63587,
          "name": null,
          "symbol": "ram_F863",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48237,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48241,
      "address_region": "program_or_external",
      "bytes": "A010",
      "text": "SWAP.B R0",
      "mnemonic": "SWAP.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48237,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48243,
      "address_region": "program_or_external",
      "bytes": "5080",
      "text": "MOV:E.B #H'80, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'80, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48237,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        ],
        "notes": [
          "R0 = 0x80"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        }
      }
    },
    {
      "address": 48245,
      "address_region": "program_or_external",
      "bytes": "FCE00090",
      "text": "MOV:G.W R0, @(-H'2000,R4)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'2000,R4)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48237,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        }
      }
    },
    {
      "address": 48249,
      "address_region": "program_or_external",
      "bytes": "FCE80090",
      "text": "MOV:G.W R0, @(-H'1800,R4)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'1800,R4)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48237,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        }
      }
    },
    {
      "address": 48253,
      "address_region": "program_or_external",
      "bytes": "15F8640680",
      "text": "MOV:G.B #H'80, @H'F864",
      "mnemonic": "MOV:G.B",
      "operands": "#H'80, @H'F864",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63588,
          "name": null,
          "symbol": "ram_F864",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48237,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        }
      }
    },
    {
      "address": 48258,
      "address_region": "program_or_external",
      "bytes": "F5EC00C7",
      "text": "BSET.B #7, @(-H'1400,R5)",
      "mnemonic": "BSET.B",
      "operands": "#7, @(-H'1400,R5)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48237,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        }
      }
    },
    {
      "address": 48262,
      "address_region": "program_or_external",
      "bytes": "1E01E7",
      "text": "BSR loc_BE70",
      "mnemonic": "BSR",
      "operands": "loc_BE70",
      "kind": "call",
      "targets": [
        48752
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48237,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48265,
      "address_region": "program_or_external",
      "bytes": "2025",
      "text": "BRA loc_BCB0",
      "mnemonic": "BRA",
      "operands": "loc_BCB0",
      "kind": "jump",
      "targets": [
        48304
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48237,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48267,
      "address_region": "program_or_external",
      "bytes": "15F86380",
      "text": "MOV:G.B @H'F863, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F863, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63587,
          "name": null,
          "symbol": "ram_F863",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48267,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48271,
      "address_region": "program_or_external",
      "bytes": "A010",
      "text": "SWAP.B R0",
      "mnemonic": "SWAP.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48267,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48273,
      "address_region": "program_or_external",
      "bytes": "15F86480",
      "text": "MOV:G.B @H'F864, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F864, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63588,
          "name": null,
          "symbol": "ram_F864",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48267,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48277,
      "address_region": "program_or_external",
      "bytes": "FCE00090",
      "text": "MOV:G.W R0, @(-H'2000,R4)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'2000,R4)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48267,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48281,
      "address_region": "program_or_external",
      "bytes": "FCE80090",
      "text": "MOV:G.W R0, @(-H'1800,R4)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'1800,R4)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48267,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48285,
      "address_region": "program_or_external",
      "bytes": "F5EC00C7",
      "text": "BSET.B #7, @(-H'1400,R5)",
      "mnemonic": "BSET.B",
      "operands": "#7, @(-H'1400,R5)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48267,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48289,
      "address_region": "program_or_external",
      "bytes": "FCC56481",
      "text": "MOV:G.W @(-H'3A9C,R4), R1",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'3A9C,R4), R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48267,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 48293,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48267,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 48295,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_BCAD",
      "mnemonic": "BEQ",
      "operands": "loc_BCAD",
      "kind": "branch",
      "targets": [
        48301
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48267,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48297,
      "address_region": "program_or_external",
      "bytes": "F9F40090",
      "text": "MOV:G.W R0, @(-H'0C00,R1)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'0C00,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48297,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48301,
      "address_region": "program_or_external",
      "bytes": "1E01C0",
      "text": "BSR loc_BE70",
      "mnemonic": "BSR",
      "operands": "loc_BE70",
      "kind": "call",
      "targets": [
        48752
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48301,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48304,
      "address_region": "program_or_external",
      "bytes": "15F8500604",
      "text": "MOV:G.B #H'04, @H'F850",
      "mnemonic": "MOV:G.B",
      "operands": "#H'04, @H'F850",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63568,
          "name": null,
          "symbol": "ram_F850",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48309,
      "address_region": "program_or_external",
      "bytes": "15F86180",
      "text": "MOV:G.B @H'F861, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F861, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63585,
          "name": null,
          "symbol": "ram_F861",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48313,
      "address_region": "program_or_external",
      "bytes": "15F85190",
      "text": "MOV:G.B R0, @H'F851",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F851",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63569,
          "name": null,
          "symbol": "ram_F851",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48317,
      "address_region": "program_or_external",
      "bytes": "1DF86280",
      "text": "MOV:G.W @H'F862, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F862, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63586,
          "name": null,
          "symbol": "ram_F862",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48321,
      "address_region": "program_or_external",
      "bytes": "1DF85290",
      "text": "MOV:G.W R0, @H'F852",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F852",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63570,
          "name": null,
          "symbol": "ram_F852",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48325,
      "address_region": "program_or_external",
      "bytes": "15F86480",
      "text": "MOV:G.B @H'F864, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F864, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63588,
          "name": null,
          "symbol": "ram_F864",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48329,
      "address_region": "program_or_external",
      "bytes": "15F85490",
      "text": "MOV:G.B R0, @H'F854",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F854",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63572,
          "name": null,
          "symbol": "ram_F854",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48333,
      "address_region": "program_or_external",
      "bytes": "1EFD56",
      "text": "BSR loc_BA26",
      "mnemonic": "BSR",
      "operands": "loc_BA26",
      "kind": "call",
      "targets": [
        47654
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48336,
      "address_region": "program_or_external",
      "bytes": "15FAA2D7",
      "text": "BCLR.B #7, @H'FAA2",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48340,
      "address_region": "program_or_external",
      "bytes": "300198",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48304,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48343,
      "address_region": "program_or_external",
      "bytes": "15F8500604",
      "text": "MOV:G.B #H'04, @H'F850",
      "mnemonic": "MOV:G.B",
      "operands": "#H'04, @H'F850",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63568,
          "name": null,
          "symbol": "ram_F850",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48348,
      "address_region": "program_or_external",
      "bytes": "15F86180",
      "text": "MOV:G.B @H'F861, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F861, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63585,
          "name": null,
          "symbol": "ram_F861",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48352,
      "address_region": "program_or_external",
      "bytes": "15F85190",
      "text": "MOV:G.B R0, @H'F851",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F851",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63569,
          "name": null,
          "symbol": "ram_F851",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48356,
      "address_region": "program_or_external",
      "bytes": "15F86280",
      "text": "MOV:G.B @H'F862, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F862, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63586,
          "name": null,
          "symbol": "ram_F862",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48360,
      "address_region": "program_or_external",
      "bytes": "15F85190",
      "text": "MOV:G.B R0, @H'F851",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F851",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63569,
          "name": null,
          "symbol": "ram_F851",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48364,
      "address_region": "program_or_external",
      "bytes": "FCE00080",
      "text": "MOV:G.W @(-H'2000,R4), R0",
      "mnemonic": "MOV:G.W",
      "operands": "@(-H'2000,R4), R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48368,
      "address_region": "program_or_external",
      "bytes": "15F85490",
      "text": "MOV:G.B R0, @H'F854",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F854",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63572,
          "name": null,
          "symbol": "ram_F854",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48372,
      "address_region": "program_or_external",
      "bytes": "A010",
      "text": "SWAP.B R0",
      "mnemonic": "SWAP.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48374,
      "address_region": "program_or_external",
      "bytes": "15F85390",
      "text": "MOV:G.B R0, @H'F853",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F853",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63571,
          "name": null,
          "symbol": "ram_F853",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48378,
      "address_region": "program_or_external",
      "bytes": "1EFD29",
      "text": "BSR loc_BA26",
      "mnemonic": "BSR",
      "operands": "loc_BA26",
      "kind": "call",
      "targets": [
        47654
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48381,
      "address_region": "program_or_external",
      "bytes": "15FAA2D7",
      "text": "BCLR.B #7, @H'FAA2",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48385,
      "address_region": "program_or_external",
      "bytes": "30016B",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48343,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48388,
      "address_region": "program_or_external",
      "bytes": "15FAA2D7",
      "text": "BCLR.B #7, @H'FAA2",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48388,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48392,
      "address_region": "program_or_external",
      "bytes": "300164",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48388,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48395,
      "address_region": "program_or_external",
      "bytes": "300161",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48395,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48398,
      "address_region": "program_or_external",
      "bytes": "AD16",
      "text": "TST.W R5",
      "mnemonic": "TST.W",
      "operands": "R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48398,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48400,
      "address_region": "program_or_external",
      "bytes": "2619",
      "text": "BNE loc_BD2B",
      "mnemonic": "BNE",
      "operands": "loc_BD2B",
      "kind": "branch",
      "targets": [
        48427
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48398,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48402,
      "address_region": "program_or_external",
      "bytes": "15F86380",
      "text": "MOV:G.B @H'F863, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F863, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63587,
          "name": null,
          "symbol": "ram_F863",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48402,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48406,
      "address_region": "program_or_external",
      "bytes": "A010",
      "text": "SWAP.B R0",
      "mnemonic": "SWAP.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48402,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48408,
      "address_region": "program_or_external",
      "bytes": "5080",
      "text": "MOV:E.B #H'80, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'80, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48402,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        ],
        "notes": [
          "R0 = 0x80"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        }
      }
    },
    {
      "address": 48410,
      "address_region": "program_or_external",
      "bytes": "FCE00090",
      "text": "MOV:G.W R0, @(-H'2000,R4)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'2000,R4)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48402,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        }
      }
    },
    {
      "address": 48414,
      "address_region": "program_or_external",
      "bytes": "FCE80090",
      "text": "MOV:G.W R0, @(-H'1800,R4)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'1800,R4)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48402,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        }
      }
    },
    {
      "address": 48418,
      "address_region": "program_or_external",
      "bytes": "F5EC00C7",
      "text": "BSET.B #7, @(-H'1400,R5)",
      "mnemonic": "BSET.B",
      "operands": "#7, @(-H'1400,R5)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48402,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            }
          }
        }
      }
    },
    {
      "address": 48422,
      "address_region": "program_or_external",
      "bytes": "1E0147",
      "text": "BSR loc_BE70",
      "mnemonic": "BSR",
      "operands": "loc_BE70",
      "kind": "call",
      "targets": [
        48752
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48402,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": true,
              "value": 128,
              "hex": "0x80",
              "width": 8,
              "source": "MOV:E.B #H'80, R0"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48425,
      "address_region": "program_or_external",
      "bytes": "203C",
      "text": "BRA loc_BD67",
      "mnemonic": "BRA",
      "operands": "loc_BD67",
      "kind": "jump",
      "targets": [
        48487
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48402,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48427,
      "address_region": "program_or_external",
      "bytes": "15F86380",
      "text": "MOV:G.B @H'F863, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F863, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63587,
          "name": null,
          "symbol": "ram_F863",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48427,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48431,
      "address_region": "program_or_external",
      "bytes": "A010",
      "text": "SWAP.B R0",
      "mnemonic": "SWAP.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48427,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48433,
      "address_region": "program_or_external",
      "bytes": "15F86480",
      "text": "MOV:G.B @H'F864, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F864, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63588,
          "name": null,
          "symbol": "ram_F864",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48427,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48437,
      "address_region": "program_or_external",
      "bytes": "FCE00090",
      "text": "MOV:G.W R0, @(-H'2000,R4)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'2000,R4)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48427,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48441,
      "address_region": "program_or_external",
      "bytes": "F5EC00C7",
      "text": "BSET.B #7, @(-H'1400,R5)",
      "mnemonic": "BSET.B",
      "operands": "#7, @(-H'1400,R5)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48427,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48445,
      "address_region": "program_or_external",
      "bytes": "F4C56581",
      "text": "MOV:G.B @(-H'3A9B,R4), R1",
      "mnemonic": "MOV:G.B",
      "operands": "@(-H'3A9B,R4), R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48427,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 48449,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48427,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 48451,
      "address_region": "program_or_external",
      "bytes": "271F",
      "text": "BEQ loc_BD64",
      "mnemonic": "BEQ",
      "operands": "loc_BD64",
      "kind": "branch",
      "targets": [
        48484
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48427,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48453,
      "address_region": "program_or_external",
      "bytes": "F9F40090",
      "text": "MOV:G.W R0, @(-H'0C00,R1)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'0C00,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48453,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48457,
      "address_region": "program_or_external",
      "bytes": "15F76EF7",
      "text": "BTST.B #7, @H'F76E",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F76E",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63342,
          "name": null,
          "symbol": "ram_F76E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48453,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48461,
      "address_region": "program_or_external",
      "bytes": "2715",
      "text": "BEQ loc_BD64",
      "mnemonic": "BEQ",
      "operands": "loc_BD64",
      "kind": "branch",
      "targets": [
        48484
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48453,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48463,
      "address_region": "program_or_external",
      "bytes": "1231",
      "text": "STM.W {R0,R4,R5}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R4,R5}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 15,
        "note": "6+3n, n=3",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48463,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48465,
      "address_region": "program_or_external",
      "bytes": "15F76E84",
      "text": "MOV:G.B @H'F76E, R4",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F76E, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63342,
          "name": null,
          "symbol": "ram_F76E",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48463,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R4 unknown after memory load"
        ]
      }
    },
    {
      "address": 48469,
      "address_region": "program_or_external",
      "bytes": "A410",
      "text": "SWAP.B R4",
      "mnemonic": "SWAP.B",
      "operands": "R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48463,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 48471,
      "address_region": "program_or_external",
      "bytes": "A184",
      "text": "MOV:G.B R1, R4",
      "mnemonic": "MOV:G.B",
      "operands": "R1, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48463,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R4 unknown after MOV source"
        ]
      }
    },
    {
      "address": 48473,
      "address_region": "program_or_external",
      "bytes": "0C0FFE54",
      "text": "AND.W #H'0FFE, R4",
      "mnemonic": "AND.W",
      "operands": "#H'0FFE, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48463,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 48477,
      "address_region": "program_or_external",
      "bytes": "A885",
      "text": "MOV:G.W R0, R5",
      "mnemonic": "MOV:G.W",
      "operands": "R0, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48463,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          }
        ],
        "notes": [
          "R5 unknown after MOV source"
        ]
      }
    },
    {
      "address": 48479,
      "address_region": "program_or_external",
      "bytes": "1E027E",
      "text": "BSR loc_BFE0",
      "mnemonic": "BSR",
      "operands": "loc_BFE0",
      "kind": "call",
      "targets": [
        49120
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48463,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "unsupported:AND.W"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48482,
      "address_region": "program_or_external",
      "bytes": "0231",
      "text": "LDM.W @SP+, {R0,R4,R5}",
      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R4,R5}",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 18,
        "note": "6+4n, n=3",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48463,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0, R4, R5"
        ]
      }
    },
    {
      "address": 48484,
      "address_region": "program_or_external",
      "bytes": "1E0109",
      "text": "BSR loc_BE70",
      "mnemonic": "BSR",
      "operands": "loc_BE70",
      "kind": "call",
      "targets": [
        48752
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48484,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48487,
      "address_region": "program_or_external",
      "bytes": "15FAA2F3",
      "text": "BTST.B #3, @H'FAA2",
      "mnemonic": "BTST.B",
      "operands": "#3, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48487,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48491,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_BD75",
      "mnemonic": "BEQ",
      "operands": "loc_BD75",
      "kind": "branch",
      "targets": [
        48501
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48487,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48493,
      "address_region": "program_or_external",
      "bytes": "15F9B508",
      "text": "ADD:Q.B #1, @H'F9B5",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F9B5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48493,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48497,
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      "text": "BRA loc_BDC2",
      "mnemonic": "BRA",
      "operands": "loc_BDC2",
      "kind": "jump",
      "targets": [
        48578
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48565,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48575,
      "address_region": "program_or_external",
      "bytes": "1E00AE",
      "text": "BSR loc_BE70",
      "mnemonic": "BSR",
      "operands": "loc_BE70",
      "kind": "call",
      "targets": [
        48752
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48575,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48578,
      "address_region": "program_or_external",
      "bytes": "15FAA2F3",
      "text": "BTST.B #3, @H'FAA2",
      "mnemonic": "BTST.B",
      "operands": "#3, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48578,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48582,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_BDD0",
      "mnemonic": "BEQ",
      "operands": "loc_BDD0",
      "kind": "branch",
      "targets": [
        48592
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48578,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48584,
      "address_region": "program_or_external",
      "bytes": "15F9B508",
      "text": "ADD:Q.B #1, @H'F9B5",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F9B5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48584,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48588,
      "address_region": "program_or_external",
      "bytes": "15F9B5D7",
      "text": "BCLR.B #7, @H'F9B5",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F9B5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48584,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48592,
      "address_region": "program_or_external",
      "bytes": "15FAA313",
      "text": "CLR.B @H'FAA3",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64163,
          "name": null,
          "symbol": "ram_FAA3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48592,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48596,
      "address_region": "program_or_external",
      "bytes": "15FAA213",
      "text": "CLR.B @H'FAA2",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48592,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48600,
      "address_region": "program_or_external",
      "bytes": "300094",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48592,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48603,
      "address_region": "program_or_external",
      "bytes": "15F86380",
      "text": "MOV:G.B @H'F863, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F863, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63587,
          "name": null,
          "symbol": "ram_F863",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48603,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48607,
      "address_region": "program_or_external",
      "bytes": "A010",
      "text": "SWAP.B R0",
      "mnemonic": "SWAP.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48603,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48609,
      "address_region": "program_or_external",
      "bytes": "15F86480",
      "text": "MOV:G.B @H'F864, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F864, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63588,
          "name": null,
          "symbol": "ram_F864",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48603,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48613,
      "address_region": "program_or_external",
      "bytes": "FCE40090",
      "text": "MOV:G.W R0, @(-H'1C00,R4)",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @(-H'1C00,R4)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48603,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48617,
      "address_region": "program_or_external",
      "bytes": "F5EC00C6",
      "text": "BSET.B #6, @(-H'1400,R5)",
      "mnemonic": "BSET.B",
      "operands": "#6, @(-H'1400,R5)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48603,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48621,
      "address_region": "program_or_external",
      "bytes": "15FAA2F3",
      "text": "BTST.B #3, @H'FAA2",
      "mnemonic": "BTST.B",
      "operands": "#3, @H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48603,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48625,
      "address_region": "program_or_external",
      "bytes": "2708",
      "text": "BEQ loc_BDFB",
      "mnemonic": "BEQ",
      "operands": "loc_BDFB",
      "kind": "branch",
      "targets": [
        48635
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48603,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48627,
      "address_region": "program_or_external",
      "bytes": "15F9B508",
      "text": "ADD:Q.B #1, @H'F9B5",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F9B5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48627,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48631,
      "address_region": "program_or_external",
      "bytes": "15F9B5D7",
      "text": "BCLR.B #7, @H'F9B5",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F9B5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63925,
          "name": null,
          "symbol": "ram_F9B5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48627,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48635,
      "address_region": "program_or_external",
      "bytes": "15FAA313",
      "text": "CLR.B @H'FAA3",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64163,
          "name": null,
          "symbol": "ram_FAA3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48635,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48639,
      "address_region": "program_or_external",
      "bytes": "15FAA213",
      "text": "CLR.B @H'FAA2",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48635,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48643,
      "address_region": "program_or_external",
      "bytes": "206A",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48635,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48645,
      "address_region": "program_or_external",
      "bytes": "1DF85880",
      "text": "MOV:G.W @H'F858, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F858, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63576,
          "name": null,
          "symbol": "ram_F858",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48645,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        }
      ],
      "dataflow": {
        "block": 48645,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48649,
      "address_region": "program_or_external",
      "bytes": "1DF85090",
      "text": "MOV:G.W R0, @H'F850",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F850",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63568,
          "name": null,
          "symbol": "ram_F850",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48645,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48653,
      "address_region": "program_or_external",
      "bytes": "1DF85A80",
      "text": "MOV:G.W @H'F85A, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F85A, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63578,
          "name": null,
          "symbol": "ram_F85A",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48653,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        }
      ],
      "dataflow": {
        "block": 48645,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48657,
      "address_region": "program_or_external",
      "bytes": "1DF85290",
      "text": "MOV:G.W R0, @H'F852",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F852",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63570,
          "name": null,
          "symbol": "ram_F852",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48645,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48661,
      "address_region": "program_or_external",
      "bytes": "1DF85C80",
      "text": "MOV:G.W @H'F85C, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F85C, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63580,
          "name": null,
          "symbol": "ram_F85C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48661,
          "action": "serial_reconstruction_evidence",
          "candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "candidate_kind": "candidate_sci1_tx_frame",
          "evidence": "tx_buffer_region",
          "evidence_summary": "TX buffer-region references cluster around H'F858-H'F85D",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            48645,
            48653,
            48661
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BE05",
            "H'BE0D",
            "H'BE15"
          ],
          "confidence": "high",
          "confidence_score": 0.95,
          "comment": "candidate/evidence-supported SCI1 6-byte TX frame; H'F858-H'F85D, checksum H'F85D seeded by H'005A; evidence: TX buffer-region references cluster around H'F858-H'F85D; confidence high"
        }
      ],
      "dataflow": {
        "block": 48645,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48665,
      "address_region": "program_or_external",
      "bytes": "1DF85490",
      "text": "MOV:G.W R0, @H'F854",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F854",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63572,
          "name": null,
          "symbol": "ram_F854",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48645,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48669,
      "address_region": "program_or_external",
      "bytes": "15F9C0061F",
      "text": "MOV:G.B #H'1F, @H'F9C0",
      "mnemonic": "MOV:G.B",
      "operands": "#H'1F, @H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48645,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48674,
      "address_region": "program_or_external",
      "bytes": "1EFC01",
      "text": "BSR loc_BA26",
      "mnemonic": "BSR",
      "operands": "loc_BA26",
      "kind": "call",
      "targets": [
        47654
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48645,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48677,
      "address_region": "program_or_external",
      "bytes": "2048",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48645,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48679,
      "address_region": "program_or_external",
      "bytes": "2046",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48679,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48681,
      "address_region": "program_or_external",
      "bytes": "15FAA4D7",
      "text": "BCLR.B #7, @H'FAA4",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'FAA4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64164,
          "name": null,
          "symbol": "ram_FAA4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48681,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48685,
      "address_region": "program_or_external",
      "bytes": "15FAA5F7",
      "text": "BTST.B #7, @H'FAA5",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FAA5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64165,
          "name": null,
          "symbol": "ram_FAA5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48681,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48689,
      "address_region": "program_or_external",
      "bytes": "273A",
      "text": "BEQ loc_BE6D",
      "mnemonic": "BEQ",
      "operands": "loc_BE6D",
      "kind": "branch",
      "targets": [
        48749
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48681,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48691,
      "address_region": "program_or_external",
      "bytes": "15FAA608",
      "text": "ADD:Q.B #1, @H'FAA6",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'FAA6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64166,
          "name": null,
          "symbol": "ram_FAA6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48691,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48695,
      "address_region": "program_or_external",
      "bytes": "15FAA60402",
      "text": "CMP:G.B #H'02, @H'FAA6",
      "mnemonic": "CMP:G.B",
      "operands": "#H'02, @H'FAA6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64166,
          "name": null,
          "symbol": "ram_FAA6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48691,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48700,
      "address_region": "program_or_external",
      "bytes": "250F",
      "text": "BCS loc_BE4D",
      "mnemonic": "BCS",
      "operands": "loc_BE4D",
      "kind": "branch",
      "targets": [
        48717
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48691,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48702,
      "address_region": "program_or_external",
      "bytes": "15F9C0061F",
      "text": "MOV:G.B #H'1F, @H'F9C0",
      "mnemonic": "MOV:G.B",
      "operands": "#H'1F, @H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48702,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48707,
      "address_region": "program_or_external",
      "bytes": "15FAA313",
      "text": "CLR.B @H'FAA3",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64163,
          "name": null,
          "symbol": "ram_FAA3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48702,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48711,
      "address_region": "program_or_external",
      "bytes": "15FAA213",
      "text": "CLR.B @H'FAA2",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48702,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48715,
      "address_region": "program_or_external",
      "bytes": "2020",
      "text": "BRA loc_BE6D",
      "mnemonic": "BRA",
      "operands": "loc_BE6D",
      "kind": "jump",
      "targets": [
        48749
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48702,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48717,
      "address_region": "program_or_external",
      "bytes": "15F8500607",
      "text": "MOV:G.B #H'07, @H'F850",
      "mnemonic": "MOV:G.B",
      "operands": "#H'07, @H'F850",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63568,
          "name": null,
          "symbol": "ram_F850",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48717,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48722,
      "address_region": "program_or_external",
      "bytes": "15F86180",
      "text": "MOV:G.B @H'F861, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F861, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63585,
          "name": null,
          "symbol": "ram_F861",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48717,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48726,
      "address_region": "program_or_external",
      "bytes": "15F85190",
      "text": "MOV:G.B R0, @H'F851",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F851",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63569,
          "name": null,
          "symbol": "ram_F851",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48717,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48730,
      "address_region": "program_or_external",
      "bytes": "1DF86280",
      "text": "MOV:G.W @H'F862, R0",
      "mnemonic": "MOV:G.W",
      "operands": "@H'F862, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63586,
          "name": null,
          "symbol": "ram_F862",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48717,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48734,
      "address_region": "program_or_external",
      "bytes": "1DF85290",
      "text": "MOV:G.W R0, @H'F852",
      "mnemonic": "MOV:G.W",
      "operands": "R0, @H'F852",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63570,
          "name": null,
          "symbol": "ram_F852",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48717,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48738,
      "address_region": "program_or_external",
      "bytes": "15F86480",
      "text": "MOV:G.B @H'F864, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F864, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63588,
          "name": null,
          "symbol": "ram_F864",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48717,
        "changes": [],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48742,
      "address_region": "program_or_external",
      "bytes": "15F85490",
      "text": "MOV:G.B R0, @H'F854",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'F854",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63572,
          "name": null,
          "symbol": "ram_F854",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48717,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48746,
      "address_region": "program_or_external",
      "bytes": "1EFBB9",
      "text": "BSR loc_BA26",
      "mnemonic": "BSR",
      "operands": "loc_BA26",
      "kind": "call",
      "targets": [
        47654
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48717,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48749,
      "address_region": "program_or_external",
      "bytes": "2000",
      "text": "BRA loc_BE6F",
      "mnemonic": "BRA",
      "operands": "loc_BE6F",
      "kind": "jump",
      "targets": [
        48751
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48749,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48751,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48751,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48752,
      "address_region": "program_or_external",
      "bytes": "15F9B983",
      "text": "MOV:G.B @H'F9B9, R3",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B9, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63929,
          "name": null,
          "symbol": "ram_F9B9",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48752,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R3 unknown after memory load"
        ]
      }
    },
    {
      "address": 48756,
      "address_region": "program_or_external",
      "bytes": "A312",
      "text": "EXTU.B R3",
      "mnemonic": "EXTU.B",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48752,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 48758,
      "address_region": "program_or_external",
      "bytes": "AB1A",
      "text": "SHLL.W R3",
      "mnemonic": "SHLL.W",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48752,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 48760,
      "address_region": "program_or_external",
      "bytes": "15F9B481",
      "text": "MOV:G.B @H'F9B4, R1",
      "mnemonic": "MOV:G.B",
      "operands": "@H'F9B4, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63924,
          "name": null,
          "symbol": "ram_F9B4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48752,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          }
        ],
        "notes": [
          "R1 unknown after memory load"
        ]
      }
    },
    {
      "address": 48764,
      "address_region": "program_or_external",
      "bytes": "A112",
      "text": "EXTU.B R1",
      "mnemonic": "EXTU.B",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48752,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 48766,
      "address_region": "program_or_external",
      "bytes": "A91A",
      "text": "SHLL.W R1",
      "mnemonic": "SHLL.W",
      "operands": "R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48752,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "unsupported:EXTU.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.W"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R1"
        ]
      }
    },
    {
      "address": 48768,
      "address_region": "program_or_external",
      "bytes": "A371",
      "text": "CMP:G.B R3, R1",
      "mnemonic": "CMP:G.B",
      "operands": "R3, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48768,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48770,
      "address_region": "program_or_external",
      "bytes": "270D",
      "text": "BEQ loc_BE91",
      "mnemonic": "BEQ",
      "operands": "loc_BE91",
      "kind": "branch",
      "targets": [
        48785
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48768,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48772,
      "address_region": "program_or_external",
      "bytes": "FBF97075",
      "text": "CMP:G.W @(-H'0690,R3), R5",
      "mnemonic": "CMP:G.W",
      "operands": "@(-H'0690,R3), R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48772,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48776,
      "address_region": "program_or_external",
      "bytes": "2713",
      "text": "BEQ loc_BE9D",
      "mnemonic": "BEQ",
      "operands": "loc_BE9D",
      "kind": "branch",
      "targets": [
        48797
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48772,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48778,
      "address_region": "program_or_external",
      "bytes": "A309",
      "text": "ADD:Q.B #2, R3",
      "mnemonic": "ADD:Q.B",
      "operands": "#2, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48778,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R3 unknown after arithmetic"
        ]
      }
    },
    {
      "address": 48780,
      "address_region": "program_or_external",
      "bytes": "043F53",
      "text": "AND.B #H'3F, R3",
      "mnemonic": "AND.B",
      "operands": "#H'3F, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48778,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 48783,
      "address_region": "program_or_external",
      "bytes": "20EF",
      "text": "BRA loc_BE80",
      "mnemonic": "BRA",
      "operands": "loc_BE80",
      "kind": "jump",
      "targets": [
        48768
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48778,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48785,
      "address_region": "program_or_external",
      "bytes": "F9F97095",
      "text": "MOV:G.W R5, @(-H'0690,R1)",
      "mnemonic": "MOV:G.W",
      "operands": "R5, @(-H'0690,R1)",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48785,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48789,
      "address_region": "program_or_external",
      "bytes": "15F9B408",
      "text": "ADD:Q.B #1, @H'F9B4",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F9B4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63924,
          "name": null,
          "symbol": "ram_F9B4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48785,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48793,
      "address_region": "program_or_external",
      "bytes": "15F9B4D5",
      "text": "BCLR.B #5, @H'F9B4",
      "mnemonic": "BCLR.B",
      "operands": "#5, @H'F9B4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63924,
          "name": null,
          "symbol": "ram_F9B4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48785,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48797,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48797,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48798,
      "address_region": "program_or_external",
      "bytes": "15FAA580",
      "text": "MOV:G.B @H'FAA5, R0",
      "mnemonic": "MOV:G.B",
      "operands": "@H'FAA5, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64165,
          "name": null,
          "symbol": "ram_FAA5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48798,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "memory_load"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after memory load"
        ]
      }
    },
    {
      "address": 48802,
      "address_region": "program_or_external",
      "bytes": "048050",
      "text": "AND.B #H'80, R0",
      "mnemonic": "AND.B",
      "operands": "#H'80, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48798,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "memory_load"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48805,
      "address_region": "program_or_external",
      "bytes": "15FAA350",
      "text": "AND.B @H'FAA3, R0",
      "mnemonic": "AND.B",
      "operands": "@H'FAA3, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64163,
          "name": null,
          "symbol": "ram_FAA3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48798,
        "changes": [],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 48809,
      "address_region": "program_or_external",
      "bytes": "15FAA390",
      "text": "MOV:G.B R0, @H'FAA3",
      "mnemonic": "MOV:G.B",
      "operands": "R0, @H'FAA3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64163,
          "name": null,
          "symbol": "ram_FAA3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48798,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48813,
      "address_region": "program_or_external",
      "bytes": "2606",
      "text": "BNE loc_BEB5",
      "mnemonic": "BNE",
      "operands": "loc_BEB5",
      "kind": "branch",
      "targets": [
        48821
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48798,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48815,
      "address_region": "program_or_external",
      "bytes": "15FAA213",
      "text": "CLR.B @H'FAA2",
      "mnemonic": "CLR.B",
      "operands": "@H'FAA2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64162,
          "name": null,
          "symbol": "ram_FAA2",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48815,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48819,
      "address_region": "program_or_external",
      "bytes": "2033",
      "text": "BRA loc_BEE8",
      "mnemonic": "BRA",
      "operands": "loc_BEE8",
      "kind": "jump",
      "targets": [
        48872
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48815,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48821,
      "address_region": "program_or_external",
      "bytes": "1DF9C616",
      "text": "TST.W @H'F9C6",
      "mnemonic": "TST.W",
      "operands": "@H'F9C6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63942,
          "name": null,
          "symbol": "ram_F9C6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48821,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48825,
      "address_region": "program_or_external",
      "bytes": "262D",
      "text": "BNE loc_BEE8",
      "mnemonic": "BNE",
      "operands": "loc_BEE8",
      "kind": "branch",
      "targets": [
        48872
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48821,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48827,
      "address_region": "program_or_external",
      "bytes": "15F9C816",
      "text": "TST.B @H'F9C8",
      "mnemonic": "TST.B",
      "operands": "@H'F9C8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63944,
          "name": null,
          "symbol": "ram_F9C8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48827,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48831,
      "address_region": "program_or_external",
      "bytes": "2723",
      "text": "BEQ loc_BEE4",
      "mnemonic": "BEQ",
      "operands": "loc_BEE4",
      "kind": "branch",
      "targets": [
        48868
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48827,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48833,
      "address_region": "program_or_external",
      "bytes": "15F9C80C",
      "text": "ADD:Q.B #-1, @H'F9C8",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F9C8",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63944,
          "name": null,
          "symbol": "ram_F9C8",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48833,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48837,
      "address_region": "program_or_external",
      "bytes": "1DF9C60701F4",
      "text": "MOV:G.W #H'01F4, @H'F9C6",
      "mnemonic": "MOV:G.W",
      "operands": "#H'01F4, @H'F9C6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63942,
          "name": null,
          "symbol": "ram_F9C6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48833,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48843,
      "address_region": "program_or_external",
      "bytes": "15FAA3F7",
      "text": "BTST.B #7, @H'FAA3",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FAA3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64163,
          "name": null,
          "symbol": "ram_FAA3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48833,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48847,
      "address_region": "program_or_external",
      "bytes": "2717",
      "text": "BEQ loc_BEE8",
      "mnemonic": "BEQ",
      "operands": "loc_BEE8",
      "kind": "branch",
      "targets": [
        48872
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48833,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48849,
      "address_region": "program_or_external",
      "bytes": "15F9C313",
      "text": "CLR.B @H'F9C3",
      "mnemonic": "CLR.B",
      "operands": "@H'F9C3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63939,
          "name": null,
          "symbol": "ram_F9C3",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48849,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48853,
      "address_region": "program_or_external",
      "bytes": "1EFB4E",
      "text": "BSR loc_BA26",
      "mnemonic": "BSR",
      "operands": "loc_BA26",
      "kind": "call",
      "targets": [
        47654
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48849,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 48856,
      "address_region": "program_or_external",
      "bytes": "200E",
      "text": "BRA loc_BEE8",
      "mnemonic": "BRA",
      "operands": "loc_BEE8",
      "kind": "jump",
      "targets": [
        48872
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48849,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48868,
      "address_region": "program_or_external",
      "bytes": "15F9C513",
      "text": "CLR.B @H'F9C5",
      "mnemonic": "CLR.B",
      "operands": "@H'F9C5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63941,
          "name": null,
          "symbol": "ram_F9C5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48868,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48872,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48872,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48874,
      "address_region": "program_or_external",
      "bytes": "15FE91D5",
      "text": "BCLR.B #5, @FRT1_TCSR",
      "mnemonic": "BCLR.B",
      "operands": "#5, @FRT1_TCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65169,
          "name": "FRT1_TCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear OCFA (bit 5) of FRT1_TCSR",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48874,
          "action": "serial_reconstruction_ram_role",
          "role_name": "post_tx_report_delay",
          "role_kind": "candidate_ram_role",
          "role_address": 63936,
          "role_address_hex": "H'F9C0",
          "evidence": "frt1_ocia_periodic_tick_isr",
          "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
          "evidence_addresses": [
            48874
          ],
          "evidence_addresses_hex": [
            "H'BEEA"
          ],
          "confidence": "candidate/evidence-supported",
          "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported"
        },
        {
          "address": 48874,
          "action": "serial_reconstruction_ram_role",
          "role_name": "secondary_tx_report_delay",
          "role_kind": "candidate_ram_role",
          "role_address": 63937,
          "role_address_hex": "H'F9C1",
          "evidence": "frt1_ocia_periodic_tick_isr",
          "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
          "evidence_addresses": [
            48874
          ],
          "evidence_addresses_hex": [
            "H'BEEA"
          ],
          "confidence": "candidate/evidence-supported",
          "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported"
        },
        {
          "address": 48874,
          "action": "serial_reconstruction_ram_role",
          "role_name": "periodic_report_countdown",
          "role_kind": "candidate_ram_role",
          "role_address": 63942,
          "role_address_hex": "H'F9C6",
          "evidence": "frt1_ocia_periodic_tick_isr",
          "evidence_summary": "candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA",
          "evidence_addresses": [
            48874
          ],
          "evidence_addresses_hex": [
            "H'BEEA"
          ],
          "confidence": "candidate/evidence-supported",
          "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic tick ISR at H'BEEA for FRT1 OCIA vector H'0062 clears OCFA; confidence candidate/evidence-supported"
        }
      ],
      "dataflow": {
        "block": 48874,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48878,
      "address_region": "program_or_external",
      "bytes": "15F9C016",
      "text": "TST.B @H'F9C0",
      "mnemonic": "TST.B",
      "operands": "@H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48878,
          "action": "serial_reconstruction_ram_role",
          "role_name": "post_tx_report_delay",
          "role_kind": "candidate_ram_role",
          "role_address": 63936,
          "role_address_hex": "H'F9C0",
          "evidence": "post_tx_report_delay_tick_decrement",
          "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
          "evidence_addresses": [
            48878,
            48884
          ],
          "evidence_addresses_hex": [
            "H'BEEE",
            "H'BEF4"
          ],
          "confidence": "candidate/evidence-supported",
          "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
        }
      ],
      "dataflow": {
        "block": 48874,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48882,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_BEF8",
      "mnemonic": "BEQ",
      "operands": "loc_BEF8",
      "kind": "branch",
      "targets": [
        48888
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48874,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48884,
      "address_region": "program_or_external",
      "bytes": "15F9C00C",
      "text": "ADD:Q.B #-1, @H'F9C0",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F9C0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63936,
          "name": null,
          "symbol": "ram_F9C0",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48884,
          "action": "serial_reconstruction_ram_role",
          "role_name": "post_tx_report_delay",
          "role_kind": "candidate_ram_role",
          "role_address": 63936,
          "role_address_hex": "H'F9C0",
          "evidence": "post_tx_report_delay_tick_decrement",
          "evidence_summary": "candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
          "evidence_addresses": [
            48878,
            48884
          ],
          "evidence_addresses_hex": [
            "H'BEEE",
            "H'BEF4"
          ],
          "confidence": "candidate/evidence-supported",
          "comment": "candidate/evidence-supported RAM role post_tx_report_delay at H'F9C0; evidence: candidate post-TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
        }
      ],
      "dataflow": {
        "block": 48884,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48888,
      "address_region": "program_or_external",
      "bytes": "15F9C116",
      "text": "TST.B @H'F9C1",
      "mnemonic": "TST.B",
      "operands": "@H'F9C1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63937,
          "name": null,
          "symbol": "ram_F9C1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48888,
          "action": "serial_reconstruction_ram_role",
          "role_name": "secondary_tx_report_delay",
          "role_kind": "candidate_ram_role",
          "role_address": 63937,
          "role_address_hex": "H'F9C1",
          "evidence": "secondary_tx_report_delay_tick_decrement",
          "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
          "evidence_addresses": [
            48888,
            48894
          ],
          "evidence_addresses_hex": [
            "H'BEF8",
            "H'BEFE"
          ],
          "confidence": "candidate/evidence-supported",
          "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
        }
      ],
      "dataflow": {
        "block": 48888,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48892,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_BF02",
      "mnemonic": "BEQ",
      "operands": "loc_BF02",
      "kind": "branch",
      "targets": [
        48898
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48888,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48894,
      "address_region": "program_or_external",
      "bytes": "15F9C10C",
      "text": "ADD:Q.B #-1, @H'F9C1",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F9C1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63937,
          "name": null,
          "symbol": "ram_F9C1",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48894,
          "action": "serial_reconstruction_ram_role",
          "role_name": "secondary_tx_report_delay",
          "role_kind": "candidate_ram_role",
          "role_address": 63937,
          "role_address_hex": "H'F9C1",
          "evidence": "secondary_tx_report_delay_tick_decrement",
          "evidence_summary": "candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR",
          "evidence_addresses": [
            48888,
            48894
          ],
          "evidence_addresses_hex": [
            "H'BEF8",
            "H'BEFE"
          ],
          "confidence": "candidate/evidence-supported",
          "comment": "candidate/evidence-supported RAM role secondary_tx_report_delay at H'F9C1; evidence: candidate secondary TX/report delay timer is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
        }
      ],
      "dataflow": {
        "block": 48894,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48898,
      "address_region": "program_or_external",
      "bytes": "1DF9C616",
      "text": "TST.W @H'F9C6",
      "mnemonic": "TST.W",
      "operands": "@H'F9C6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63942,
          "name": null,
          "symbol": "ram_F9C6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48898,
          "action": "serial_reconstruction_ram_role",
          "role_name": "periodic_report_countdown",
          "role_kind": "candidate_ram_role",
          "role_address": 63942,
          "role_address_hex": "H'F9C6",
          "evidence": "periodic_report_countdown_tick_decrement",
          "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR",
          "evidence_addresses": [
            48898,
            48904
          ],
          "evidence_addresses_hex": [
            "H'BF02",
            "H'BF08"
          ],
          "confidence": "candidate/evidence-supported",
          "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
        }
      ],
      "dataflow": {
        "block": 48898,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48902,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_BF0C",
      "mnemonic": "BEQ",
      "operands": "loc_BF0C",
      "kind": "branch",
      "targets": [
        48908
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48898,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48904,
      "address_region": "program_or_external",
      "bytes": "1DF9C60C",
      "text": "ADD:Q.W #-1, @H'F9C6",
      "mnemonic": "ADD:Q.W",
      "operands": "#-1, @H'F9C6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63942,
          "name": null,
          "symbol": "ram_F9C6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "serial_reconstruction": [
        {
          "address": 48904,
          "action": "serial_reconstruction_ram_role",
          "role_name": "periodic_report_countdown",
          "role_kind": "candidate_ram_role",
          "role_address": 63942,
          "role_address_hex": "H'F9C6",
          "evidence": "periodic_report_countdown_tick_decrement",
          "evidence_summary": "candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR",
          "evidence_addresses": [
            48898,
            48904
          ],
          "evidence_addresses_hex": [
            "H'BF02",
            "H'BF08"
          ],
          "confidence": "candidate/evidence-supported",
          "comment": "candidate/evidence-supported RAM role periodic_report_countdown at H'F9C6; evidence: candidate periodic report countdown is decremented by the FRT1 OCIA periodic tick ISR; confidence candidate/evidence-supported"
        }
      ],
      "dataflow": {
        "block": 48904,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48908,
      "address_region": "program_or_external",
      "bytes": "15F6F6F7",
      "text": "BTST.B #7, @H'F6F6",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'F6F6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63222,
          "name": null,
          "symbol": "ram_F6F6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48908,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48912,
      "address_region": "program_or_external",
      "bytes": "2710",
      "text": "BEQ loc_BF22",
      "mnemonic": "BEQ",
      "operands": "loc_BF22",
      "kind": "branch",
      "targets": [
        48930
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48908,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48914,
      "address_region": "program_or_external",
      "bytes": "1DF6F416",
      "text": "TST.W @H'F6F4",
      "mnemonic": "TST.W",
      "operands": "@H'F6F4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63220,
          "name": null,
          "symbol": "ram_F6F4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48914,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48918,
      "address_region": "program_or_external",
      "bytes": "2606",
      "text": "BNE loc_BF1E",
      "mnemonic": "BNE",
      "operands": "loc_BF1E",
      "kind": "branch",
      "targets": [
        48926
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48914,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48920,
      "address_region": "program_or_external",
      "bytes": "15F6F6C5",
      "text": "BSET.B #5, @H'F6F6",
      "mnemonic": "BSET.B",
      "operands": "#5, @H'F6F6",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63222,
          "name": null,
          "symbol": "ram_F6F6",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48920,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48924,
      "address_region": "program_or_external",
      "bytes": "2004",
      "text": "BRA loc_BF22",
      "mnemonic": "BRA",
      "operands": "loc_BF22",
      "kind": "jump",
      "targets": [
        48930
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48920,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48926,
      "address_region": "program_or_external",
      "bytes": "1DF6F40C",
      "text": "ADD:Q.W #-1, @H'F6F4",
      "mnemonic": "ADD:Q.W",
      "operands": "#-1, @H'F6F4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63220,
          "name": null,
          "symbol": "ram_F6F4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48926,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48930,
      "address_region": "program_or_external",
      "bytes": "0A",
      "text": "RTE",
      "mnemonic": "RTE",
      "operands": "",
      "kind": "rte",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 13,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48930,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48931,
      "address_region": "program_or_external",
      "bytes": "15FEA1D5",
      "text": "BCLR.B #5, @FRT2_TCSR",
      "mnemonic": "BCLR.B",
      "operands": "#5, @FRT2_TCSR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65185,
          "name": "FRT2_TCSR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear OCFA (bit 5) of FRT2_TCSR",
      "valid": true,
      "dataflow": {
        "block": 48931,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48935,
      "address_region": "program_or_external",
      "bytes": "15F9C416",
      "text": "TST.B @H'F9C4",
      "mnemonic": "TST.B",
      "operands": "@H'F9C4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63940,
          "name": null,
          "symbol": "ram_F9C4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48931,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48939,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_BF31",
      "mnemonic": "BEQ",
      "operands": "loc_BF31",
      "kind": "branch",
      "targets": [
        48945
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48931,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48941,
      "address_region": "program_or_external",
      "bytes": "15F9C40C",
      "text": "ADD:Q.B #-1, @H'F9C4",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F9C4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63940,
          "name": null,
          "symbol": "ram_F9C4",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48941,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48945,
      "address_region": "program_or_external",
      "bytes": "15F9C516",
      "text": "TST.B @H'F9C5",
      "mnemonic": "TST.B",
      "operands": "@H'F9C5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63941,
          "name": null,
          "symbol": "ram_F9C5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48945,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48949,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_BF3B",
      "mnemonic": "BEQ",
      "operands": "loc_BF3B",
      "kind": "branch",
      "targets": [
        48955
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48945,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48951,
      "address_region": "program_or_external",
      "bytes": "15F9C50C",
      "text": "ADD:Q.B #-1, @H'F9C5",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F9C5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63941,
          "name": null,
          "symbol": "ram_F9C5",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48951,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48955,
      "address_region": "program_or_external",
      "bytes": "15F72416",
      "text": "TST.B @H'F724",
      "mnemonic": "TST.B",
      "operands": "@H'F724",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63268,
          "name": null,
          "symbol": "ram_F724",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48955,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48959,
      "address_region": "program_or_external",
      "bytes": "2706",
      "text": "BEQ loc_BF47",
      "mnemonic": "BEQ",
      "operands": "loc_BF47",
      "kind": "branch",
      "targets": [
        48967
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48955,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48961,
      "address_region": "program_or_external",
      "bytes": "15F7240C",
      "text": "ADD:Q.B #-1, @H'F724",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F724",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63268,
          "name": null,
          "symbol": "ram_F724",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48961,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48965,
      "address_region": "program_or_external",
      "bytes": "2009",
      "text": "BRA loc_BF50",
      "mnemonic": "BRA",
      "operands": "loc_BF50",
      "kind": "jump",
      "targets": [
        48976
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48961,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48967,
      "address_region": "program_or_external",
      "bytes": "15F7240603",
      "text": "MOV:G.B #H'03, @H'F724",
      "mnemonic": "MOV:G.B",
      "operands": "#H'03, @H'F724",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63268,
          "name": null,
          "symbol": "ram_F724",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48967,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48972,
      "address_region": "program_or_external",
      "bytes": "15F72315",
      "text": "NOT.B @H'F723",
      "mnemonic": "NOT.B",
      "operands": "@H'F723",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63267,
          "name": null,
          "symbol": "ram_F723",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48967,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48976,
      "address_region": "program_or_external",
      "bytes": "15FB03F7",
      "text": "BTST.B #7, @H'FB03",
      "mnemonic": "BTST.B",
      "operands": "#7, @H'FB03",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
          "name": null,
          "symbol": "ram_FB03",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48976,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48980,
      "address_region": "program_or_external",
      "bytes": "2717",
      "text": "BEQ loc_BF6D",
      "mnemonic": "BEQ",
      "operands": "loc_BF6D",
      "kind": "branch",
      "targets": [
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      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48976,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48982,
      "address_region": "program_or_external",
      "bytes": "15FB0216",
      "text": "TST.B @H'FB02",
      "mnemonic": "TST.B",
      "operands": "@H'FB02",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64258,
          "name": null,
          "symbol": "ram_FB02",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48982,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48986,
      "address_region": "program_or_external",
      "bytes": "2706",
      "text": "BEQ loc_BF62",
      "mnemonic": "BEQ",
      "operands": "loc_BF62",
      "kind": "branch",
      "targets": [
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      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48982,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48988,
      "address_region": "program_or_external",
      "bytes": "15FB020C",
      "text": "ADD:Q.B #-1, @H'FB02",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'FB02",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64258,
          "name": null,
          "symbol": "ram_FB02",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48988,
        "changes": [
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            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48992,
      "address_region": "program_or_external",
      "bytes": "200B",
      "text": "BRA loc_BF6D",
      "mnemonic": "BRA",
      "operands": "loc_BF6D",
      "kind": "jump",
      "targets": [
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      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48988,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 48994,
      "address_region": "program_or_external",
      "bytes": "15FB03D7",
      "text": "BCLR.B #7, @H'FB03",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'FB03",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 64259,
          "name": null,
          "symbol": "ram_FB03",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48994,
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            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 48998,
      "address_region": "program_or_external",
      "bytes": "123F",
      "text": "STM.W {R0,R1,R2,R3,R4,R5}, @-SP",
      "mnemonic": "STM.W",
      "operands": "{R0,R1,R2,R3,R4,R5}, @-SP",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 24,
        "note": "6+3n, n=6",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48994,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49000,
      "address_region": "program_or_external",
      "bytes": "1E8984",
      "text": "BSR loc_48EF",
      "mnemonic": "BSR",
      "operands": "loc_48EF",
      "kind": "call",
      "targets": [
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      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48994,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "register",
            "name": "R2",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
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            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
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          },
          {
            "kind": "register",
            "name": "R4",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
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            "kind": "register",
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              "reason": "block_entry"
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            "after": {
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              "reason": "call"
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          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
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              "known": false,
              "reason": "call"
            }
          },
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            "kind": "register",
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              "known": false,
              "reason": "block_entry"
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              "reason": "call"
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          },
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            "kind": "control",
            "name": "CCR",
            "before": {
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              "reason": "flags"
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              "reason": "call"
            }
          },
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            "kind": "control",
            "name": "BR",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
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          },
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            "kind": "control",
            "name": "EP",
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              "reason": "block_entry"
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              "reason": "call"
            }
          },
          {
            "kind": "control",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          },
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            "kind": "control",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
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          },
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            "kind": "control",
            "name": "SR",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
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    },
    {
      "address": 49003,
      "address_region": "program_or_external",
      "bytes": "023F",
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      "mnemonic": "LDM.W",
      "operands": "@SP+, {R0,R1,R2,R3,R4,R5}",
      "kind": "normal",
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      "cycles": {
        "cycles": 30,
        "note": "6+4n, n=6",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 48994,
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            "kind": "register",
            "name": "R0",
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              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
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            "kind": "register",
            "name": "R1",
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              "known": false,
              "reason": "call"
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              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
          {
            "kind": "register",
            "name": "R2",
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              "known": false,
              "reason": "call"
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            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
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          },
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            "kind": "register",
            "name": "R3",
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              "known": false,
              "reason": "call"
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            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
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          },
          {
            "kind": "register",
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            "after": {
              "known": false,
              "reason": "unsupported:LDM.W"
            }
          },
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            "kind": "register",
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              "reason": "call"
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              "reason": "unsupported:LDM.W"
            }
          }
        ],
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        ]
      }
    },
    {
      "address": 49005,
      "address_region": "program_or_external",
      "bytes": "15F76C16",
      "text": "TST.B @H'F76C",
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      "operands": "@H'F76C",
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      "targets": [],
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        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63340,
          "name": null,
          "symbol": "ram_F76C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
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        "block": 49005,
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            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
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      }
    },
    {
      "address": 49009,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_BF77",
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      "operands": "loc_BF77",
      "kind": "branch",
      "targets": [
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      ],
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        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49005,
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        "notes": []
      }
    },
    {
      "address": 49011,
      "address_region": "program_or_external",
      "bytes": "15F76C0C",
      "text": "ADD:Q.B #-1, @H'F76C",
      "mnemonic": "ADD:Q.B",
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        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63340,
          "name": null,
          "symbol": "ram_F76C",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
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            "kind": "control",
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              "known": false,
              "reason": "flags"
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          }
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        "notes": []
      }
    },
    {
      "address": 49015,
      "address_region": "program_or_external",
      "bytes": "15F84016",
      "text": "TST.B @H'F840",
      "mnemonic": "TST.B",
      "operands": "@H'F840",
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        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63552,
          "name": null,
          "symbol": "ram_F840",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
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            "kind": "control",
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              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "flags"
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          }
        ],
        "notes": []
      }
    },
    {
      "address": 49019,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_BF81",
      "mnemonic": "BEQ",
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        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49015,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49021,
      "address_region": "program_or_external",
      "bytes": "15F8400C",
      "text": "ADD:Q.B #-1, @H'F840",
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      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63552,
          "name": null,
          "symbol": "ram_F840",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49021,
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          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49025,
      "address_region": "program_or_external",
      "bytes": "15F72616",
      "text": "TST.B @H'F726",
      "mnemonic": "TST.B",
      "operands": "@H'F726",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63270,
          "name": null,
          "symbol": "ram_F726",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
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      "dataflow": {
        "block": 49025,
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          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
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            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49029,
      "address_region": "program_or_external",
      "bytes": "271C",
      "text": "BEQ loc_BFA3",
      "mnemonic": "BEQ",
      "operands": "loc_BFA3",
      "kind": "branch",
      "targets": [
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        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49025,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49031,
      "address_region": "program_or_external",
      "bytes": "15F7260C",
      "text": "ADD:Q.B #-1, @H'F726",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F726",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63270,
          "name": null,
          "symbol": "ram_F726",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49031,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
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              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49035,
      "address_region": "program_or_external",
      "bytes": "2616",
      "text": "BNE loc_BFA3",
      "mnemonic": "BNE",
      "operands": "loc_BFA3",
      "kind": "branch",
      "targets": [
        49059
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49031,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49037,
      "address_region": "program_or_external",
      "bytes": "15F713D6",
      "text": "BCLR.B #6, @H'F713",
      "mnemonic": "BCLR.B",
      "operands": "#6, @H'F713",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63251,
          "name": null,
          "symbol": "ram_F713",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49037,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49041,
      "address_region": "program_or_external",
      "bytes": "2610",
      "text": "BNE loc_BFA3",
      "mnemonic": "BNE",
      "operands": "loc_BFA3",
      "kind": "branch",
      "targets": [
        49059
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49037,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49043,
      "address_region": "program_or_external",
      "bytes": "15F711D7",
      "text": "BCLR.B #7, @H'F711",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F711",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63249,
          "name": null,
          "symbol": "ram_F711",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49043,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49047,
      "address_region": "program_or_external",
      "bytes": "15F711D6",
      "text": "BCLR.B #6, @H'F711",
      "mnemonic": "BCLR.B",
      "operands": "#6, @H'F711",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63249,
          "name": null,
          "symbol": "ram_F711",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49043,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49051,
      "address_region": "program_or_external",
      "bytes": "15F711D5",
      "text": "BCLR.B #5, @H'F711",
      "mnemonic": "BCLR.B",
      "operands": "#5, @H'F711",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63249,
          "name": null,
          "symbol": "ram_F711",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49043,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49055,
      "address_region": "program_or_external",
      "bytes": "15F711D4",
      "text": "BCLR.B #4, @H'F711",
      "mnemonic": "BCLR.B",
      "operands": "#4, @H'F711",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63249,
          "name": null,
          "symbol": "ram_F711",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49043,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49059,
      "address_region": "program_or_external",
      "bytes": "15F79716",
      "text": "TST.B @H'F797",
      "mnemonic": "TST.B",
      "operands": "@H'F797",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63383,
          "name": null,
          "symbol": "ram_F797",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49059,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49063,
      "address_region": "program_or_external",
      "bytes": "270A",
      "text": "BEQ loc_BFB3",
      "mnemonic": "BEQ",
      "operands": "loc_BFB3",
      "kind": "branch",
      "targets": [
        49075
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49059,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49065,
      "address_region": "program_or_external",
      "bytes": "15F7970C",
      "text": "ADD:Q.B #-1, @H'F797",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F797",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63383,
          "name": null,
          "symbol": "ram_F797",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49065,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49069,
      "address_region": "program_or_external",
      "bytes": "2604",
      "text": "BNE loc_BFB3",
      "mnemonic": "BNE",
      "operands": "loc_BFB3",
      "kind": "branch",
      "targets": [
        49075
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49065,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49071,
      "address_region": "program_or_external",
      "bytes": "15F731D7",
      "text": "BCLR.B #7, @H'F731",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49071,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49075,
      "address_region": "program_or_external",
      "bytes": "15F79816",
      "text": "TST.B @H'F798",
      "mnemonic": "TST.B",
      "operands": "@H'F798",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63384,
          "name": null,
          "symbol": "ram_F798",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49075,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49079,
      "address_region": "program_or_external",
      "bytes": "270A",
      "text": "BEQ loc_BFC3",
      "mnemonic": "BEQ",
      "operands": "loc_BFC3",
      "kind": "branch",
      "targets": [
        49091
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49075,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49081,
      "address_region": "program_or_external",
      "bytes": "15F7980C",
      "text": "ADD:Q.B #-1, @H'F798",
      "mnemonic": "ADD:Q.B",
      "operands": "#-1, @H'F798",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63384,
          "name": null,
          "symbol": "ram_F798",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49081,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49085,
      "address_region": "program_or_external",
      "bytes": "2604",
      "text": "BNE loc_BFC3",
      "mnemonic": "BNE",
      "operands": "loc_BFC3",
      "kind": "branch",
      "targets": [
        49091
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49081,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49087,
      "address_region": "program_or_external",
      "bytes": "15F731D7",
      "text": "BCLR.B #7, @H'F731",
      "mnemonic": "BCLR.B",
      "operands": "#7, @H'F731",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63281,
          "name": null,
          "symbol": "ram_F731",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49087,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49091,
      "address_region": "program_or_external",
      "bytes": "0A",
      "text": "RTE",
      "mnemonic": "RTE",
      "operands": "",
      "kind": "rte",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "base_cycles": 13,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49091,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49092,
      "address_region": "program_or_external",
      "bytes": "15FEECF7",
      "text": "BTST.B #7, @WDT_TCSR_R",
      "mnemonic": "BTST.B",
      "operands": "#7, @WDT_TCSR_R",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65260,
          "name": "WDT_TCSR_R",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49092,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49096,
      "address_region": "program_or_external",
      "bytes": "1DFEEC07A53F",
      "text": "MOV:G.W #H'A53F, @WDT_TCSR_R",
      "mnemonic": "MOV:G.W",
      "operands": "#H'A53F, @WDT_TCSR_R",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 11,
        "base_cycles": 9,
        "alignment_adjustment": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65260,
          "name": "WDT_TCSR_R",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "WDT_TCSR_R = H'A53F (OVF=0 WT/IT=0 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, interval IRQ0, clock phi/4096)",
      "valid": true,
      "dataflow": {
        "block": 49092,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49102,
      "address_region": "program_or_external",
      "bytes": "15F79408",
      "text": "ADD:Q.B #1, @H'F794",
      "mnemonic": "ADD:Q.B",
      "operands": "#1, @H'F794",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63380,
          "name": null,
          "symbol": "ram_F794",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49092,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49106,
      "address_region": "program_or_external",
      "bytes": "15F794040A",
      "text": "CMP:G.B #H'0A, @H'F794",
      "mnemonic": "CMP:G.B",
      "operands": "#H'0A, @H'F794",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63380,
          "name": null,
          "symbol": "ram_F794",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49092,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49111,
      "address_region": "program_or_external",
      "bytes": "2606",
      "text": "BNE loc_BFDF",
      "mnemonic": "BNE",
      "operands": "loc_BFDF",
      "kind": "branch",
      "targets": [
        49119
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49092,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49113,
      "address_region": "program_or_external",
      "bytes": "1DFEEC07A57F",
      "text": "MOV:G.W #H'A57F, @WDT_TCSR_R",
      "mnemonic": "MOV:G.W",
      "operands": "#H'A57F, @WDT_TCSR_R",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 9,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65260,
          "name": "WDT_TCSR_R",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "WDT_TCSR_R = H'A57F (OVF=0 WT/IT=1 TME=1 CKS2=1 CKS1=1 CKS0=1; TCSR password H'A5, WDT enabled, watchdog NMI, clock phi/4096)",
      "valid": true,
      "dataflow": {
        "block": 49113,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49119,
      "address_region": "program_or_external",
      "bytes": "0A",
      "text": "RTE",
      "mnemonic": "RTE",
      "operands": "",
      "kind": "rte",
      "targets": [],
      "cycles": {
        "cycles": 14,
        "base_cycles": 13,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49119,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49120,
      "address_region": "program_or_external",
      "bytes": "15F840060A",
      "text": "MOV:G.B #H'0A, @H'F840",
      "mnemonic": "MOV:G.B",
      "operands": "#H'0A, @H'F840",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63552,
          "name": null,
          "symbol": "ram_F840",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49120,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49125,
      "address_region": "program_or_external",
      "bytes": "AD82",
      "text": "MOV:G.W R5, R2",
      "mnemonic": "MOV:G.W",
      "operands": "R5, R2",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49125,
        "changes": [
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R2 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49127,
      "address_region": "program_or_external",
      "bytes": "0E27",
      "text": "BSR loc_C010",
      "mnemonic": "BSR",
      "operands": "loc_C010",
      "kind": "call",
      "targets": [
        49168
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49125,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49129,
      "address_region": "program_or_external",
      "bytes": "0E4E",
      "text": "BSR loc_C039",
      "mnemonic": "BSR",
      "operands": "loc_C039",
      "kind": "call",
      "targets": [
        49209
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49125,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49131,
      "address_region": "program_or_external",
      "bytes": "AA75",
      "text": "CMP:G.W R2, R5",
      "mnemonic": "CMP:G.W",
      "operands": "R2, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49125,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49133,
      "address_region": "program_or_external",
      "bytes": "270E",
      "text": "BEQ loc_BFFD",
      "mnemonic": "BEQ",
      "operands": "loc_BFFD",
      "kind": "branch",
      "targets": [
        49149
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49125,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49135,
      "address_region": "program_or_external",
      "bytes": "15F84016",
      "text": "TST.B @H'F840",
      "mnemonic": "TST.B",
      "operands": "@H'F840",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63552,
          "name": null,
          "symbol": "ram_F840",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49135,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49139,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_BFF9",
      "mnemonic": "BEQ",
      "operands": "loc_BFF9",
      "kind": "branch",
      "targets": [
        49145
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49135,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49141,
      "address_region": "program_or_external",
      "bytes": "AA85",
      "text": "MOV:G.W R2, R5",
      "mnemonic": "MOV:G.W",
      "operands": "R2, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49141,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R5 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49143,
      "address_region": "program_or_external",
      "bytes": "20EC",
      "text": "BRA loc_BFE5",
      "mnemonic": "BRA",
      "operands": "loc_BFE5",
      "kind": "jump",
      "targets": [
        49125
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49141,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49145,
      "address_region": "program_or_external",
      "bytes": "15F841C7",
      "text": "BSET.B #7, @H'F841",
      "mnemonic": "BSET.B",
      "operands": "#7, @H'F841",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63553,
          "name": null,
          "symbol": "ram_F841",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49145,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49149,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49149,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49150,
      "address_region": "program_or_external",
      "bytes": "15F840060A",
      "text": "MOV:G.B #H'0A, @H'F840",
      "mnemonic": "MOV:G.B",
      "operands": "#H'0A, @H'F840",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63552,
          "name": null,
          "symbol": "ram_F840",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49150,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49155,
      "address_region": "program_or_external",
      "bytes": "0E34",
      "text": "BSR loc_C039",
      "mnemonic": "BSR",
      "operands": "loc_C039",
      "kind": "call",
      "targets": [
        49209
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49150,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49157,
      "address_region": "program_or_external",
      "bytes": "15F84016",
      "text": "TST.B @H'F840",
      "mnemonic": "TST.B",
      "operands": "@H'F840",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63552,
          "name": null,
          "symbol": "ram_F840",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49150,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49161,
      "address_region": "program_or_external",
      "bytes": "2604",
      "text": "BNE loc_C00F",
      "mnemonic": "BNE",
      "operands": "loc_C00F",
      "kind": "branch",
      "targets": [
        49167
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49150,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49163,
      "address_region": "program_or_external",
      "bytes": "15F841C6",
      "text": "BSET.B #6, @H'F841",
      "mnemonic": "BSET.B",
      "operands": "#6, @H'F841",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63553,
          "name": null,
          "symbol": "ram_F841",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49163,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49167,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49167,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49168,
      "address_region": "program_or_external",
      "bytes": "0E58",
      "text": "BSR loc_C06A",
      "mnemonic": "BSR",
      "operands": "loc_C06A",
      "kind": "call",
      "targets": [
        49258
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49168,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49170,
      "address_region": "program_or_external",
      "bytes": "15F84016",
      "text": "TST.B @H'F840",
      "mnemonic": "TST.B",
      "operands": "@H'F840",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63552,
          "name": null,
          "symbol": "ram_F840",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49170,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49174,
      "address_region": "program_or_external",
      "bytes": "2720",
      "text": "BEQ loc_C038",
      "mnemonic": "BEQ",
      "operands": "loc_C038",
      "kind": "branch",
      "targets": [
        49208
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49170,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49176,
      "address_region": "program_or_external",
      "bytes": "1E0106",
      "text": "BSR loc_C121",
      "mnemonic": "BSR",
      "operands": "loc_C121",
      "kind": "call",
      "targets": [
        49441
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49176,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49179,
      "address_region": "program_or_external",
      "bytes": "A380",
      "text": "MOV:G.B R3, R0",
      "mnemonic": "MOV:G.B",
      "operands": "R3, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49176,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49181,
      "address_region": "program_or_external",
      "bytes": "0E6C",
      "text": "BSR loc_C08B",
      "mnemonic": "BSR",
      "operands": "loc_C08B",
      "kind": "call",
      "targets": [
        49291
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49176,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49183,
      "address_region": "program_or_external",
      "bytes": "27F1",
      "text": "BEQ loc_C012",
      "mnemonic": "BEQ",
      "operands": "loc_C012",
      "kind": "branch",
      "targets": [
        49170
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49176,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49185,
      "address_region": "program_or_external",
      "bytes": "A480",
      "text": "MOV:G.B R4, R0",
      "mnemonic": "MOV:G.B",
      "operands": "R4, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49185,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49187,
      "address_region": "program_or_external",
      "bytes": "0E66",
      "text": "BSR loc_C08B",
      "mnemonic": "BSR",
      "operands": "loc_C08B",
      "kind": "call",
      "targets": [
        49291
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49185,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49189,
      "address_region": "program_or_external",
      "bytes": "27EB",
      "text": "BEQ loc_C012",
      "mnemonic": "BEQ",
      "operands": "loc_C012",
      "kind": "branch",
      "targets": [
        49170
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49185,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49191,
      "address_region": "program_or_external",
      "bytes": "AD80",
      "text": "MOV:G.W R5, R0",
      "mnemonic": "MOV:G.W",
      "operands": "R5, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49191,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49193,
      "address_region": "program_or_external",
      "bytes": "A010",
      "text": "SWAP.B R0",
      "mnemonic": "SWAP.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49191,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 49195,
      "address_region": "program_or_external",
      "bytes": "0E5E",
      "text": "BSR loc_C08B",
      "mnemonic": "BSR",
      "operands": "loc_C08B",
      "kind": "call",
      "targets": [
        49291
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49191,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49197,
      "address_region": "program_or_external",
      "bytes": "27E3",
      "text": "BEQ loc_C012",
      "mnemonic": "BEQ",
      "operands": "loc_C012",
      "kind": "branch",
      "targets": [
        49170
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49191,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49199,
      "address_region": "program_or_external",
      "bytes": "A580",
      "text": "MOV:G.B R5, R0",
      "mnemonic": "MOV:G.B",
      "operands": "R5, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49199,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49201,
      "address_region": "program_or_external",
      "bytes": "0E58",
      "text": "BSR loc_C08B",
      "mnemonic": "BSR",
      "operands": "loc_C08B",
      "kind": "call",
      "targets": [
        49291
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49199,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49203,
      "address_region": "program_or_external",
      "bytes": "27DD",
      "text": "BEQ loc_C012",
      "mnemonic": "BEQ",
      "operands": "loc_C012",
      "kind": "branch",
      "targets": [
        49170
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49199,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49205,
      "address_region": "program_or_external",
      "bytes": "1E010A",
      "text": "BSR loc_C142",
      "mnemonic": "BSR",
      "operands": "loc_C142",
      "kind": "call",
      "targets": [
        49474
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49205,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49208,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49208,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49209,
      "address_region": "program_or_external",
      "bytes": "0E2F",
      "text": "BSR loc_C06A",
      "mnemonic": "BSR",
      "operands": "loc_C06A",
      "kind": "call",
      "targets": [
        49258
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49209,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49211,
      "address_region": "program_or_external",
      "bytes": "15F84016",
      "text": "TST.B @H'F840",
      "mnemonic": "TST.B",
      "operands": "@H'F840",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 63552,
          "name": null,
          "symbol": "ram_F840",
          "region": "on_chip_ram",
          "kind": "ram"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49211,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49215,
      "address_region": "program_or_external",
      "bytes": "2728",
      "text": "BEQ loc_C069",
      "mnemonic": "BEQ",
      "operands": "loc_C069",
      "kind": "branch",
      "targets": [
        49257
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49211,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49217,
      "address_region": "program_or_external",
      "bytes": "1E00DD",
      "text": "BSR loc_C121",
      "mnemonic": "BSR",
      "operands": "loc_C121",
      "kind": "call",
      "targets": [
        49441
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49217,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49220,
      "address_region": "program_or_external",
      "bytes": "A380",
      "text": "MOV:G.B R3, R0",
      "mnemonic": "MOV:G.B",
      "operands": "R3, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49217,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49222,
      "address_region": "program_or_external",
      "bytes": "0E43",
      "text": "BSR loc_C08B",
      "mnemonic": "BSR",
      "operands": "loc_C08B",
      "kind": "call",
      "targets": [
        49291
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49217,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49224,
      "address_region": "program_or_external",
      "bytes": "27F1",
      "text": "BEQ loc_C03B",
      "mnemonic": "BEQ",
      "operands": "loc_C03B",
      "kind": "branch",
      "targets": [
        49211
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49217,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49226,
      "address_region": "program_or_external",
      "bytes": "A480",
      "text": "MOV:G.B R4, R0",
      "mnemonic": "MOV:G.B",
      "operands": "R4, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49226,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49228,
      "address_region": "program_or_external",
      "bytes": "0E3D",
      "text": "BSR loc_C08B",
      "mnemonic": "BSR",
      "operands": "loc_C08B",
      "kind": "call",
      "targets": [
        49291
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49226,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49230,
      "address_region": "program_or_external",
      "bytes": "27EB",
      "text": "BEQ loc_C03B",
      "mnemonic": "BEQ",
      "operands": "loc_C03B",
      "kind": "branch",
      "targets": [
        49211
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49226,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49232,
      "address_region": "program_or_external",
      "bytes": "1E00CE",
      "text": "BSR loc_C121",
      "mnemonic": "BSR",
      "operands": "loc_C121",
      "kind": "call",
      "targets": [
        49441
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49232,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49235,
      "address_region": "program_or_external",
      "bytes": "A380",
      "text": "MOV:G.B R3, R0",
      "mnemonic": "MOV:G.B",
      "operands": "R3, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49232,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R0 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49237,
      "address_region": "program_or_external",
      "bytes": "A0C0",
      "text": "BSET.B #0, R0",
      "mnemonic": "BSET.B",
      "operands": "#0, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49232,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 49239,
      "address_region": "program_or_external",
      "bytes": "0E32",
      "text": "BSR loc_C08B",
      "mnemonic": "BSR",
      "operands": "loc_C08B",
      "kind": "call",
      "targets": [
        49291
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49232,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "unsupported:BSET.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49241,
      "address_region": "program_or_external",
      "bytes": "27E0",
      "text": "BEQ loc_C03B",
      "mnemonic": "BEQ",
      "operands": "loc_C03B",
      "kind": "branch",
      "targets": [
        49211
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49232,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49243,
      "address_region": "program_or_external",
      "bytes": "1E007D",
      "text": "BSR loc_C0DB",
      "mnemonic": "BSR",
      "operands": "loc_C0DB",
      "kind": "call",
      "targets": [
        49371
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49243,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R2",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R6",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "register",
            "name": "R7",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "BR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "EP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "DP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "TP",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "SR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49246,
      "address_region": "program_or_external",
      "bytes": "A510",
      "text": "SWAP.B R5",
      "mnemonic": "SWAP.B",
      "operands": "R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49243,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "call"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R5"
        ]
      }
    },
    {
      "address": 49248,
      "address_region": "program_or_external",
      "bytes": "1E00A9",
      "text": "BSR loc_C10C",
      "mnemonic": "BSR",
      "operands": "loc_C10C",
      "kind": "call",
      "targets": [
        49420
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49243,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "flags"
            },
            "after": {
              "known": false,
              "reason": "call"
            }
          }
        ],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49251,
      "address_region": "program_or_external",
      "bytes": "1E0075",
      "text": "BSR loc_C0DB",
      "mnemonic": "BSR",
      "operands": "loc_C0DB",
      "kind": "call",
      "targets": [
        49371
      ],
      "cycles": {
        "cycles": 14,
        "base_cycles": 9,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49243,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49254,
      "address_region": "program_or_external",
      "bytes": "1E00D9",
      "text": "BSR loc_C142",
      "mnemonic": "BSR",
      "operands": "loc_C142",
      "kind": "call",
      "targets": [
        49474
      ],
      "cycles": {
        "cycles": 13,
        "base_cycles": 9,
        "stack_adjustment": 4,
        "note": "PC word push to stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49243,
        "changes": [],
        "notes": [
          "call clobbers tracked register state"
        ]
      }
    },
    {
      "address": 49257,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49257,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49258,
      "address_region": "program_or_external",
      "bytes": "0C0FFF54",
      "text": "AND.W #H'0FFF, R4",
      "mnemonic": "AND.W",
      "operands": "#H'0FFF, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 4,
        "base_cycles": 4,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49258,
        "changes": [
          {
            "kind": "register",
            "name": "R4",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.W"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R4"
        ]
      }
    },
    {
      "address": 49262,
      "address_region": "program_or_external",
      "bytes": "4C0800",
      "text": "CMP:I #H'0800, R4",
      "mnemonic": "CMP:I",
      "operands": "#H'0800, R4",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49258,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49265,
      "address_region": "program_or_external",
      "bytes": "240B",
      "text": "BCC loc_C07E",
      "mnemonic": "BCC",
      "operands": "loc_C07E",
      "kind": "branch",
      "targets": [
        49278
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49258,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49267,
      "address_region": "program_or_external",
      "bytes": "AC83",
      "text": "MOV:G.W R4, R3",
      "mnemonic": "MOV:G.W",
      "operands": "R4, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49267,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R3 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49269,
      "address_region": "program_or_external",
      "bytes": "A310",
      "text": "SWAP.B R3",
      "mnemonic": "SWAP.B",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49267,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 49271,
      "address_region": "program_or_external",
      "bytes": "A31A",
      "text": "SHLL.B R3",
      "mnemonic": "SHLL.B",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49267,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 49273,
      "address_region": "program_or_external",
      "bytes": "04A043",
      "text": "OR.B #H'A0, R3",
      "mnemonic": "OR.B",
      "operands": "#H'A0, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49267,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 49276,
      "address_region": "program_or_external",
      "bytes": "200C",
      "text": "BRA loc_C08A",
      "mnemonic": "BRA",
      "operands": "loc_C08A",
      "kind": "jump",
      "targets": [
        49290
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49267,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49278,
      "address_region": "program_or_external",
      "bytes": "AC83",
      "text": "MOV:G.W R4, R3",
      "mnemonic": "MOV:G.W",
      "operands": "R4, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49278,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unknown_operand"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R3 unknown after MOV source"
        ]
      }
    },
    {
      "address": 49280,
      "address_region": "program_or_external",
      "bytes": "A310",
      "text": "SWAP.B R3",
      "mnemonic": "SWAP.B",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49278,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unknown_operand"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 49282,
      "address_region": "program_or_external",
      "bytes": "A31A",
      "text": "SHLL.B R3",
      "mnemonic": "SHLL.B",
      "operands": "R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49278,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:SWAP.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 49284,
      "address_region": "program_or_external",
      "bytes": "040E53",
      "text": "AND.B #H'0E, R3",
      "mnemonic": "AND.B",
      "operands": "#H'0E, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49278,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:AND.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 49287,
      "address_region": "program_or_external",
      "bytes": "04E043",
      "text": "OR.B #H'E0, R3",
      "mnemonic": "OR.B",
      "operands": "#H'E0, R3",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "base_cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49278,
        "changes": [
          {
            "kind": "register",
            "name": "R3",
            "before": {
              "known": false,
              "reason": "unsupported:AND.B"
            },
            "after": {
              "known": false,
              "reason": "unsupported:OR.B"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R3"
        ]
      }
    },
    {
      "address": 49290,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49290,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49291,
      "address_region": "program_or_external",
      "bytes": "590007",
      "text": "MOV:I.W #H'0007, R1",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0007, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49291,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 7,
              "hex": "0x0007",
              "width": 16,
              "source": "MOV:I.W #H'0007, R1"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "R1 = 0x0007"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 7,
              "hex": "0x0007",
              "width": 16,
              "source": "MOV:I.W #H'0007, R1"
            }
          }
        }
      }
    },
    {
      "address": 49294,
      "address_region": "program_or_external",
      "bytes": "A01A",
      "text": "SHLL.B R0",
      "mnemonic": "SHLL.B",
      "operands": "R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49294,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:SHLL.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R0"
        ]
      }
    },
    {
      "address": 49296,
      "address_region": "program_or_external",
      "bytes": "2406",
      "text": "BCC loc_C098",
      "mnemonic": "BCC",
      "operands": "loc_C098",
      "kind": "branch",
      "targets": [
        49304
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49294,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49298,
      "address_region": "program_or_external",
      "bytes": "15FEFFC7",
      "text": "BSET.B #7, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#7, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 7 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49298,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49302,
      "address_region": "program_or_external",
      "bytes": "2004",
      "text": "BRA loc_C09C",
      "mnemonic": "BRA",
      "operands": "loc_C09C",
      "kind": "jump",
      "targets": [
        49308
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "cycles": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49298,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49304,
      "address_region": "program_or_external",
      "bytes": "15FEFFD7",
      "text": "BCLR.B #7, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 7 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49304,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49308,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49308,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49312,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49308,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49316,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49308,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49320,
      "address_region": "program_or_external",
      "bytes": "15FEFFD1",
      "text": "BCLR.B #1, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49308,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49324,
      "address_region": "program_or_external",
      "bytes": "01B9DF",
      "text": "SCB/F R1, loc_C08E",
      "mnemonic": "SCB/F",
      "operands": "R1, loc_C08E",
      "kind": "branch",
      "targets": [
        49294
      ],
      "cycles": {
        "false": 3,
        "count_minus_1": 4,
        "taken": 8,
        "base_taken": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49308,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49327,
      "address_region": "program_or_external",
      "bytes": "15FEFE0613",
      "text": "MOV:G.B #H'13, @P9DDR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'13, @P9DDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65278,
          "name": "P9DDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P9DDR = H'13",
      "valid": true,
      "dataflow": {
        "block": 49327,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49332,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49327,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49336,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49327,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49340,
      "address_region": "program_or_external",
      "bytes": "15FEFFF7",
      "text": "BTST.B #7, @P9DR",
      "mnemonic": "BTST.B",
      "operands": "#7, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 7,
        "base_cycles": 6,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49327,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49344,
      "address_region": "program_or_external",
      "bytes": "270D",
      "text": "BEQ loc_C0CF",
      "mnemonic": "BEQ",
      "operands": "loc_C0CF",
      "kind": "branch",
      "targets": [
        49359
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 7,
        "base_taken": 7,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49327,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49346,
      "address_region": "program_or_external",
      "bytes": "15FEFFD1",
      "text": "BCLR.B #1, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49346,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49350,
      "address_region": "program_or_external",
      "bytes": "15FEFE0693",
      "text": "MOV:G.B #H'93, @P9DDR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'93, @P9DDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65278,
          "name": "P9DDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P9DDR = H'93",
      "valid": true,
      "dataflow": {
        "block": 49346,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49355,
      "address_region": "program_or_external",
      "bytes": "5000",
      "text": "MOV:E.B #H'00, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'00, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49346,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 0,
              "hex": "0x00",
              "width": 8,
              "source": "MOV:E.B #H'00, R0"
            }
          }
        ],
        "notes": [
          "R0 = 0x00"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 0,
              "hex": "0x00",
              "width": 8,
              "source": "MOV:E.B #H'00, R0"
            }
          }
        }
      }
    },
    {
      "address": 49357,
      "address_region": "program_or_external",
      "bytes": "200B",
      "text": "BRA loc_C0DA",
      "mnemonic": "BRA",
      "operands": "loc_C0DA",
      "kind": "jump",
      "targets": [
        49370
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49346,
        "changes": [],
        "notes": [],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 0,
              "hex": "0x00",
              "width": 8,
              "source": "MOV:E.B #H'00, R0"
            }
          }
        }
      }
    },
    {
      "address": 49359,
      "address_region": "program_or_external",
      "bytes": "15FEFFD1",
      "text": "BCLR.B #1, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49359,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49363,
      "address_region": "program_or_external",
      "bytes": "15FEFE0693",
      "text": "MOV:G.B #H'93, @P9DDR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'93, @P9DDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65278,
          "name": "P9DDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P9DDR = H'93",
      "valid": true,
      "dataflow": {
        "block": 49359,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49368,
      "address_region": "program_or_external",
      "bytes": "5001",
      "text": "MOV:E.B #H'01, R0",
      "mnemonic": "MOV:E.B",
      "operands": "#H'01, R0",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49359,
        "changes": [
          {
            "kind": "register",
            "name": "R0",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 1,
              "hex": "0x01",
              "width": 8,
              "source": "MOV:E.B #H'01, R0"
            }
          }
        ],
        "notes": [
          "R0 = 0x01"
        ],
        "known_after": {
          "registers": {
            "R0": {
              "known": true,
              "value": 1,
              "hex": "0x01",
              "width": 8,
              "source": "MOV:E.B #H'01, R0"
            }
          }
        }
      }
    },
    {
      "address": 49370,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49370,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49371,
      "address_region": "program_or_external",
      "bytes": "15FEFE0613",
      "text": "MOV:G.B #H'13, @P9DDR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'13, @P9DDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65278,
          "name": "P9DDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P9DDR = H'13",
      "valid": true,
      "dataflow": {
        "block": 49371,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49376,
      "address_region": "program_or_external",
      "bytes": "590007",
      "text": "MOV:I.W #H'0007, R1",
      "mnemonic": "MOV:I.W",
      "operands": "#H'0007, R1",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 3,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49371,
        "changes": [
          {
            "kind": "register",
            "name": "R1",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": true,
              "value": 7,
              "hex": "0x0007",
              "width": 16,
              "source": "MOV:I.W #H'0007, R1"
            }
          }
        ],
        "notes": [
          "R1 = 0x0007"
        ],
        "known_after": {
          "registers": {
            "R1": {
              "known": true,
              "value": 7,
              "hex": "0x0007",
              "width": 16,
              "source": "MOV:I.W #H'0007, R1"
            }
          }
        }
      }
    },
    {
      "address": 49379,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49379,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49383,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49379,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49387,
      "address_region": "program_or_external",
      "bytes": "15FEFFF7",
      "text": "BTST.B #7, @P9DR",
      "mnemonic": "BTST.B",
      "operands": "#7, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 6,
        "base_cycles": 6,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49379,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49391,
      "address_region": "program_or_external",
      "bytes": "2704",
      "text": "BEQ loc_C0F5",
      "mnemonic": "BEQ",
      "operands": "loc_C0F5",
      "kind": "branch",
      "targets": [
        49397
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49379,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49393,
      "address_region": "program_or_external",
      "bytes": "A549",
      "text": "BSET.B R1, R5",
      "mnemonic": "BSET.B",
      "operands": "R1, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49393,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BSET.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R5"
        ]
      }
    },
    {
      "address": 49395,
      "address_region": "program_or_external",
      "bytes": "2002",
      "text": "BRA loc_C0F7",
      "mnemonic": "BRA",
      "operands": "loc_C0F7",
      "kind": "jump",
      "targets": [
        49399
      ],
      "cycles": {
        "not_taken": 3,
        "taken": 8,
        "base_taken": 7,
        "alignment_adjustment_taken": 1,
        "cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49393,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49397,
      "address_region": "program_or_external",
      "bytes": "A559",
      "text": "BCLR.B R1, R5",
      "mnemonic": "BCLR.B",
      "operands": "R1, R5",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 2,
        "base_cycles": 2,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49397,
        "changes": [
          {
            "kind": "register",
            "name": "R5",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "unsupported:BCLR.B"
            }
          },
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": [
          "unsupported operation invalidated R5"
        ]
      }
    },
    {
      "address": 49399,
      "address_region": "program_or_external",
      "bytes": "15FEFFD1",
      "text": "BCLR.B #1, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49399,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49403,
      "address_region": "program_or_external",
      "bytes": "15FEFFD1",
      "text": "BCLR.B #1, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49399,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49407,
      "address_region": "program_or_external",
      "bytes": "15FEFFD1",
      "text": "BCLR.B #1, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49399,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49411,
      "address_region": "program_or_external",
      "bytes": "01B9DD",
      "text": "SCB/F R1, loc_C0E3",
      "mnemonic": "SCB/F",
      "operands": "R1, loc_C0E3",
      "kind": "branch",
      "targets": [
        49379
      ],
      "cycles": {
        "false": 3,
        "count_minus_1": 4,
        "taken": 9,
        "base_taken": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49399,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49414,
      "address_region": "program_or_external",
      "bytes": "15FEFE0693",
      "text": "MOV:G.B #H'93, @P9DDR",
      "mnemonic": "MOV:G.B",
      "operands": "#H'93, @P9DDR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65278,
          "name": "P9DDR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "P9DDR = H'93",
      "valid": true,
      "dataflow": {
        "block": 49414,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49419,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49414,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49420,
      "address_region": "program_or_external",
      "bytes": "15FEFFD7",
      "text": "BCLR.B #7, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 7 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49420,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49424,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49420,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49428,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49420,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49432,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49420,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49436,
      "address_region": "program_or_external",
      "bytes": "15FEFFD1",
      "text": "BCLR.B #1, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49420,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49440,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49420,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49441,
      "address_region": "program_or_external",
      "bytes": "15FEFFC7",
      "text": "BSET.B #7, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#7, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 7 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49441,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49445,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49441,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49449,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49441,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49453,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49441,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49457,
      "address_region": "program_or_external",
      "bytes": "15FEFFD7",
      "text": "BCLR.B #7, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 7 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49441,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49461,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49441,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49465,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49441,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49469,
      "address_region": "program_or_external",
      "bytes": "15FEFFD1",
      "text": "BCLR.B #1, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 8,
        "base_cycles": 8,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49441,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49473,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 13,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49441,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49474,
      "address_region": "program_or_external",
      "bytes": "15FEFFD7",
      "text": "BCLR.B #7, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#7, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 7 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49474,
        "changes": [
          {
            "kind": "control",
            "name": "CCR",
            "before": {
              "known": false,
              "reason": "block_entry"
            },
            "after": {
              "known": false,
              "reason": "flags"
            }
          }
        ],
        "notes": []
      }
    },
    {
      "address": 49478,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49474,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49482,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49474,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49486,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49474,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49490,
      "address_region": "program_or_external",
      "bytes": "15FEFFC7",
      "text": "BSET.B #7, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#7, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 7 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49474,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49494,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49474,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49498,
      "address_region": "program_or_external",
      "bytes": "15FEFFC1",
      "text": "BSET.B #1, @P9DR",
      "mnemonic": "BSET.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "set bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49474,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49502,
      "address_region": "program_or_external",
      "bytes": "15FEFFD1",
      "text": "BCLR.B #1, @P9DR",
      "mnemonic": "BCLR.B",
      "operands": "#1, @P9DR",
      "kind": "normal",
      "targets": [],
      "cycles": {
        "cycles": 9,
        "base_cycles": 8,
        "alignment_adjustment": 1,
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [
        {
          "address": 65279,
          "name": "P9DR",
          "symbol": null,
          "region": "register_field",
          "kind": "registers"
        }
      ],
      "comment": "clear bit 1 of P9DR",
      "valid": true,
      "dataflow": {
        "block": 49474,
        "changes": [],
        "notes": []
      }
    },
    {
      "address": 49506,
      "address_region": "program_or_external",
      "bytes": "19",
      "text": "RTS",
      "mnemonic": "RTS",
      "operands": "",
      "kind": "return",
      "targets": [],
      "cycles": {
        "cycles": 12,
        "base_cycles": 8,
        "stack_adjustment": 4,
        "note": "PC word pop from stack",
        "source": "manual Appendix A.4, tables A-7/A-8",
        "assumption": "on-chip instruction fetch/operand access, no external wait states"
      },
      "references": [],
      "comment": "",
      "valid": true,
      "dataflow": {
        "block": 49474,
        "changes": [],
        "notes": []
      }
    }
  ],
  "decompiler_consistency": {
    "kind": "decompiler_pseudocode_consistency",
    "summary": "3 byte-immediate-to-word destination case(s) require explicit zero-extension in pseudocode.",
    "checks": [
      {
        "kind": "byte_immediate_to_word_destination",
        "status": "requires_zero_extend8_to16_pseudocode",
        "address": 4163,
        "address_hex": "H'1043",
        "instruction": "MOV:G.W #H'00, @FRT1_FRC_H",
        "expected_pseudocode_hint": "zero_extend8_to16",
        "zero_extended_value_hex": "0x0000",
        "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte."
      },
      {
        "kind": "byte_immediate_to_word_destination",
        "status": "requires_zero_extend8_to16_pseudocode",
        "address": 4184,
        "address_hex": "H'1058",
        "instruction": "MOV:G.W #H'00, @FRT2_FRC_H",
        "expected_pseudocode_hint": "zero_extend8_to16",
        "zero_extended_value_hex": "0x0000",
        "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte."
      },
      {
        "kind": "byte_immediate_to_word_destination",
        "status": "requires_zero_extend8_to16_pseudocode",
        "address": 16487,
        "address_hex": "H'4067",
        "instruction": "MOV:G.W #H'00, @(-H'0790,R2)",
        "expected_pseudocode_hint": "zero_extend8_to16",
        "zero_extended_value_hex": "0x0000",
        "summary": "Word-sized MOV with an 8-bit immediate writes a zero-extended word. Pseudocode should not model this as a one-byte write or preserve the old low byte."
      }
    ]
  },
  "serial_semantics": {
    "kind": "serial_semantics",
    "protocol_semantics": [
      {
        "kind": "serial_semantics",
        "scope": "evidence_supported_sci1_6_byte_frame",
        "confidence": "medium-high",
        "confidence_score": 0.9,
        "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation.",
        "frame_candidate": {
          "channel": "SCI1",
          "rx_frame_start": 63584,
          "rx_frame_start_hex": "H'F860",
          "rx_frame_end": 63589,
          "rx_frame_end_hex": "H'F865",
          "tx_staging_start": 63568,
          "tx_staging_start_hex": "H'F850",
          "tx_staging_end": 63572,
          "tx_staging_end_hex": "H'F854",
          "tx_frame_start": 63576,
          "tx_frame_start_hex": "H'F858",
          "tx_frame_end": 63581,
          "tx_frame_end_hex": "H'F85D",
          "frame_length": 6,
          "tx_staging_length": 5,
          "checksum_seed": 90,
          "checksum_seed_hex": "H'005A",
          "serial_reconstruction_supported": true,
          "rx_reconstruction_candidate_id": "sci1_rx_frame_f868_len6_candidate",
          "tx_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate"
        },
        "byte_layout": [
          {
            "offset": 0,
            "rx_address": 63584,
            "tx_staging_address": 63568,
            "name_candidate": "op_flags",
            "semantic": "low three bits select a command; upper bits are preserved or gated in some paths",
            "confidence": "medium-high"
          },
          {
            "offset": 1,
            "rx_address": 63585,
            "tx_staging_address": 63569,
            "name_candidate": "addr_page_flags",
            "semantic": "candidate high/page byte for logical point/index; bit 7 is tested as a control flag",
            "confidence": "medium"
          },
          {
            "offset": 2,
            "rx_address": 63586,
            "tx_staging_address": 63570,
            "name_candidate": "addr_offset",
            "semantic": "candidate low/offset byte for logical point/index",
            "confidence": "medium"
          },
          {
            "offset": 3,
            "rx_address": 63587,
            "tx_staging_address": 63571,
            "name_candidate": "value_hi",
            "semantic": "candidate high byte of a word value",
            "confidence": "medium"
          },
          {
            "offset": 4,
            "rx_address": 63588,
            "tx_staging_address": 63572,
            "name_candidate": "value_lo",
            "semantic": "candidate low byte of a word value",
            "confidence": "medium"
          },
          {
            "offset": 5,
            "rx_address": 63589,
            "tx_staging_address": null,
            "name_candidate": "checksum",
            "semantic": "0x5A-seeded XOR of bytes 0..4",
            "confidence": "high"
          }
        ],
        "fields": [
          {
            "id": "rx_0",
            "kind": "rx_frame_field_candidate",
            "offset": 0,
            "address": 63584,
            "address_hex": "H'F860",
            "role_candidate": "command_selector_candidate",
            "evidence_addresses": [
              48088,
              48136,
              48055,
              48160,
              48162,
              48164,
              48197,
              48166,
              48199,
              48169,
              48202,
              48171,
              48140,
              48204,
              48174,
              48207,
              48176,
              48209,
              48212,
              48214
            ],
            "evidence_addresses_hex": [
              "H'BBD8",
              "H'BC08",
              "H'BBB7",
              "H'BC20",
              "H'BC22",
              "H'BC24",
              "H'BC45",
              "H'BC26",
              "H'BC47",
              "H'BC29",
              "H'BC4A",
              "H'BC2B",
              "H'BC0C",
              "H'BC4C",
              "H'BC2E",
              "H'BC4F",
              "H'BC30",
              "H'BC51",
              "H'BC54",
              "H'BC56"
            ],
            "read_count": 2,
            "write_count": 2,
            "confidence": "medium",
            "caveat": "RX[0] is masked with 0x07 before command comparisons."
          },
          {
            "id": "rx_1",
            "kind": "rx_frame_field_candidate",
            "offset": 1,
            "address": 63585,
            "address_hex": "H'F861",
            "role_candidate": "payload_byte_candidate",
            "evidence_addresses": [
              48092,
              48119,
              48153,
              48190,
              48309,
              48348,
              48722
            ],
            "evidence_addresses_hex": [
              "H'BBDC",
              "H'BBF7",
              "H'BC19",
              "H'BC3E",
              "H'BCB5",
              "H'BCDC",
              "H'BE52"
            ],
            "read_count": 7,
            "write_count": 1,
            "confidence": "medium",
            "caveat": "Role is inferred from reads in command processing."
          },
          {
            "id": "rx_2",
            "kind": "rx_frame_field_candidate",
            "offset": 2,
            "address": 63586,
            "address_hex": "H'F862",
            "role_candidate": "payload_byte_candidate",
            "evidence_addresses": [
              48096,
              48125,
              48317,
              48356,
              48730,
              48063
            ],
            "evidence_addresses_hex": [
              "H'BBE0",
              "H'BBFD",
              "H'BCBD",
              "H'BCE4",
              "H'BE5A",
              "H'BBBF"
            ],
            "read_count": 5,
            "write_count": 2,
            "confidence": "medium",
            "caveat": "Role is inferred from reads in command processing."
          },
          {
            "id": "rx_3",
            "kind": "rx_frame_field_candidate",
            "offset": 3,
            "address": 63587,
            "address_hex": "H'F863",
            "role_candidate": "payload_byte_candidate",
            "evidence_addresses": [
              48100,
              48237,
              48267,
              48402,
              48427,
              48603
            ],
            "evidence_addresses_hex": [
              "H'BBE4",
              "H'BC6D",
              "H'BC8B",
              "H'BD12",
              "H'BD2B",
              "H'BDDB"
            ],
            "read_count": 6,
            "write_count": 1,
            "confidence": "medium",
            "caveat": "Role is inferred from reads in command processing."
          },
          {
            "id": "rx_4",
            "kind": "rx_frame_field_candidate",
            "offset": 4,
            "address": 63588,
            "address_hex": "H'F864",
            "role_candidate": "payload_byte_candidate",
            "evidence_addresses": [
              48104,
              48273,
              48325,
              48433,
              48609,
              48738,
              48071,
              48253
            ],
            "evidence_addresses_hex": [
              "H'BBE8",
              "H'BC91",
              "H'BCC5",
              "H'BD31",
              "H'BDE1",
              "H'BE62",
              "H'BBC7",
              "H'BC7D"
            ],
            "read_count": 6,
            "write_count": 3,
            "confidence": "medium",
            "caveat": "Role is inferred from reads in command processing."
          },
          {
            "id": "rx_5",
            "kind": "rx_frame_field_candidate",
            "offset": 5,
            "address": 63589,
            "address_hex": "H'F865",
            "role_candidate": "checksum_byte_candidate",
            "evidence_addresses": [
              48108
            ],
            "evidence_addresses_hex": [
              "H'BBEC"
            ],
            "read_count": 1,
            "write_count": 0,
            "confidence": "medium",
            "caveat": "RX[5] is compared with a checksum over RX[0..4]."
          },
          {
            "id": "tx_staging_0",
            "kind": "tx_staging_field_candidate",
            "offset": 0,
            "address": 63568,
            "address_hex": "H'F850",
            "role_candidate": "response_staging_byte_candidate",
            "evidence_addresses": [
              47900,
              48304,
              48343,
              48649,
              48717
            ],
            "evidence_addresses_hex": [
              "H'BB1C",
              "H'BCB0",
              "H'BCD7",
              "H'BE09",
              "H'BE4D"
            ],
            "write_count": 5,
            "confidence": "medium",
            "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
          },
          {
            "id": "tx_staging_1",
            "kind": "tx_staging_field_candidate",
            "offset": 1,
            "address": 63569,
            "address_hex": "H'F851",
            "role_candidate": "response_staging_byte_candidate",
            "evidence_addresses": [
              47915,
              48313,
              48352,
              48360,
              48649,
              48726
            ],
            "evidence_addresses_hex": [
              "H'BB2B",
              "H'BCB9",
              "H'BCE0",
              "H'BCE8",
              "H'BE09",
              "H'BE56"
            ],
            "write_count": 6,
            "confidence": "medium",
            "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
          },
          {
            "id": "tx_staging_2",
            "kind": "tx_staging_field_candidate",
            "offset": 2,
            "address": 63570,
            "address_hex": "H'F852",
            "role_candidate": "response_staging_byte_candidate",
            "evidence_addresses": [
              47904,
              48321,
              48657,
              48734
            ],
            "evidence_addresses_hex": [
              "H'BB20",
              "H'BCC1",
              "H'BE11",
              "H'BE5E"
            ],
            "write_count": 4,
            "confidence": "medium",
            "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
          },
          {
            "id": "tx_staging_3",
            "kind": "tx_staging_field_candidate",
            "offset": 3,
            "address": 63571,
            "address_hex": "H'F853",
            "role_candidate": "response_staging_byte_candidate",
            "evidence_addresses": [
              47935,
              48321,
              48374,
              48657,
              48734
            ],
            "evidence_addresses_hex": [
              "H'BB3F",
              "H'BCC1",
              "H'BCF6",
              "H'BE11",
              "H'BE5E"
            ],
            "write_count": 5,
            "confidence": "medium",
            "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
          },
          {
            "id": "tx_staging_4",
            "kind": "tx_staging_field_candidate",
            "offset": 4,
            "address": 63572,
            "address_hex": "H'F854",
            "role_candidate": "response_staging_byte_candidate",
            "evidence_addresses": [
              47929,
              48329,
              48368,
              48665,
              48742
            ],
            "evidence_addresses_hex": [
              "H'BB39",
              "H'BCC9",
              "H'BCF0",
              "H'BE19",
              "H'BE66"
            ],
            "write_count": 5,
            "confidence": "medium",
            "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
          }
        ],
        "command_dispatch": {
          "kind": "command_dispatch_candidate",
          "selector": "rx0_low3_bits",
          "field": "command_low3",
          "rx_offset": 0,
          "rx_address": 63584,
          "rx_address_hex": "H'F860",
          "source_address": 63584,
          "source_address_hex": "H'F860",
          "source_field": "byte0",
          "mask": 7,
          "mask_hex": "H'0007",
          "selector_register": "R0",
          "read_address": 48136,
          "read_address_hex": "H'BC08",
          "mask_address": 48140,
          "mask_address_hex": "H'BC0C",
          "command_values": [
            0,
            1,
            2,
            4,
            5,
            6,
            7
          ],
          "command_values_hex": [
            "H'00",
            "H'01",
            "H'02",
            "H'04",
            "H'05",
            "H'06",
            "H'07"
          ],
          "comparisons": [
            {
              "command_value": 0,
              "command_value_hex": "H'00",
              "compare_address": 48160,
              "compare_address_hex": "H'BC20",
              "branch_address": 48162,
              "branch_address_hex": "H'BC22",
              "handler_start": 48233,
              "handler_start_hex": "H'BC69",
              "evidence_addresses": [
                48160,
                48162
              ],
              "evidence_addresses_hex": [
                "H'BC20",
                "H'BC22"
              ],
              "availability": "initial_idle_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 == 0"
              ],
              "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
              "handler_start_index": 2147
            },
            {
              "command_value": 1,
              "command_value_hex": "H'01",
              "compare_address": 48164,
              "compare_address_hex": "H'BC24",
              "branch_address": 48166,
              "branch_address_hex": "H'BC26",
              "handler_start": 48343,
              "handler_start_hex": "H'BCD7",
              "evidence_addresses": [
                48164,
                48166
              ],
              "evidence_addresses_hex": [
                "H'BC24",
                "H'BC26"
              ],
              "availability": "initial_idle_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 == 0",
                "F861.bit7 == 0"
              ],
              "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0",
              "handler_start_index": 2179
            },
            {
              "command_value": 2,
              "command_value_hex": "H'02",
              "compare_address": 48169,
              "compare_address_hex": "H'BC29",
              "branch_address": 48171,
              "branch_address_hex": "H'BC2B",
              "handler_start": 48388,
              "handler_start_hex": "H'BD04",
              "evidence_addresses": [
                48169,
                48171
              ],
              "evidence_addresses_hex": [
                "H'BC29",
                "H'BC2B"
              ],
              "availability": "initial_idle_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 == 0"
              ],
              "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
              "handler_start_index": 2191
            },
            {
              "command_value": 7,
              "command_value_hex": "H'07",
              "compare_address": 48174,
              "compare_address_hex": "H'BC2E",
              "branch_address": 48176,
              "branch_address_hex": "H'BC30",
              "handler_start": 48645,
              "handler_start_hex": "H'BE05",
              "evidence_addresses": [
                48174,
                48176
              ],
              "evidence_addresses_hex": [
                "H'BC2E",
                "H'BC30"
              ],
              "availability": "initial_idle_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 == 0"
              ],
              "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
              "handler_start_index": 2275
            },
            {
              "command_value": 4,
              "command_value_hex": "H'04",
              "compare_address": 48197,
              "compare_address_hex": "H'BC45",
              "branch_address": 48199,
              "branch_address_hex": "H'BC47",
              "handler_start": 48398,
              "handler_start_hex": "H'BD0E",
              "evidence_addresses": [
                48197,
                48199
              ],
              "evidence_addresses_hex": [
                "H'BC45",
                "H'BC47"
              ],
              "availability": "continuation_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 != 0"
              ],
              "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
              "handler_start_index": 2194
            },
            {
              "command_value": 5,
              "command_value_hex": "H'05",
              "compare_address": 48202,
              "compare_address_hex": "H'BC4A",
              "branch_address": 48204,
              "branch_address_hex": "H'BC4C",
              "handler_start": 48512,
              "handler_start_hex": "H'BD80",
              "evidence_addresses": [
                48202,
                48204
              ],
              "evidence_addresses_hex": [
                "H'BC4A",
                "H'BC4C"
              ],
              "availability": "continuation_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 != 0"
              ],
              "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
              "handler_start_index": 2231
            },
            {
              "command_value": 6,
              "command_value_hex": "H'06",
              "compare_address": 48207,
              "compare_address_hex": "H'BC4F",
              "branch_address": 48209,
              "branch_address_hex": "H'BC51",
              "handler_start": 48603,
              "handler_start_hex": "H'BDDB",
              "evidence_addresses": [
                48207,
                48209
              ],
              "evidence_addresses_hex": [
                "H'BC4F",
                "H'BC51"
              ],
              "availability": "continuation_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 != 0"
              ],
              "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
              "handler_start_index": 2263
            },
            {
              "command_value": 7,
              "command_value_hex": "H'07",
              "compare_address": 48212,
              "compare_address_hex": "H'BC54",
              "branch_address": 48214,
              "branch_address_hex": "H'BC56",
              "handler_start": 48645,
              "handler_start_hex": "H'BE05",
              "evidence_addresses": [
                48212,
                48214
              ],
              "evidence_addresses_hex": [
                "H'BC54",
                "H'BC56"
              ],
              "availability": "continuation_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 != 0"
              ],
              "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
              "handler_start_index": 2275
            }
          ],
          "state_split": {
            "kind": "serial_command_dispatch_state_split",
            "state_address": 64162,
            "state_address_hex": "H'FAA2",
            "test_address": 48143,
            "test_address_hex": "H'BC0F",
            "branch_address": 48147,
            "branch_address_hex": "H'BC13",
            "continuation_target": 48186,
            "continuation_target_hex": "H'BC3A",
            "initial_idle_commands": [
              0,
              1,
              2,
              7
            ],
            "initial_idle_commands_hex": [
              "H'00",
              "H'01",
              "H'02",
              "H'07"
            ],
            "continuation_commands": [
              4,
              5,
              6,
              7
            ],
            "continuation_commands_hex": [
              "H'04",
              "H'05",
              "H'06",
              "H'07"
            ],
            "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.",
            "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.",
            "evidence_addresses": [
              48143,
              48147
            ],
            "evidence_addresses_hex": [
              "H'BC0F",
              "H'BC13"
            ]
          },
          "dispatcher_split": {
            "kind": "serial_command_dispatch_state_split",
            "state_address": 64162,
            "state_address_hex": "H'FAA2",
            "test_address": 48143,
            "test_address_hex": "H'BC0F",
            "branch_address": 48147,
            "branch_address_hex": "H'BC13",
            "continuation_target": 48186,
            "continuation_target_hex": "H'BC3A",
            "initial_idle_commands": [
              0,
              1,
              2,
              7
            ],
            "initial_idle_commands_hex": [
              "H'00",
              "H'01",
              "H'02",
              "H'07"
            ],
            "continuation_commands": [
              4,
              5,
              6,
              7
            ],
            "continuation_commands_hex": [
              "H'04",
              "H'05",
              "H'06",
              "H'07"
            ],
            "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.",
            "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.",
            "evidence_addresses": [
              48143,
              48147
            ],
            "evidence_addresses_hex": [
              "H'BC0F",
              "H'BC13"
            ]
          },
          "cases": [
            {
              "value": 0,
              "value_hex": "H'00",
              "target": 48233,
              "target_hex": "H'BC69",
              "compare_address": 48160,
              "branch_address": 48162,
              "availability": "initial_idle_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 == 0"
              ]
            },
            {
              "value": 1,
              "value_hex": "H'01",
              "target": 48343,
              "target_hex": "H'BCD7",
              "compare_address": 48164,
              "branch_address": 48166,
              "availability": "initial_idle_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 == 0",
                "F861.bit7 == 0"
              ]
            },
            {
              "value": 2,
              "value_hex": "H'02",
              "target": 48388,
              "target_hex": "H'BD04",
              "compare_address": 48169,
              "branch_address": 48171,
              "availability": "initial_idle_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 == 0"
              ]
            },
            {
              "value": 7,
              "value_hex": "H'07",
              "target": 48645,
              "target_hex": "H'BE05",
              "compare_address": 48174,
              "branch_address": 48176,
              "availability": "initial_idle_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 == 0"
              ]
            },
            {
              "value": 4,
              "value_hex": "H'04",
              "target": 48398,
              "target_hex": "H'BD0E",
              "compare_address": 48197,
              "branch_address": 48199,
              "availability": "continuation_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 != 0"
              ]
            },
            {
              "value": 5,
              "value_hex": "H'05",
              "target": 48512,
              "target_hex": "H'BD80",
              "compare_address": 48202,
              "branch_address": 48204,
              "availability": "continuation_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 != 0"
              ]
            },
            {
              "value": 6,
              "value_hex": "H'06",
              "target": 48603,
              "target_hex": "H'BDDB",
              "compare_address": 48207,
              "branch_address": 48209,
              "availability": "continuation_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 != 0"
              ]
            },
            {
              "value": 7,
              "value_hex": "H'07",
              "target": 48645,
              "target_hex": "H'BE05",
              "compare_address": 48212,
              "branch_address": 48214,
              "availability": "continuation_dispatch",
              "availability_conditions": [
                "valid checksum/no RX physical error",
                "FAA2 != 0"
              ]
            }
          ],
          "evidence_addresses": [
            48136,
            48140,
            48160,
            48162,
            48164,
            48166,
            48169,
            48171,
            48174,
            48176,
            48197,
            48199,
            48202,
            48204,
            48207,
            48209,
            48212,
            48214
          ],
          "confidence": "medium",
          "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.",
          "evidence_addresses_hex": [
            "H'BC08",
            "H'BC0C",
            "H'BC20",
            "H'BC22",
            "H'BC24",
            "H'BC26",
            "H'BC29",
            "H'BC2B",
            "H'BC2E",
            "H'BC30",
            "H'BC45",
            "H'BC47",
            "H'BC4A",
            "H'BC4C",
            "H'BC4F",
            "H'BC51",
            "H'BC54",
            "H'BC56"
          ]
        },
        "commands": [
          {
            "kind": "command_candidate",
            "command_value": 0,
            "command_value_hex": "H'00",
            "name_candidate": "set_value_acked",
            "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response",
            "handler_alternatives": [
              {
                "handler_start": 48233,
                "handler_start_hex": "H'BC69",
                "handler_end": 48340,
                "handler_end_hex": "H'BCD4",
                "dispatch_compare_address": 48160,
                "dispatch_compare_address_hex": "H'BC20",
                "dispatch_branch_address": 48162,
                "dispatch_branch_address_hex": "H'BC22",
                "availability": "initial_idle_dispatch",
                "availability_conditions": [
                  "valid checksum/no RX physical error",
                  "FAA2 == 0"
                ]
              }
            ],
            "evidence_addresses": [
              48136,
              48140,
              48160,
              48162,
              48304,
              48313,
              48321,
              48329,
              48309,
              48317,
              48325,
              48333
            ],
            "response_candidates": [
              "response_at_BCCD"
            ],
            "rx_reads": [
              {
                "instruction_address": 48237,
                "instruction_address_hex": "H'BC6D",
                "rx_offset": 3,
                "rx_address": 63587,
                "rx_address_hex": "H'F863",
                "instruction": "MOV:G.B @H'F863, R0"
              },
              {
                "instruction_address": 48267,
                "instruction_address_hex": "H'BC8B",
                "rx_offset": 3,
                "rx_address": 63587,
                "rx_address_hex": "H'F863",
                "instruction": "MOV:G.B @H'F863, R0"
              },
              {
                "instruction_address": 48273,
                "instruction_address_hex": "H'BC91",
                "rx_offset": 4,
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "instruction": "MOV:G.B @H'F864, R0"
              },
              {
                "instruction_address": 48309,
                "instruction_address_hex": "H'BCB5",
                "rx_offset": 1,
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "instruction": "MOV:G.B @H'F861, R0"
              },
              {
                "instruction_address": 48317,
                "instruction_address_hex": "H'BCBD",
                "rx_offset": 2,
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "instruction": "MOV:G.W @H'F862, R0"
              },
              {
                "instruction_address": 48325,
                "instruction_address_hex": "H'BCC5",
                "rx_offset": 4,
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
            "handler_start": 48233,
            "handler_start_hex": "H'BC69",
            "handler_end": 48340,
            "handler_end_hex": "H'BCD4",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
            "semantic_notes": [],
            "effects": [
              {
                "kind": "table_write_candidate",
                "target_candidate": "primary_value_table_candidate",
                "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero",
                "table_base": 57344,
                "table_base_hex": "H'E000",
                "evidence_addresses": [
                  48245,
                  48277
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BC75",
                  "H'BC95"
                ]
              },
              {
                "kind": "table_write_candidate",
                "target_candidate": "current_value_table_candidate",
                "source_candidate": "same candidate value written to the primary table",
                "table_base": 59392,
                "table_base_hex": "H'E800",
                "evidence_addresses": [
                  48249,
                  48281
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BC79",
                  "H'BC99"
                ]
              },
              {
                "kind": "flag_update_candidate",
                "target_candidate": "per_index_flag_table_candidate",
                "operation_candidate": "set bit 7",
                "table_base": 60416,
                "table_base_hex": "H'EC00",
                "evidence_addresses": [
                  48258,
                  48285
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BC82",
                  "H'BC9D"
                ]
              },
              {
                "kind": "response_staging_candidate",
                "response_candidates": [
                  "response_at_BCCD"
                ],
                "operation_candidate": "stage F850-F854 and call loc_BA26",
                "evidence_addresses": [
                  48333
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BCCD"
                ]
              }
            ],
            "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.",
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC20",
              "H'BC22",
              "H'BCB0",
              "H'BCB9",
              "H'BCC1",
              "H'BCC9",
              "H'BCB5",
              "H'BCBD",
              "H'BCC5",
              "H'BCCD"
            ]
          },
          {
            "kind": "command_candidate",
            "command_value": 1,
            "command_value_hex": "H'01",
            "name_candidate": "read_value",
            "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence",
            "handler_alternatives": [
              {
                "handler_start": 48343,
                "handler_start_hex": "H'BCD7",
                "handler_end": 48385,
                "handler_end_hex": "H'BD01",
                "dispatch_compare_address": 48164,
                "dispatch_compare_address_hex": "H'BC24",
                "dispatch_branch_address": 48166,
                "dispatch_branch_address_hex": "H'BC26",
                "availability": "initial_idle_dispatch",
                "availability_conditions": [
                  "valid checksum/no RX physical error",
                  "FAA2 == 0",
                  "F861.bit7 == 0"
                ]
              }
            ],
            "evidence_addresses": [
              48136,
              48140,
              48164,
              48166,
              48343,
              48352,
              48360,
              48368,
              48374,
              48348,
              48356,
              48378
            ],
            "response_candidates": [
              "response_at_BCFA"
            ],
            "rx_reads": [
              {
                "instruction_address": 48348,
                "instruction_address_hex": "H'BCDC",
                "rx_offset": 1,
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "instruction": "MOV:G.B @H'F861, R0"
              },
              {
                "instruction_address": 48356,
                "instruction_address_hex": "H'BCE4",
                "rx_offset": 2,
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "instruction": "MOV:G.B @H'F862, R0"
              }
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
            "handler_start": 48343,
            "handler_start_hex": "H'BCD7",
            "handler_end": 48385,
            "handler_end_hex": "H'BD01",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0",
              "F861.bit7 == 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0",
            "semantic_notes": [
              "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.",
              "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.",
              "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.",
              "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame."
            ],
            "effects": [
              {
                "kind": "table_read_candidate",
                "target_candidate": "primary_value_table_candidate",
                "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7",
                "table_base": 57344,
                "table_base_hex": "H'E000",
                "address_expression_candidate": "E000 + 2*selector",
                "evidence_addresses": [
                  48364
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BCEC"
                ]
              },
              {
                "kind": "response_staging_candidate",
                "response_candidates": [
                  "response_at_BCFA"
                ],
                "operation_candidate": "stage F850-F854 and call loc_BA26",
                "evidence_addresses": [
                  48378
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BCFA"
                ]
              }
            ],
            "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.",
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC24",
              "H'BC26",
              "H'BCD7",
              "H'BCE0",
              "H'BCE8",
              "H'BCF0",
              "H'BCF6",
              "H'BCDC",
              "H'BCE4",
              "H'BCFA"
            ]
          },
          {
            "kind": "command_candidate",
            "command_value": 2,
            "command_value_hex": "H'02",
            "name_candidate": "clear_or_abort",
            "summary": "candidate clear/abort path with no immediate response builder",
            "handler_alternatives": [
              {
                "handler_start": 48388,
                "handler_start_hex": "H'BD04",
                "handler_end": 48395,
                "handler_end_hex": "H'BD0B",
                "dispatch_compare_address": 48169,
                "dispatch_compare_address_hex": "H'BC29",
                "dispatch_branch_address": 48171,
                "dispatch_branch_address_hex": "H'BC2B",
                "availability": "initial_idle_dispatch",
                "availability_conditions": [
                  "valid checksum/no RX physical error",
                  "FAA2 == 0"
                ]
              }
            ],
            "evidence_addresses": [
              48136,
              48140,
              48169,
              48171
            ],
            "response_candidates": [],
            "rx_reads": [],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
            "handler_start": 48388,
            "handler_start_hex": "H'BD04",
            "handler_end": 48395,
            "handler_end_hex": "H'BD0B",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
            "semantic_notes": [],
            "effects": [
              {
                "kind": "state_clear_candidate",
                "target_candidate": "serial_session_flags_candidate",
                "state_address": 64162,
                "state_address_hex": "H'FAA2",
                "operation_candidate": "clear bit 7",
                "evidence_addresses": [
                  48388
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BD04"
                ]
              }
            ],
            "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.",
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC29",
              "H'BC2B"
            ]
          },
          {
            "kind": "command_candidate",
            "command_value": 4,
            "command_value_hex": "H'04",
            "name_candidate": "set_value_no_immediate_reply",
            "summary": "candidate write/update path that stores a value without an immediate serial response",
            "handler_alternatives": [
              {
                "handler_start": 48398,
                "handler_start_hex": "H'BD0E",
                "handler_end": 48509,
                "handler_end_hex": "H'BD7D",
                "dispatch_compare_address": 48197,
                "dispatch_compare_address_hex": "H'BC45",
                "dispatch_branch_address": 48199,
                "dispatch_branch_address_hex": "H'BC47",
                "availability": "continuation_dispatch",
                "availability_conditions": [
                  "valid checksum/no RX physical error",
                  "FAA2 != 0"
                ]
              }
            ],
            "evidence_addresses": [
              48136,
              48140,
              48197,
              48199
            ],
            "response_candidates": [],
            "rx_reads": [
              {
                "instruction_address": 48402,
                "instruction_address_hex": "H'BD12",
                "rx_offset": 3,
                "rx_address": 63587,
                "rx_address_hex": "H'F863",
                "instruction": "MOV:G.B @H'F863, R0"
              },
              {
                "instruction_address": 48427,
                "instruction_address_hex": "H'BD2B",
                "rx_offset": 3,
                "rx_address": 63587,
                "rx_address_hex": "H'F863",
                "instruction": "MOV:G.B @H'F863, R0"
              },
              {
                "instruction_address": 48433,
                "instruction_address_hex": "H'BD31",
                "rx_offset": 4,
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
            "handler_start": 48398,
            "handler_start_hex": "H'BD0E",
            "handler_end": 48509,
            "handler_end_hex": "H'BD7D",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
            "semantic_notes": [],
            "effects": [
              {
                "kind": "table_write_candidate",
                "target_candidate": "primary_value_table_candidate",
                "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero",
                "table_base": 57344,
                "table_base_hex": "H'E000",
                "evidence_addresses": [
                  48410,
                  48437
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BD1A",
                  "H'BD35"
                ]
              },
              {
                "kind": "flag_update_candidate",
                "target_candidate": "per_index_flag_table_candidate",
                "operation_candidate": "set bit 7",
                "table_base": 60416,
                "table_base_hex": "H'EC00",
                "evidence_addresses": [
                  48418,
                  48441
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BD22",
                  "H'BD39"
                ]
              }
            ],
            "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.",
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC45",
              "H'BC47"
            ]
          },
          {
            "kind": "command_candidate",
            "command_value": 5,
            "command_value_hex": "H'05",
            "name_candidate": "ack_or_clear_pending",
            "summary": "continuation-only conditional acknowledgement/session clear path",
            "handler_alternatives": [
              {
                "handler_start": 48512,
                "handler_start_hex": "H'BD80",
                "handler_end": 48600,
                "handler_end_hex": "H'BDD8",
                "dispatch_compare_address": 48202,
                "dispatch_compare_address_hex": "H'BC4A",
                "dispatch_branch_address": 48204,
                "dispatch_branch_address_hex": "H'BC4C",
                "availability": "continuation_dispatch",
                "availability_conditions": [
                  "valid checksum/no RX physical error",
                  "FAA2 != 0"
                ]
              }
            ],
            "evidence_addresses": [
              48136,
              48140,
              48202,
              48204
            ],
            "response_candidates": [],
            "rx_reads": [],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
            "handler_start": 48512,
            "handler_start_hex": "H'BD80",
            "handler_end": 48600,
            "handler_end_hex": "H'BDD8",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
            "semantic_notes": [
              "Only accepted on the continuation dispatcher path when FAA2 != 0.",
              "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.",
              "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.",
              "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work."
            ],
            "effects": [
              {
                "kind": "conditional_ack_session_clear_candidate",
                "target_candidate": "selected event/pending state",
                "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response",
                "selector_without_response_hex": "H'0040",
                "requires": [
                  "FAA2 != 0"
                ],
                "fallthrough_when": "FAA2 == 0",
                "evidence_addresses": [
                  48578,
                  48596,
                  48592,
                  48584,
                  48588
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BDC2",
                  "H'BDD4",
                  "H'BDD0",
                  "H'BDC8",
                  "H'BDCC"
                ]
              }
            ],
            "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.",
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC4A",
              "H'BC4C"
            ]
          },
          {
            "kind": "command_candidate",
            "command_value": 6,
            "command_value_hex": "H'06",
            "name_candidate": "set_secondary_value",
            "summary": "candidate secondary-table value write path",
            "handler_alternatives": [
              {
                "handler_start": 48603,
                "handler_start_hex": "H'BDDB",
                "handler_end": 48643,
                "handler_end_hex": "H'BE03",
                "dispatch_compare_address": 48207,
                "dispatch_compare_address_hex": "H'BC4F",
                "dispatch_branch_address": 48209,
                "dispatch_branch_address_hex": "H'BC51",
                "availability": "continuation_dispatch",
                "availability_conditions": [
                  "valid checksum/no RX physical error",
                  "FAA2 != 0"
                ]
              }
            ],
            "evidence_addresses": [
              48136,
              48140,
              48207,
              48209
            ],
            "response_candidates": [],
            "rx_reads": [
              {
                "instruction_address": 48603,
                "instruction_address_hex": "H'BDDB",
                "rx_offset": 3,
                "rx_address": 63587,
                "rx_address_hex": "H'F863",
                "instruction": "MOV:G.B @H'F863, R0"
              },
              {
                "instruction_address": 48609,
                "instruction_address_hex": "H'BDE1",
                "rx_offset": 4,
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
            "handler_start": 48603,
            "handler_start_hex": "H'BDDB",
            "handler_end": 48643,
            "handler_end_hex": "H'BE03",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
            "semantic_notes": [],
            "effects": [
              {
                "kind": "table_write_candidate",
                "target_candidate": "secondary_value_table_candidate",
                "source_candidate": "RX[3:4] value bytes",
                "table_base": 58368,
                "table_base_hex": "H'E400",
                "evidence_addresses": [
                  48613
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BDE5"
                ]
              },
              {
                "kind": "flag_update_candidate",
                "target_candidate": "per_index_flag_table_candidate",
                "operation_candidate": "set bit 6",
                "table_base": 60416,
                "table_base_hex": "H'EC00",
                "evidence_addresses": [
                  48617
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BDE9"
                ]
              }
            ],
            "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.",
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC4F",
              "H'BC51"
            ]
          },
          {
            "kind": "command_candidate",
            "command_value": 7,
            "command_value_hex": "H'07",
            "name_candidate": "retransmit_or_error_reply",
            "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo",
            "handler_alternatives": [
              {
                "handler_start": 48645,
                "handler_start_hex": "H'BE05",
                "handler_end": 48677,
                "handler_end_hex": "H'BE25",
                "dispatch_compare_address": 48174,
                "dispatch_compare_address_hex": "H'BC2E",
                "dispatch_branch_address": 48176,
                "dispatch_branch_address_hex": "H'BC30",
                "availability": "initial_idle_dispatch",
                "availability_conditions": [
                  "valid checksum/no RX physical error",
                  "FAA2 == 0"
                ]
              },
              {
                "handler_start": 48645,
                "handler_start_hex": "H'BE05",
                "handler_end": 48677,
                "handler_end_hex": "H'BE25",
                "dispatch_compare_address": 48212,
                "dispatch_compare_address_hex": "H'BC54",
                "dispatch_branch_address": 48214,
                "dispatch_branch_address_hex": "H'BC56",
                "availability": "continuation_dispatch",
                "availability_conditions": [
                  "valid checksum/no RX physical error",
                  "FAA2 != 0"
                ]
              }
            ],
            "evidence_addresses": [
              48136,
              48140,
              48174,
              48176,
              48212,
              48214,
              48649,
              48657,
              48665,
              48674
            ],
            "response_candidates": [
              "response_at_BE22"
            ],
            "rx_reads": [],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
            "handler_start": 48645,
            "handler_start_hex": "H'BE05",
            "handler_end": 48677,
            "handler_end_hex": "H'BE25",
            "availability": [
              "initial_idle_dispatch",
              "continuation_dispatch"
            ],
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0",
              "FAA2 != 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0",
            "semantic_notes": [
              "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.",
              "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value."
            ],
            "effects": [
              {
                "kind": "retransmit_candidate",
                "source_candidate": "previous TX frame bytes H'F858-H'F85C",
                "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26",
                "response_candidates": [
                  "response_at_BE22"
                ],
                "evidence_addresses": [
                  48645,
                  48649,
                  48653,
                  48657,
                  48661,
                  48665,
                  48669,
                  48674
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BE05",
                  "H'BE09",
                  "H'BE0D",
                  "H'BE11",
                  "H'BE15",
                  "H'BE19",
                  "H'BE1D",
                  "H'BE22"
                ]
              },
              {
                "kind": "retry_error_echo_candidate",
                "source_candidate": "RX payload bytes F861-F864",
                "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26",
                "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value",
                "response_candidates": [],
                "evidence_addresses": [],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": []
              },
              {
                "kind": "response_staging_candidate",
                "response_candidates": [
                  "response_at_BE22"
                ],
                "operation_candidate": "stage F850-F854 and call loc_BA26",
                "evidence_addresses": [
                  48674
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BE22"
                ]
              }
            ],
            "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.",
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC2E",
              "H'BC30",
              "H'BC54",
              "H'BC56",
              "H'BE09",
              "H'BE11",
              "H'BE19",
              "H'BE22"
            ]
          }
        ],
        "command_effects": [
          {
            "kind": "command_effects_candidate",
            "command_value": 0,
            "command_value_hex": "H'00",
            "name_candidate": "set_value_acked",
            "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
            "semantic_notes": [],
            "effects": [
              {
                "kind": "table_write_candidate",
                "target_candidate": "primary_value_table_candidate",
                "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero",
                "table_base": 57344,
                "table_base_hex": "H'E000",
                "evidence_addresses": [
                  48245,
                  48277
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BC75",
                  "H'BC95"
                ]
              },
              {
                "kind": "table_write_candidate",
                "target_candidate": "current_value_table_candidate",
                "source_candidate": "same candidate value written to the primary table",
                "table_base": 59392,
                "table_base_hex": "H'E800",
                "evidence_addresses": [
                  48249,
                  48281
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BC79",
                  "H'BC99"
                ]
              },
              {
                "kind": "flag_update_candidate",
                "target_candidate": "per_index_flag_table_candidate",
                "operation_candidate": "set bit 7",
                "table_base": 60416,
                "table_base_hex": "H'EC00",
                "evidence_addresses": [
                  48258,
                  48285
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BC82",
                  "H'BC9D"
                ]
              },
              {
                "kind": "response_staging_candidate",
                "response_candidates": [
                  "response_at_BCCD"
                ],
                "operation_candidate": "stage F850-F854 and call loc_BA26",
                "evidence_addresses": [
                  48333
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BCCD"
                ]
              }
            ],
            "response_candidates": [
              "response_at_BCCD"
            ],
            "evidence_addresses": [
              48136,
              48140,
              48160,
              48162,
              48304,
              48313,
              48321,
              48329,
              48309,
              48317,
              48325,
              48333
            ],
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC20",
              "H'BC22",
              "H'BCB0",
              "H'BCB9",
              "H'BCC1",
              "H'BCC9",
              "H'BCB5",
              "H'BCBD",
              "H'BCC5",
              "H'BCCD"
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
          },
          {
            "kind": "command_effects_candidate",
            "command_value": 1,
            "command_value_hex": "H'01",
            "name_candidate": "read_value",
            "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0",
              "F861.bit7 == 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0",
            "semantic_notes": [
              "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.",
              "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.",
              "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.",
              "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame."
            ],
            "effects": [
              {
                "kind": "table_read_candidate",
                "target_candidate": "primary_value_table_candidate",
                "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7",
                "table_base": 57344,
                "table_base_hex": "H'E000",
                "address_expression_candidate": "E000 + 2*selector",
                "evidence_addresses": [
                  48364
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BCEC"
                ]
              },
              {
                "kind": "response_staging_candidate",
                "response_candidates": [
                  "response_at_BCFA"
                ],
                "operation_candidate": "stage F850-F854 and call loc_BA26",
                "evidence_addresses": [
                  48378
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BCFA"
                ]
              }
            ],
            "response_candidates": [
              "response_at_BCFA"
            ],
            "evidence_addresses": [
              48136,
              48140,
              48164,
              48166,
              48343,
              48352,
              48360,
              48368,
              48374,
              48348,
              48356,
              48378
            ],
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC24",
              "H'BC26",
              "H'BCD7",
              "H'BCE0",
              "H'BCE8",
              "H'BCF0",
              "H'BCF6",
              "H'BCDC",
              "H'BCE4",
              "H'BCFA"
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
          },
          {
            "kind": "command_effects_candidate",
            "command_value": 2,
            "command_value_hex": "H'02",
            "name_candidate": "clear_or_abort",
            "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
            "semantic_notes": [],
            "effects": [
              {
                "kind": "state_clear_candidate",
                "target_candidate": "serial_session_flags_candidate",
                "state_address": 64162,
                "state_address_hex": "H'FAA2",
                "operation_candidate": "clear bit 7",
                "evidence_addresses": [
                  48388
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BD04"
                ]
              }
            ],
            "response_candidates": [],
            "evidence_addresses": [
              48136,
              48140,
              48169,
              48171
            ],
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC29",
              "H'BC2B"
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
          },
          {
            "kind": "command_effects_candidate",
            "command_value": 4,
            "command_value_hex": "H'04",
            "name_candidate": "set_value_no_immediate_reply",
            "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
            "semantic_notes": [],
            "effects": [
              {
                "kind": "table_write_candidate",
                "target_candidate": "primary_value_table_candidate",
                "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero",
                "table_base": 57344,
                "table_base_hex": "H'E000",
                "evidence_addresses": [
                  48410,
                  48437
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BD1A",
                  "H'BD35"
                ]
              },
              {
                "kind": "flag_update_candidate",
                "target_candidate": "per_index_flag_table_candidate",
                "operation_candidate": "set bit 7",
                "table_base": 60416,
                "table_base_hex": "H'EC00",
                "evidence_addresses": [
                  48418,
                  48441
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BD22",
                  "H'BD39"
                ]
              }
            ],
            "response_candidates": [],
            "evidence_addresses": [
              48136,
              48140,
              48197,
              48199
            ],
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC45",
              "H'BC47"
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
          },
          {
            "kind": "command_effects_candidate",
            "command_value": 5,
            "command_value_hex": "H'05",
            "name_candidate": "ack_or_clear_pending",
            "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
            "semantic_notes": [
              "Only accepted on the continuation dispatcher path when FAA2 != 0.",
              "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.",
              "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.",
              "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work."
            ],
            "effects": [
              {
                "kind": "conditional_ack_session_clear_candidate",
                "target_candidate": "selected event/pending state",
                "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response",
                "selector_without_response_hex": "H'0040",
                "requires": [
                  "FAA2 != 0"
                ],
                "fallthrough_when": "FAA2 == 0",
                "evidence_addresses": [
                  48578,
                  48596,
                  48592,
                  48584,
                  48588
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BDC2",
                  "H'BDD4",
                  "H'BDD0",
                  "H'BDC8",
                  "H'BDCC"
                ]
              }
            ],
            "response_candidates": [],
            "evidence_addresses": [
              48136,
              48140,
              48202,
              48204
            ],
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC4A",
              "H'BC4C"
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
          },
          {
            "kind": "command_effects_candidate",
            "command_value": 6,
            "command_value_hex": "H'06",
            "name_candidate": "set_secondary_value",
            "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
            "semantic_notes": [],
            "effects": [
              {
                "kind": "table_write_candidate",
                "target_candidate": "secondary_value_table_candidate",
                "source_candidate": "RX[3:4] value bytes",
                "table_base": 58368,
                "table_base_hex": "H'E400",
                "evidence_addresses": [
                  48613
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BDE5"
                ]
              },
              {
                "kind": "flag_update_candidate",
                "target_candidate": "per_index_flag_table_candidate",
                "operation_candidate": "set bit 6",
                "table_base": 60416,
                "table_base_hex": "H'EC00",
                "evidence_addresses": [
                  48617
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BDE9"
                ]
              }
            ],
            "response_candidates": [],
            "evidence_addresses": [
              48136,
              48140,
              48207,
              48209
            ],
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC4F",
              "H'BC51"
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
          },
          {
            "kind": "command_effects_candidate",
            "command_value": 7,
            "command_value_hex": "H'07",
            "name_candidate": "retransmit_or_error_reply",
            "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.",
            "availability": [
              "initial_idle_dispatch",
              "continuation_dispatch"
            ],
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0",
              "FAA2 != 0"
            ],
            "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0",
            "semantic_notes": [
              "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.",
              "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value."
            ],
            "effects": [
              {
                "kind": "retransmit_candidate",
                "source_candidate": "previous TX frame bytes H'F858-H'F85C",
                "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26",
                "response_candidates": [
                  "response_at_BE22"
                ],
                "evidence_addresses": [
                  48645,
                  48649,
                  48653,
                  48657,
                  48661,
                  48665,
                  48669,
                  48674
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BE05",
                  "H'BE09",
                  "H'BE0D",
                  "H'BE11",
                  "H'BE15",
                  "H'BE19",
                  "H'BE1D",
                  "H'BE22"
                ]
              },
              {
                "kind": "retry_error_echo_candidate",
                "source_candidate": "RX payload bytes F861-F864",
                "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26",
                "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value",
                "response_candidates": [],
                "evidence_addresses": [],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": []
              },
              {
                "kind": "response_staging_candidate",
                "response_candidates": [
                  "response_at_BE22"
                ],
                "operation_candidate": "stage F850-F854 and call loc_BA26",
                "evidence_addresses": [
                  48674
                ],
                "confidence": "candidate-medium",
                "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
                "evidence_addresses_hex": [
                  "H'BE22"
                ]
              }
            ],
            "response_candidates": [
              "response_at_BE22"
            ],
            "evidence_addresses": [
              48136,
              48140,
              48174,
              48176,
              48212,
              48214,
              48649,
              48657,
              48665,
              48674
            ],
            "evidence_addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC2E",
              "H'BC30",
              "H'BC54",
              "H'BC56",
              "H'BE09",
              "H'BE11",
              "H'BE19",
              "H'BE22"
            ],
            "confidence": "medium",
            "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
          }
        ],
        "index_decoder": {
          "kind": "logical_index_decoder_candidate",
          "label": "loc_622B",
          "address": 25131,
          "address_hex": "H'622B",
          "input_fields": [
            "addr_page_flags",
            "addr_offset"
          ],
          "output_register": "R5",
          "post_scale_register": "R4",
          "post_scale": "R4 = R5 << 1",
          "mapping_candidate": [
            {
              "page": 0,
              "offset_range": "0x00-0x7F",
              "index_range": "0x000-0x07F"
            },
            {
              "page": 1,
              "offset_range": "0x00-0xFF",
              "index_range": "0x080-0x17F"
            },
            {
              "page": 2,
              "offset_range": "0x00-0x7F",
              "index_range": "0x180-0x1FF"
            },
            {
              "page": "other/overflow",
              "index": "0x1FF"
            }
          ],
          "evidence_addresses": [
            48129
          ],
          "evidence_addresses_hex": [
            "H'BC01"
          ],
          "confidence": "medium",
          "caveat": "Mapping is inferred from loc_622B behavior and the nearby R4 = R5 << 1 table-index use."
        },
        "logical_table_map_candidates": [
          {
            "kind": "logical_table_map_candidate",
            "name_candidate": "primary_value_table_candidate",
            "element_candidate": "word_value",
            "logical_base_address": 57344,
            "logical_base_address_hex": "H'E000",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "observed_index_registers": [
              "R0",
              "R3",
              "R4"
            ],
            "observed_accesses": [
              "read",
              "write"
            ],
            "observed_widths": [
              2
            ],
            "accesses": [
              {
                "instruction_address": 6627,
                "instruction_address_hex": "H'19E3",
                "operand": "@(-H'2000,R3)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'2000,R3), R0"
              },
              {
                "instruction_address": 6659,
                "instruction_address_hex": "H'1A03",
                "operand": "@(-H'2000,R3)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "CMP:G.W @(-H'2000,R3), R1"
              },
              {
                "instruction_address": 6717,
                "instruction_address_hex": "H'1A3D",
                "operand": "@(-H'2000,R3)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'2000,R3), R0"
              },
              {
                "instruction_address": 6763,
                "instruction_address_hex": "H'1A6B",
                "operand": "@(-H'2000,R3)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "CMP:G.W @(-H'2000,R3), R0"
              },
              {
                "instruction_address": 16268,
                "instruction_address_hex": "H'3F8C",
                "operand": "@(-H'2000,R0)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'2000,R0)"
              },
              {
                "instruction_address": 16503,
                "instruction_address_hex": "H'4077",
                "operand": "@(-H'2000,R0)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'2000,R0)"
              },
              {
                "instruction_address": 48245,
                "instruction_address_hex": "H'BC75",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'2000,R4)"
              },
              {
                "instruction_address": 48277,
                "instruction_address_hex": "H'BC95",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'2000,R4)"
              },
              {
                "instruction_address": 48364,
                "instruction_address_hex": "H'BCEC",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'2000,R4), R0"
              },
              {
                "instruction_address": 48410,
                "instruction_address_hex": "H'BD1A",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'2000,R4)"
              },
              {
                "instruction_address": 48437,
                "instruction_address_hex": "H'BD35",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'2000,R4)"
              }
            ],
            "evidence_addresses": [
              6627,
              6659,
              6717,
              6763,
              16268,
              16503,
              48245,
              48277,
              48364,
              48410,
              48437
            ],
            "evidence_addresses_hex": [
              "H'19E3",
              "H'1A03",
              "H'1A3D",
              "H'1A6B",
              "H'3F8C",
              "H'4077",
              "H'BC75",
              "H'BC95",
              "H'BCEC",
              "H'BD1A",
              "H'BD35"
            ],
            "confidence": "candidate-medium",
            "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
          },
          {
            "kind": "logical_table_map_candidate",
            "name_candidate": "secondary_value_table_candidate",
            "element_candidate": "word_value",
            "logical_base_address": 58368,
            "logical_base_address_hex": "H'E400",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "observed_index_registers": [
              "R0",
              "R3",
              "R4"
            ],
            "observed_accesses": [
              "read",
              "write"
            ],
            "observed_widths": [
              2
            ],
            "accesses": [
              {
                "instruction_address": 6570,
                "instruction_address_hex": "H'19AA",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'1C00,R3), R0"
              },
              {
                "instruction_address": 6731,
                "instruction_address_hex": "H'1A4B",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'1C00,R3), R1"
              },
              {
                "instruction_address": 6747,
                "instruction_address_hex": "H'1A5B",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'1C00,R3), R1"
              },
              {
                "instruction_address": 6785,
                "instruction_address_hex": "H'1A81",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "AND.W @(-H'1C00,R3), R1"
              },
              {
                "instruction_address": 6836,
                "instruction_address_hex": "H'1AB4",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "BTST.W R0, @(-H'1C00,R3)"
              },
              {
                "instruction_address": 6849,
                "instruction_address_hex": "H'1AC1",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "BTST.W R0, @(-H'1C00,R3)"
              },
              {
                "instruction_address": 16507,
                "instruction_address_hex": "H'407B",
                "operand": "@(-H'1C00,R0)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'1C00,R0)"
              },
              {
                "instruction_address": 48613,
                "instruction_address_hex": "H'BDE5",
                "operand": "@(-H'1C00,R4)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1C00,R4)"
              }
            ],
            "evidence_addresses": [
              6570,
              6731,
              6747,
              6785,
              6836,
              6849,
              16507,
              48613
            ],
            "evidence_addresses_hex": [
              "H'19AA",
              "H'1A4B",
              "H'1A5B",
              "H'1A81",
              "H'1AB4",
              "H'1AC1",
              "H'407B",
              "H'BDE5"
            ],
            "confidence": "candidate-medium",
            "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
          },
          {
            "kind": "logical_table_map_candidate",
            "name_candidate": "current_value_table_candidate",
            "element_candidate": "word_value",
            "logical_base_address": 59392,
            "logical_base_address_hex": "H'E800",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "observed_index_registers": [
              "R0",
              "R3",
              "R4"
            ],
            "observed_accesses": [
              "read",
              "write"
            ],
            "observed_widths": [
              2
            ],
            "accesses": [
              {
                "instruction_address": 6665,
                "instruction_address_hex": "H'1A09",
                "operand": "@(-H'1800,R3)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R3",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R1, @(-H'1800,R3)"
              },
              {
                "instruction_address": 6769,
                "instruction_address_hex": "H'1A71",
                "operand": "@(-H'1800,R3)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R3",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1800,R3)"
              },
              {
                "instruction_address": 16272,
                "instruction_address_hex": "H'3F90",
                "operand": "@(-H'1800,R0)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'1800,R0)"
              },
              {
                "instruction_address": 16511,
                "instruction_address_hex": "H'407F",
                "operand": "@(-H'1800,R0)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'1800,R0)"
              },
              {
                "instruction_address": 47925,
                "instruction_address_hex": "H'BB35",
                "operand": "@(-H'1800,R0)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R0",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'1800,R0), R4"
              },
              {
                "instruction_address": 48249,
                "instruction_address_hex": "H'BC79",
                "operand": "@(-H'1800,R4)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1800,R4)"
              },
              {
                "instruction_address": 48281,
                "instruction_address_hex": "H'BC99",
                "operand": "@(-H'1800,R4)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1800,R4)"
              },
              {
                "instruction_address": 48414,
                "instruction_address_hex": "H'BD1E",
                "operand": "@(-H'1800,R4)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1800,R4)"
              }
            ],
            "evidence_addresses": [
              6665,
              6769,
              16272,
              16511,
              47925,
              48249,
              48281,
              48414
            ],
            "evidence_addresses_hex": [
              "H'1A09",
              "H'1A71",
              "H'3F90",
              "H'407F",
              "H'BB35",
              "H'BC79",
              "H'BC99",
              "H'BD1E"
            ],
            "confidence": "candidate-medium",
            "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
          },
          {
            "kind": "logical_table_map_candidate",
            "name_candidate": "flag_table_candidate",
            "element_candidate": "bit_flags",
            "logical_base_address": 60416,
            "logical_base_address_hex": "H'EC00",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "observed_index_registers": [
              "R0",
              "R5"
            ],
            "observed_accesses": [
              "write"
            ],
            "observed_widths": [
              1,
              2
            ],
            "accesses": [
              {
                "instruction_address": 16520,
                "instruction_address_hex": "H'4088",
                "operand": "@(-H'1400,R0)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'1400,R0)"
              },
              {
                "instruction_address": 48258,
                "instruction_address_hex": "H'BC82",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #7, @(-H'1400,R5)"
              },
              {
                "instruction_address": 48285,
                "instruction_address_hex": "H'BC9D",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #7, @(-H'1400,R5)"
              },
              {
                "instruction_address": 48418,
                "instruction_address_hex": "H'BD22",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #7, @(-H'1400,R5)"
              },
              {
                "instruction_address": 48441,
                "instruction_address_hex": "H'BD39",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #7, @(-H'1400,R5)"
              },
              {
                "instruction_address": 48617,
                "instruction_address_hex": "H'BDE9",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #6, @(-H'1400,R5)"
              }
            ],
            "evidence_addresses": [
              16520,
              48258,
              48285,
              48418,
              48441,
              48617
            ],
            "evidence_addresses_hex": [
              "H'4088",
              "H'BC82",
              "H'BC9D",
              "H'BD22",
              "H'BD39",
              "H'BDE9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
          }
        ],
        "table_map_candidates": [
          {
            "kind": "logical_table_map_candidate",
            "name_candidate": "primary_value_table_candidate",
            "element_candidate": "word_value",
            "logical_base_address": 57344,
            "logical_base_address_hex": "H'E000",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "observed_index_registers": [
              "R0",
              "R3",
              "R4"
            ],
            "observed_accesses": [
              "read",
              "write"
            ],
            "observed_widths": [
              2
            ],
            "accesses": [
              {
                "instruction_address": 6627,
                "instruction_address_hex": "H'19E3",
                "operand": "@(-H'2000,R3)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'2000,R3), R0"
              },
              {
                "instruction_address": 6659,
                "instruction_address_hex": "H'1A03",
                "operand": "@(-H'2000,R3)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "CMP:G.W @(-H'2000,R3), R1"
              },
              {
                "instruction_address": 6717,
                "instruction_address_hex": "H'1A3D",
                "operand": "@(-H'2000,R3)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'2000,R3), R0"
              },
              {
                "instruction_address": 6763,
                "instruction_address_hex": "H'1A6B",
                "operand": "@(-H'2000,R3)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "CMP:G.W @(-H'2000,R3), R0"
              },
              {
                "instruction_address": 16268,
                "instruction_address_hex": "H'3F8C",
                "operand": "@(-H'2000,R0)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'2000,R0)"
              },
              {
                "instruction_address": 16503,
                "instruction_address_hex": "H'4077",
                "operand": "@(-H'2000,R0)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'2000,R0)"
              },
              {
                "instruction_address": 48245,
                "instruction_address_hex": "H'BC75",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'2000,R4)"
              },
              {
                "instruction_address": 48277,
                "instruction_address_hex": "H'BC95",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'2000,R4)"
              },
              {
                "instruction_address": 48364,
                "instruction_address_hex": "H'BCEC",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'2000,R4), R0"
              },
              {
                "instruction_address": 48410,
                "instruction_address_hex": "H'BD1A",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'2000,R4)"
              },
              {
                "instruction_address": 48437,
                "instruction_address_hex": "H'BD35",
                "operand": "@(-H'2000,R4)",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'2000,R4)"
              }
            ],
            "evidence_addresses": [
              6627,
              6659,
              6717,
              6763,
              16268,
              16503,
              48245,
              48277,
              48364,
              48410,
              48437
            ],
            "evidence_addresses_hex": [
              "H'19E3",
              "H'1A03",
              "H'1A3D",
              "H'1A6B",
              "H'3F8C",
              "H'4077",
              "H'BC75",
              "H'BC95",
              "H'BCEC",
              "H'BD1A",
              "H'BD35"
            ],
            "confidence": "candidate-medium",
            "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
          },
          {
            "kind": "logical_table_map_candidate",
            "name_candidate": "secondary_value_table_candidate",
            "element_candidate": "word_value",
            "logical_base_address": 58368,
            "logical_base_address_hex": "H'E400",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "observed_index_registers": [
              "R0",
              "R3",
              "R4"
            ],
            "observed_accesses": [
              "read",
              "write"
            ],
            "observed_widths": [
              2
            ],
            "accesses": [
              {
                "instruction_address": 6570,
                "instruction_address_hex": "H'19AA",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'1C00,R3), R0"
              },
              {
                "instruction_address": 6731,
                "instruction_address_hex": "H'1A4B",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'1C00,R3), R1"
              },
              {
                "instruction_address": 6747,
                "instruction_address_hex": "H'1A5B",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'1C00,R3), R1"
              },
              {
                "instruction_address": 6785,
                "instruction_address_hex": "H'1A81",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "AND.W @(-H'1C00,R3), R1"
              },
              {
                "instruction_address": 6836,
                "instruction_address_hex": "H'1AB4",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "BTST.W R0, @(-H'1C00,R3)"
              },
              {
                "instruction_address": 6849,
                "instruction_address_hex": "H'1AC1",
                "operand": "@(-H'1C00,R3)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R3",
                "access": "read",
                "width": 2,
                "instruction": "BTST.W R0, @(-H'1C00,R3)"
              },
              {
                "instruction_address": 16507,
                "instruction_address_hex": "H'407B",
                "operand": "@(-H'1C00,R0)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'1C00,R0)"
              },
              {
                "instruction_address": 48613,
                "instruction_address_hex": "H'BDE5",
                "operand": "@(-H'1C00,R4)",
                "negative_offset": 7168,
                "negative_offset_hex": "H'1C00",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1C00,R4)"
              }
            ],
            "evidence_addresses": [
              6570,
              6731,
              6747,
              6785,
              6836,
              6849,
              16507,
              48613
            ],
            "evidence_addresses_hex": [
              "H'19AA",
              "H'1A4B",
              "H'1A5B",
              "H'1A81",
              "H'1AB4",
              "H'1AC1",
              "H'407B",
              "H'BDE5"
            ],
            "confidence": "candidate-medium",
            "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
          },
          {
            "kind": "logical_table_map_candidate",
            "name_candidate": "current_value_table_candidate",
            "element_candidate": "word_value",
            "logical_base_address": 59392,
            "logical_base_address_hex": "H'E800",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "observed_index_registers": [
              "R0",
              "R3",
              "R4"
            ],
            "observed_accesses": [
              "read",
              "write"
            ],
            "observed_widths": [
              2
            ],
            "accesses": [
              {
                "instruction_address": 6665,
                "instruction_address_hex": "H'1A09",
                "operand": "@(-H'1800,R3)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R3",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R1, @(-H'1800,R3)"
              },
              {
                "instruction_address": 6769,
                "instruction_address_hex": "H'1A71",
                "operand": "@(-H'1800,R3)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R3",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1800,R3)"
              },
              {
                "instruction_address": 16272,
                "instruction_address_hex": "H'3F90",
                "operand": "@(-H'1800,R0)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'1800,R0)"
              },
              {
                "instruction_address": 16511,
                "instruction_address_hex": "H'407F",
                "operand": "@(-H'1800,R0)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'1800,R0)"
              },
              {
                "instruction_address": 47925,
                "instruction_address_hex": "H'BB35",
                "operand": "@(-H'1800,R0)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R0",
                "access": "read",
                "width": 2,
                "instruction": "MOV:G.W @(-H'1800,R0), R4"
              },
              {
                "instruction_address": 48249,
                "instruction_address_hex": "H'BC79",
                "operand": "@(-H'1800,R4)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1800,R4)"
              },
              {
                "instruction_address": 48281,
                "instruction_address_hex": "H'BC99",
                "operand": "@(-H'1800,R4)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1800,R4)"
              },
              {
                "instruction_address": 48414,
                "instruction_address_hex": "H'BD1E",
                "operand": "@(-H'1800,R4)",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R4",
                "access": "write",
                "width": 2,
                "instruction": "MOV:G.W R0, @(-H'1800,R4)"
              }
            ],
            "evidence_addresses": [
              6665,
              6769,
              16272,
              16511,
              47925,
              48249,
              48281,
              48414
            ],
            "evidence_addresses_hex": [
              "H'1A09",
              "H'1A71",
              "H'3F90",
              "H'407F",
              "H'BB35",
              "H'BC79",
              "H'BC99",
              "H'BD1E"
            ],
            "confidence": "candidate-medium",
            "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
          },
          {
            "kind": "logical_table_map_candidate",
            "name_candidate": "flag_table_candidate",
            "element_candidate": "bit_flags",
            "logical_base_address": 60416,
            "logical_base_address_hex": "H'EC00",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "observed_index_registers": [
              "R0",
              "R5"
            ],
            "observed_accesses": [
              "write"
            ],
            "observed_widths": [
              1,
              2
            ],
            "accesses": [
              {
                "instruction_address": 16520,
                "instruction_address_hex": "H'4088",
                "operand": "@(-H'1400,R0)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R0",
                "access": "write",
                "width": 2,
                "instruction": "CLR.W @(-H'1400,R0)"
              },
              {
                "instruction_address": 48258,
                "instruction_address_hex": "H'BC82",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #7, @(-H'1400,R5)"
              },
              {
                "instruction_address": 48285,
                "instruction_address_hex": "H'BC9D",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #7, @(-H'1400,R5)"
              },
              {
                "instruction_address": 48418,
                "instruction_address_hex": "H'BD22",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #7, @(-H'1400,R5)"
              },
              {
                "instruction_address": 48441,
                "instruction_address_hex": "H'BD39",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #7, @(-H'1400,R5)"
              },
              {
                "instruction_address": 48617,
                "instruction_address_hex": "H'BDE9",
                "operand": "@(-H'1400,R5)",
                "negative_offset": 5120,
                "negative_offset_hex": "H'1400",
                "index_register": "R5",
                "access": "write",
                "width": 1,
                "instruction": "BSET.B #6, @(-H'1400,R5)"
              }
            ],
            "evidence_addresses": [
              16520,
              48258,
              48285,
              48418,
              48441,
              48617
            ],
            "evidence_addresses_hex": [
              "H'4088",
              "H'BC82",
              "H'BC9D",
              "H'BD22",
              "H'BD39",
              "H'BDE9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
          }
        ],
        "state_variable_candidates": [
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "serial_session_flags_candidate",
            "address": 64162,
            "address_hex": "H'FAA2",
            "access_count": 18,
            "read_count": 5,
            "write_count": 13,
            "bit_candidates": [
              3,
              7
            ],
            "immediate_values": [
              3,
              7
            ],
            "immediate_values_hex": [
              "H'0003",
              "H'0007"
            ],
            "accesses": [
              {
                "instruction_address": 47748,
                "instruction_address_hex": "H'BA84",
                "access": "read",
                "mnemonic": "BTST.B",
                "instruction": "BTST.B #3, @H'FAA2",
                "bit": 3,
                "immediate": 3,
                "immediate_hex": "H'03"
              },
              {
                "instruction_address": 47766,
                "instruction_address_hex": "H'BA96",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #3, @H'FAA2",
                "bit": 3,
                "immediate": 3,
                "immediate_hex": "H'03"
              },
              {
                "instruction_address": 47872,
                "instruction_address_hex": "H'BB00",
                "access": "write",
                "mnemonic": "BSET.B",
                "instruction": "BSET.B #3, @H'FAA2",
                "bit": 3,
                "immediate": 3,
                "immediate_hex": "H'03"
              },
              {
                "instruction_address": 48143,
                "instruction_address_hex": "H'BC0F",
                "access": "read",
                "mnemonic": "TST.B",
                "instruction": "TST.B @H'FAA2"
              },
              {
                "instruction_address": 48149,
                "instruction_address_hex": "H'BC15",
                "access": "write",
                "mnemonic": "BSET.B",
                "instruction": "BSET.B #7, @H'FAA2",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48179,
                "instruction_address_hex": "H'BC33",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA2"
              },
              {
                "instruction_address": 48220,
                "instruction_address_hex": "H'BC5C",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #3, @H'FAA2",
                "bit": 3,
                "immediate": 3,
                "immediate_hex": "H'03"
              },
              {
                "instruction_address": 48336,
                "instruction_address_hex": "H'BCD0",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #7, @H'FAA2",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48381,
                "instruction_address_hex": "H'BCFD",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #7, @H'FAA2",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48388,
                "instruction_address_hex": "H'BD04",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #7, @H'FAA2",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48487,
                "instruction_address_hex": "H'BD67",
                "access": "read",
                "mnemonic": "BTST.B",
                "instruction": "BTST.B #3, @H'FAA2",
                "bit": 3,
                "immediate": 3,
                "immediate_hex": "H'03"
              },
              {
                "instruction_address": 48505,
                "instruction_address_hex": "H'BD79",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA2"
              },
              {
                "instruction_address": 48578,
                "instruction_address_hex": "H'BDC2",
                "access": "read",
                "mnemonic": "BTST.B",
                "instruction": "BTST.B #3, @H'FAA2",
                "bit": 3,
                "immediate": 3,
                "immediate_hex": "H'03"
              },
              {
                "instruction_address": 48596,
                "instruction_address_hex": "H'BDD4",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA2"
              },
              {
                "instruction_address": 48621,
                "instruction_address_hex": "H'BDED",
                "access": "read",
                "mnemonic": "BTST.B",
                "instruction": "BTST.B #3, @H'FAA2",
                "bit": 3,
                "immediate": 3,
                "immediate_hex": "H'03"
              },
              {
                "instruction_address": 48639,
                "instruction_address_hex": "H'BDFF",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA2"
              },
              {
                "instruction_address": 48711,
                "instruction_address_hex": "H'BE47",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA2"
              },
              {
                "instruction_address": 48815,
                "instruction_address_hex": "H'BEAF",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA2"
              }
            ],
            "evidence_addresses": [
              47748,
              47766,
              47872,
              48143,
              48149,
              48179,
              48220,
              48336,
              48381,
              48388,
              48487,
              48505,
              48578,
              48596,
              48621,
              48639,
              48711,
              48815
            ],
            "evidence_addresses_hex": [
              "H'BA84",
              "H'BA96",
              "H'BB00",
              "H'BC0F",
              "H'BC15",
              "H'BC33",
              "H'BC5C",
              "H'BCD0",
              "H'BCFD",
              "H'BD04",
              "H'BD67",
              "H'BD79",
              "H'BDC2",
              "H'BDD4",
              "H'BDED",
              "H'BDFF",
              "H'BE47",
              "H'BEAF"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "serial_pending_mask_candidate",
            "address": 64163,
            "address_hex": "H'FAA3",
            "access_count": 10,
            "read_count": 1,
            "write_count": 9,
            "bit_candidates": [
              7
            ],
            "immediate_values": [
              128,
              7
            ],
            "immediate_values_hex": [
              "H'0080",
              "H'0007"
            ],
            "accesses": [
              {
                "instruction_address": 47770,
                "instruction_address_hex": "H'BA9A",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA3"
              },
              {
                "instruction_address": 47953,
                "instruction_address_hex": "H'BB51",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'80, @H'FAA3",
                "immediate": 128,
                "immediate_hex": "H'80"
              },
              {
                "instruction_address": 48227,
                "instruction_address_hex": "H'BC63",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA3"
              },
              {
                "instruction_address": 48501,
                "instruction_address_hex": "H'BD75",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA3"
              },
              {
                "instruction_address": 48592,
                "instruction_address_hex": "H'BDD0",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA3"
              },
              {
                "instruction_address": 48635,
                "instruction_address_hex": "H'BDFB",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA3"
              },
              {
                "instruction_address": 48707,
                "instruction_address_hex": "H'BE43",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA3"
              },
              {
                "instruction_address": 48805,
                "instruction_address_hex": "H'BEA5",
                "access": "write",
                "mnemonic": "AND.B",
                "instruction": "AND.B @H'FAA3, R0"
              },
              {
                "instruction_address": 48809,
                "instruction_address_hex": "H'BEA9",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B R0, @H'FAA3"
              },
              {
                "instruction_address": 48843,
                "instruction_address_hex": "H'BECB",
                "access": "read",
                "mnemonic": "BTST.B",
                "instruction": "BTST.B #7, @H'FAA3",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              }
            ],
            "evidence_addresses": [
              47770,
              47953,
              48227,
              48501,
              48592,
              48635,
              48707,
              48805,
              48809,
              48843
            ],
            "evidence_addresses_hex": [
              "H'BA9A",
              "H'BB51",
              "H'BC63",
              "H'BD75",
              "H'BDD0",
              "H'BDFB",
              "H'BE43",
              "H'BEA5",
              "H'BEA9",
              "H'BECB"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "serial_rx_error_or_retry_gate_candidate",
            "address": 64164,
            "address_hex": "H'FAA4",
            "access_count": 4,
            "read_count": 1,
            "write_count": 3,
            "bit_candidates": [
              7
            ],
            "immediate_values": [
              7
            ],
            "immediate_values_hex": [
              "H'0007"
            ],
            "accesses": [
              {
                "instruction_address": 47959,
                "instruction_address_hex": "H'BB57",
                "access": "write",
                "mnemonic": "BSET.B",
                "instruction": "BSET.B #7, @H'FAA4",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48004,
                "instruction_address_hex": "H'BB84",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA4"
              },
              {
                "instruction_address": 48079,
                "instruction_address_hex": "H'BBCF",
                "access": "read",
                "mnemonic": "BTST.B",
                "instruction": "BTST.B #7, @H'FAA4",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48681,
                "instruction_address_hex": "H'BE29",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #7, @H'FAA4",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              }
            ],
            "evidence_addresses": [
              47959,
              48004,
              48079,
              48681
            ],
            "evidence_addresses_hex": [
              "H'BB57",
              "H'BB84",
              "H'BBCF",
              "H'BE29"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "serial_retry_enable_or_mode_flags_candidate",
            "address": 64165,
            "address_hex": "H'FAA5",
            "access_count": 4,
            "read_count": 4,
            "write_count": 0,
            "bit_candidates": [
              7
            ],
            "immediate_values": [
              7
            ],
            "immediate_values_hex": [
              "H'0007"
            ],
            "accesses": [
              {
                "instruction_address": 16460,
                "instruction_address_hex": "H'404C",
                "access": "read",
                "mnemonic": "BTST.B",
                "instruction": "BTST.B #7, @H'FAA5",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 47754,
                "instruction_address_hex": "H'BA8A",
                "access": "read",
                "mnemonic": "BTST.B",
                "instruction": "BTST.B #7, @H'FAA5",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48685,
                "instruction_address_hex": "H'BE2D",
                "access": "read",
                "mnemonic": "BTST.B",
                "instruction": "BTST.B #7, @H'FAA5",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48798,
                "instruction_address_hex": "H'BE9E",
                "access": "read",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B @H'FAA5, R0"
              }
            ],
            "evidence_addresses": [
              16460,
              47754,
              48685,
              48798
            ],
            "evidence_addresses_hex": [
              "H'404C",
              "H'BA8A",
              "H'BE2D",
              "H'BE9E"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "serial_retry_counter_candidate",
            "address": 64166,
            "address_hex": "H'FAA6",
            "access_count": 3,
            "read_count": 1,
            "write_count": 2,
            "bit_candidates": [],
            "immediate_values": [
              1,
              2
            ],
            "immediate_values_hex": [
              "H'0001",
              "H'0002"
            ],
            "accesses": [
              {
                "instruction_address": 48115,
                "instruction_address_hex": "H'BBF3",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'FAA6"
              },
              {
                "instruction_address": 48691,
                "instruction_address_hex": "H'BE33",
                "access": "write",
                "mnemonic": "ADD:Q.B",
                "instruction": "ADD:Q.B #1, @H'FAA6",
                "immediate": 1,
                "immediate_hex": "H'01"
              },
              {
                "instruction_address": 48695,
                "instruction_address_hex": "H'BE37",
                "access": "read",
                "mnemonic": "CMP:G.B",
                "instruction": "CMP:G.B #H'02, @H'FAA6",
                "immediate": 2,
                "immediate_hex": "H'02"
              }
            ],
            "evidence_addresses": [
              48115,
              48691,
              48695
            ],
            "evidence_addresses_hex": [
              "H'BBF3",
              "H'BE33",
              "H'BE37"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "event_queue_read_cursor_candidate",
            "address": 63924,
            "address_hex": "H'F9B4",
            "access_count": 3,
            "read_count": 1,
            "write_count": 2,
            "bit_candidates": [
              5
            ],
            "immediate_values": [
              1,
              5
            ],
            "immediate_values_hex": [
              "H'0001",
              "H'0005"
            ],
            "accesses": [
              {
                "instruction_address": 48760,
                "instruction_address_hex": "H'BE78",
                "access": "read",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B @H'F9B4, R1"
              },
              {
                "instruction_address": 48789,
                "instruction_address_hex": "H'BE95",
                "access": "write",
                "mnemonic": "ADD:Q.B",
                "instruction": "ADD:Q.B #1, @H'F9B4",
                "immediate": 1,
                "immediate_hex": "H'01"
              },
              {
                "instruction_address": 48793,
                "instruction_address_hex": "H'BE99",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #5, @H'F9B4",
                "bit": 5,
                "immediate": 5,
                "immediate_hex": "H'05"
              }
            ],
            "evidence_addresses": [
              48760,
              48789,
              48793
            ],
            "evidence_addresses_hex": [
              "H'BE78",
              "H'BE95",
              "H'BE99"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "event_queue_write_or_pending_cursor_candidate",
            "address": 63925,
            "address_hex": "H'F9B5",
            "access_count": 8,
            "read_count": 2,
            "write_count": 6,
            "bit_candidates": [
              7
            ],
            "immediate_values": [
              1,
              7
            ],
            "immediate_values_hex": [
              "H'0001",
              "H'0007"
            ],
            "accesses": [
              {
                "instruction_address": 16479,
                "instruction_address_hex": "H'405F",
                "access": "read",
                "mnemonic": "CMP:G.B",
                "instruction": "CMP:G.B @H'F9B5, R2"
              },
              {
                "instruction_address": 47858,
                "instruction_address_hex": "H'BAF2",
                "access": "read",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B @H'F9B5, R1"
              },
              {
                "instruction_address": 48493,
                "instruction_address_hex": "H'BD6D",
                "access": "write",
                "mnemonic": "ADD:Q.B",
                "instruction": "ADD:Q.B #1, @H'F9B5",
                "immediate": 1,
                "immediate_hex": "H'01"
              },
              {
                "instruction_address": 48497,
                "instruction_address_hex": "H'BD71",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #7, @H'F9B5",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48584,
                "instruction_address_hex": "H'BDC8",
                "access": "write",
                "mnemonic": "ADD:Q.B",
                "instruction": "ADD:Q.B #1, @H'F9B5",
                "immediate": 1,
                "immediate_hex": "H'01"
              },
              {
                "instruction_address": 48588,
                "instruction_address_hex": "H'BDCC",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #7, @H'F9B5",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48627,
                "instruction_address_hex": "H'BDF3",
                "access": "write",
                "mnemonic": "ADD:Q.B",
                "instruction": "ADD:Q.B #1, @H'F9B5",
                "immediate": 1,
                "immediate_hex": "H'01"
              },
              {
                "instruction_address": 48631,
                "instruction_address_hex": "H'BDF7",
                "access": "write",
                "mnemonic": "BCLR.B",
                "instruction": "BCLR.B #7, @H'F9B5",
                "bit": 7,
                "immediate": 7,
                "immediate_hex": "H'07"
              }
            ],
            "evidence_addresses": [
              16479,
              47858,
              48493,
              48497,
              48584,
              48588,
              48627,
              48631
            ],
            "evidence_addresses_hex": [
              "H'405F",
              "H'BAF2",
              "H'BD6D",
              "H'BD71",
              "H'BDC8",
              "H'BDCC",
              "H'BDF3",
              "H'BDF7"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "event_queue_base_or_current_slot_candidate",
            "address": 63929,
            "address_hex": "H'F9B9",
            "access_count": 1,
            "read_count": 1,
            "write_count": 0,
            "bit_candidates": [],
            "immediate_values": [],
            "immediate_values_hex": [],
            "accesses": [
              {
                "instruction_address": 48752,
                "instruction_address_hex": "H'BE70",
                "access": "read",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B @H'F9B9, R3"
              }
            ],
            "evidence_addresses": [
              48752
            ],
            "evidence_addresses_hex": [
              "H'BE70"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "serial_tx_busy_timer_candidate",
            "address": 63936,
            "address_hex": "H'F9C0",
            "access_count": 10,
            "read_count": 2,
            "write_count": 8,
            "bit_candidates": [],
            "immediate_values": [
              100,
              31,
              9,
              240,
              65535
            ],
            "immediate_values_hex": [
              "H'0064",
              "H'001F",
              "H'0009",
              "H'00F0",
              "H'FFFF"
            ],
            "accesses": [
              {
                "instruction_address": 47654,
                "instruction_address_hex": "H'BA26",
                "access": "read",
                "mnemonic": "TST.B",
                "instruction": "TST.B @H'F9C0"
              },
              {
                "instruction_address": 47660,
                "instruction_address_hex": "H'BA2C",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'64, @H'F9C0",
                "immediate": 100,
                "immediate_hex": "H'64"
              },
              {
                "instruction_address": 47778,
                "instruction_address_hex": "H'BAA2",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'1F, @H'F9C0",
                "immediate": 31,
                "immediate_hex": "H'1F"
              },
              {
                "instruction_address": 47834,
                "instruction_address_hex": "H'BADA",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'09, @H'F9C0",
                "immediate": 9,
                "immediate_hex": "H'09"
              },
              {
                "instruction_address": 47841,
                "instruction_address_hex": "H'BAE1",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'09, @H'F9C0",
                "immediate": 9,
                "immediate_hex": "H'09"
              },
              {
                "instruction_address": 47848,
                "instruction_address_hex": "H'BAE8",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'F0, @H'F9C0",
                "immediate": 240,
                "immediate_hex": "H'F0"
              },
              {
                "instruction_address": 48669,
                "instruction_address_hex": "H'BE1D",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'1F, @H'F9C0",
                "immediate": 31,
                "immediate_hex": "H'1F"
              },
              {
                "instruction_address": 48702,
                "instruction_address_hex": "H'BE3E",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'1F, @H'F9C0",
                "immediate": 31,
                "immediate_hex": "H'1F"
              },
              {
                "instruction_address": 48878,
                "instruction_address_hex": "H'BEEE",
                "access": "read",
                "mnemonic": "TST.B",
                "instruction": "TST.B @H'F9C0"
              },
              {
                "instruction_address": 48884,
                "instruction_address_hex": "H'BEF4",
                "access": "write",
                "mnemonic": "ADD:Q.B",
                "instruction": "ADD:Q.B #-1, @H'F9C0",
                "immediate": 65535,
                "immediate_hex": "H'FFFF"
              }
            ],
            "evidence_addresses": [
              47654,
              47660,
              47778,
              47834,
              47841,
              47848,
              48669,
              48702,
              48878,
              48884
            ],
            "evidence_addresses_hex": [
              "H'BA26",
              "H'BA2C",
              "H'BAA2",
              "H'BADA",
              "H'BAE1",
              "H'BAE8",
              "H'BE1D",
              "H'BE3E",
              "H'BEEE",
              "H'BEF4"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "idle_heartbeat_gate_countdown_candidate",
            "address": 63940,
            "address_hex": "H'F9C4",
            "access_count": 5,
            "read_count": 2,
            "write_count": 3,
            "bit_candidates": [],
            "immediate_values": [
              20,
              7,
              65535
            ],
            "immediate_values_hex": [
              "H'0014",
              "H'0007",
              "H'FFFF"
            ],
            "accesses": [
              {
                "instruction_address": 16454,
                "instruction_address_hex": "H'4046",
                "access": "read",
                "mnemonic": "TST.B",
                "instruction": "TST.B @H'F9C4"
              },
              {
                "instruction_address": 16608,
                "instruction_address_hex": "H'40E0",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'14, @H'F9C4",
                "immediate": 20,
                "immediate_hex": "H'14"
              },
              {
                "instruction_address": 47665,
                "instruction_address_hex": "H'BA31",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'07, @H'F9C4",
                "immediate": 7,
                "immediate_hex": "H'07"
              },
              {
                "instruction_address": 48935,
                "instruction_address_hex": "H'BF27",
                "access": "read",
                "mnemonic": "TST.B",
                "instruction": "TST.B @H'F9C4"
              },
              {
                "instruction_address": 48941,
                "instruction_address_hex": "H'BF2D",
                "access": "write",
                "mnemonic": "ADD:Q.B",
                "instruction": "ADD:Q.B #-1, @H'F9C4",
                "immediate": 65535,
                "immediate_hex": "H'FFFF"
              }
            ],
            "evidence_addresses": [
              16454,
              16608,
              47665,
              48935,
              48941
            ],
            "evidence_addresses_hex": [
              "H'4046",
              "H'40E0",
              "H'BA31",
              "H'BF27",
              "H'BF2D"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "rx_session_timeout_candidate",
            "address": 63941,
            "address_hex": "H'F9C5",
            "access_count": 4,
            "read_count": 1,
            "write_count": 3,
            "bit_candidates": [],
            "immediate_values": [
              20,
              65535
            ],
            "immediate_values_hex": [
              "H'0014",
              "H'FFFF"
            ],
            "accesses": [
              {
                "instruction_address": 48030,
                "instruction_address_hex": "H'BB9E",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'14, @H'F9C5",
                "immediate": 20,
                "immediate_hex": "H'14"
              },
              {
                "instruction_address": 48868,
                "instruction_address_hex": "H'BEE4",
                "access": "write",
                "mnemonic": "CLR.B",
                "instruction": "CLR.B @H'F9C5"
              },
              {
                "instruction_address": 48945,
                "instruction_address_hex": "H'BF31",
                "access": "read",
                "mnemonic": "TST.B",
                "instruction": "TST.B @H'F9C5"
              },
              {
                "instruction_address": 48951,
                "instruction_address_hex": "H'BF37",
                "access": "write",
                "mnemonic": "ADD:Q.B",
                "instruction": "ADD:Q.B #-1, @H'F9C5",
                "immediate": 65535,
                "immediate_hex": "H'FFFF"
              }
            ],
            "evidence_addresses": [
              48030,
              48868,
              48945,
              48951
            ],
            "evidence_addresses_hex": [
              "H'BB9E",
              "H'BEE4",
              "H'BF31",
              "H'BF37"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "autonomous_report_period_timer_candidate",
            "address": 63942,
            "address_hex": "H'F9C6",
            "access_count": 5,
            "read_count": 2,
            "write_count": 3,
            "bit_candidates": [],
            "immediate_values": [
              500,
              65535
            ],
            "immediate_values_hex": [
              "H'01F4",
              "H'FFFF"
            ],
            "accesses": [
              {
                "instruction_address": 47942,
                "instruction_address_hex": "H'BB46",
                "access": "write",
                "mnemonic": "MOV:G.W",
                "instruction": "MOV:G.W #H'01F4, @H'F9C6",
                "immediate": 500,
                "immediate_hex": "H'01F4"
              },
              {
                "instruction_address": 48821,
                "instruction_address_hex": "H'BEB5",
                "access": "read",
                "mnemonic": "TST.W",
                "instruction": "TST.W @H'F9C6"
              },
              {
                "instruction_address": 48837,
                "instruction_address_hex": "H'BEC5",
                "access": "write",
                "mnemonic": "MOV:G.W",
                "instruction": "MOV:G.W #H'01F4, @H'F9C6",
                "immediate": 500,
                "immediate_hex": "H'01F4"
              },
              {
                "instruction_address": 48898,
                "instruction_address_hex": "H'BF02",
                "access": "read",
                "mnemonic": "TST.W",
                "instruction": "TST.W @H'F9C6"
              },
              {
                "instruction_address": 48904,
                "instruction_address_hex": "H'BF08",
                "access": "write",
                "mnemonic": "ADD:Q.W",
                "instruction": "ADD:Q.W #-1, @H'F9C6",
                "immediate": 65535,
                "immediate_hex": "H'FFFF"
              }
            ],
            "evidence_addresses": [
              47942,
              48821,
              48837,
              48898,
              48904
            ],
            "evidence_addresses_hex": [
              "H'BB46",
              "H'BEB5",
              "H'BEC5",
              "H'BF02",
              "H'BF08"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          },
          {
            "kind": "serial_state_variable_candidate",
            "name_candidate": "autonomous_report_resend_countdown_candidate",
            "address": 63944,
            "address_hex": "H'F9C8",
            "access_count": 3,
            "read_count": 1,
            "write_count": 2,
            "bit_candidates": [],
            "immediate_values": [
              20,
              65535
            ],
            "immediate_values_hex": [
              "H'0014",
              "H'FFFF"
            ],
            "accesses": [
              {
                "instruction_address": 47948,
                "instruction_address_hex": "H'BB4C",
                "access": "write",
                "mnemonic": "MOV:G.B",
                "instruction": "MOV:G.B #H'14, @H'F9C8",
                "immediate": 20,
                "immediate_hex": "H'14"
              },
              {
                "instruction_address": 48827,
                "instruction_address_hex": "H'BEBB",
                "access": "read",
                "mnemonic": "TST.B",
                "instruction": "TST.B @H'F9C8"
              },
              {
                "instruction_address": 48833,
                "instruction_address_hex": "H'BEC1",
                "access": "write",
                "mnemonic": "ADD:Q.B",
                "instruction": "ADD:Q.B #-1, @H'F9C8",
                "immediate": 65535,
                "immediate_hex": "H'FFFF"
              }
            ],
            "evidence_addresses": [
              47948,
              48827,
              48833
            ],
            "evidence_addresses_hex": [
              "H'BB4C",
              "H'BEBB",
              "H'BEC1"
            ],
            "confidence": "candidate-medium",
            "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
          }
        ],
        "send_builder": {
          "kind": "tx_send_builder_candidate",
          "label": "loc_BA26",
          "address": 47654,
          "address_hex": "H'BA26",
          "staging_buffer_start": 63568,
          "staging_buffer_start_hex": "H'F850",
          "staging_buffer_end": 63572,
          "staging_buffer_end_hex": "H'F854",
          "tx_frame_start": 63576,
          "tx_frame_start_hex": "H'F858",
          "tx_frame_end": 63581,
          "tx_frame_end_hex": "H'F85D",
          "checksum_address": 63581,
          "checksum_address_hex": "H'F85D",
          "checksum_seed": 90,
          "checksum_seed_hex": "H'005A",
          "staging_to_frame_copies": [],
          "response_call_addresses": [
            47939,
            48333,
            48378,
            48674,
            48746
          ],
          "response_call_addresses_hex": [
            "H'BB43",
            "H'BCCD",
            "H'BCFA",
            "H'BE22",
            "H'BE6A"
          ],
          "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate",
          "evidence_addresses": [
            47674,
            47682,
            47690,
            47696,
            47700,
            47704,
            47708,
            47712,
            47716,
            47726,
            47939,
            48333,
            48378,
            48674,
            48746
          ],
          "evidence_addresses_hex": [
            "H'BA3A",
            "H'BA42",
            "H'BA4A",
            "H'BA50",
            "H'BA54",
            "H'BA58",
            "H'BA5C",
            "H'BA60",
            "H'BA64",
            "H'BA6E",
            "H'BB43",
            "H'BCCD",
            "H'BCFA",
            "H'BE22",
            "H'BE6A"
          ],
          "confidence": "low",
          "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission."
        },
        "response_candidates": [
          {
            "id": "response_at_BB43",
            "kind": "response_staging_candidate",
            "call_address": 47939,
            "call_address_hex": "H'BB43",
            "send_builder": "loc_BA26",
            "send_builder_address": 47654,
            "send_builder_address_hex": "H'BA26",
            "window_start": 47872,
            "window_start_hex": "H'BB00",
            "writes": [
              {
                "instruction_address": 47900,
                "instruction_address_hex": "H'BB1C",
                "addresses": [
                  63568
                ],
                "addresses_hex": [
                  "H'F850"
                ],
                "source_operand": "R1",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R1",
                  "source_category": "computed",
                  "operation": "AND",
                  "evidence_address": 47897,
                  "evidence_address_hex": "H'BB19",
                  "instruction": "AND.B #H'07, R1"
                },
                "instruction": "MOV:G.B R1, @H'F850"
              },
              {
                "instruction_address": 47904,
                "instruction_address_hex": "H'BB20",
                "addresses": [
                  63570
                ],
                "addresses_hex": [
                  "H'F852"
                ],
                "source_operand": "R5",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "@(-H'0790,R0)",
                  "source_category": "computed",
                  "evidence_address": 47880,
                  "evidence_address_hex": "H'BB08",
                  "instruction": "MOV:G.W @(-H'0790,R0), R0"
                },
                "instruction": "MOV:G.B R5, @H'F852"
              },
              {
                "instruction_address": 47915,
                "instruction_address_hex": "H'BB2B",
                "addresses": [
                  63569
                ],
                "addresses_hex": [
                  "H'F851"
                ],
                "source_operand": "R5",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R5",
                  "source_category": "computed",
                  "operation": "OR",
                  "evidence_address": 47913,
                  "evidence_address_hex": "H'BB29",
                  "instruction": "OR.B R2, R5"
                },
                "instruction": "MOV:G.B R5, @H'F851"
              },
              {
                "instruction_address": 47929,
                "instruction_address_hex": "H'BB39",
                "addresses": [
                  63572
                ],
                "addresses_hex": [
                  "H'F854"
                ],
                "source_operand": "R4",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4"
                },
                "instruction": "MOV:G.B R4, @H'F854"
              },
              {
                "instruction_address": 47935,
                "instruction_address_hex": "H'BB3F",
                "addresses": [
                  63571
                ],
                "addresses_hex": [
                  "H'F853"
                ],
                "source_operand": "R4",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4",
                  "transforms": [
                    "swap_bytes"
                  ]
                },
                "instruction": "MOV:G.B R4, @H'F853"
              }
            ],
            "rx_reads": [],
            "evidence_addresses": [
              47900,
              47904,
              47915,
              47929,
              47935,
              47939
            ],
            "evidence_addresses_hex": [
              "H'BB1C",
              "H'BB20",
              "H'BB2B",
              "H'BB39",
              "H'BB3F",
              "H'BB43"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
            "schema": {
              "kind": "response_schema_candidate",
              "response_id": "response_at_BB43",
              "call_address": 47939,
              "call_address_hex": "H'BB43",
              "buffer_start": 63568,
              "buffer_start_hex": "H'F850",
              "buffer_end": 63572,
              "buffer_end_hex": "H'F854",
              "bytes": [
                {
                  "offset": 0,
                  "byte": "byte0",
                  "tx_byte": "TX[0]",
                  "tx_staging_byte": "TX[0]",
                  "address": 63568,
                  "address_hex": "H'F850",
                  "source_kind": "computed",
                  "source_expression": "computed",
                  "source": {
                    "kind": "register_or_computed",
                    "operand": "R1",
                    "source_category": "computed",
                    "operation": "AND",
                    "evidence_address": 47897,
                    "evidence_address_hex": "H'BB19",
                    "instruction": "AND.B #H'07, R1",
                    "byte_index": 0
                  },
                  "write_instruction_address": 47900,
                  "write_instruction_address_hex": "H'BB1C",
                  "instruction": "MOV:G.B R1, @H'F850",
                  "evidence_addresses": [
                    47900
                  ],
                  "evidence_addresses_hex": [
                    "H'BB1C"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 1,
                  "byte": "byte1",
                  "tx_byte": "TX[1]",
                  "tx_staging_byte": "TX[1]",
                  "address": 63569,
                  "address_hex": "H'F851",
                  "source_kind": "computed",
                  "source_expression": "computed",
                  "source": {
                    "kind": "register_or_computed",
                    "operand": "R5",
                    "source_category": "computed",
                    "operation": "OR",
                    "evidence_address": 47913,
                    "evidence_address_hex": "H'BB29",
                    "instruction": "OR.B R2, R5",
                    "byte_index": 0
                  },
                  "write_instruction_address": 47915,
                  "write_instruction_address_hex": "H'BB2B",
                  "instruction": "MOV:G.B R5, @H'F851",
                  "evidence_addresses": [
                    47915
                  ],
                  "evidence_addresses_hex": [
                    "H'BB2B"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 2,
                  "byte": "byte2",
                  "tx_byte": "TX[2]",
                  "tx_staging_byte": "TX[2]",
                  "address": 63570,
                  "address_hex": "H'F852",
                  "source_kind": "computed",
                  "source_expression": "computed",
                  "source": {
                    "kind": "register_or_computed",
                    "operand": "@(-H'0790,R0)",
                    "source_category": "computed",
                    "evidence_address": 47880,
                    "evidence_address_hex": "H'BB08",
                    "instruction": "MOV:G.W @(-H'0790,R0), R0",
                    "byte_index": 0
                  },
                  "write_instruction_address": 47904,
                  "write_instruction_address_hex": "H'BB20",
                  "instruction": "MOV:G.B R5, @H'F852",
                  "evidence_addresses": [
                    47904
                  ],
                  "evidence_addresses_hex": [
                    "H'BB20"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 3,
                  "byte": "byte3",
                  "tx_byte": "TX[3]",
                  "tx_staging_byte": "TX[3]",
                  "address": 63571,
                  "address_hex": "H'F853",
                  "source_kind": "table",
                  "source_expression": "current_value_table_candidate",
                  "source": {
                    "name_candidate": "current_value_table_candidate",
                    "element_candidate": "word_value",
                    "logical_base_address": 59392,
                    "logical_base_address_hex": "H'E800",
                    "negative_offset": 6144,
                    "negative_offset_hex": "H'1800",
                    "index_register": "R0",
                    "operand": "@(-H'1800,R0)",
                    "kind": "table",
                    "access_width": 2,
                    "evidence_address": 47925,
                    "evidence_address_hex": "H'BB35",
                    "instruction": "MOV:G.W @(-H'1800,R0), R4",
                    "transforms": [
                      "swap_bytes"
                    ],
                    "byte_index": 0
                  },
                  "write_instruction_address": 47935,
                  "write_instruction_address_hex": "H'BB3F",
                  "instruction": "MOV:G.B R4, @H'F853",
                  "evidence_addresses": [
                    47935
                  ],
                  "evidence_addresses_hex": [
                    "H'BB3F"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 4,
                  "byte": "byte4",
                  "tx_byte": "TX[4]",
                  "tx_staging_byte": "TX[4]",
                  "address": 63572,
                  "address_hex": "H'F854",
                  "source_kind": "table",
                  "source_expression": "current_value_table_candidate",
                  "source": {
                    "name_candidate": "current_value_table_candidate",
                    "element_candidate": "word_value",
                    "logical_base_address": 59392,
                    "logical_base_address_hex": "H'E800",
                    "negative_offset": 6144,
                    "negative_offset_hex": "H'1800",
                    "index_register": "R0",
                    "operand": "@(-H'1800,R0)",
                    "kind": "table",
                    "access_width": 2,
                    "evidence_address": 47925,
                    "evidence_address_hex": "H'BB35",
                    "instruction": "MOV:G.W @(-H'1800,R0), R4",
                    "byte_index": 0
                  },
                  "write_instruction_address": 47929,
                  "write_instruction_address_hex": "H'BB39",
                  "instruction": "MOV:G.B R4, @H'F854",
                  "evidence_addresses": [
                    47929
                  ],
                  "evidence_addresses_hex": [
                    "H'BB39"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                }
              ],
              "semantic_notes": [],
              "evidence_addresses": [
                47900,
                47915,
                47904,
                47935,
                47929
              ],
              "evidence_addresses_hex": [
                "H'BB1C",
                "H'BB2B",
                "H'BB20",
                "H'BB3F",
                "H'BB39"
              ],
              "confidence": "candidate-medium",
              "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
            },
            "byte_schema": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "computed",
                "source_expression": "computed",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R1",
                  "source_category": "computed",
                  "operation": "AND",
                  "evidence_address": 47897,
                  "evidence_address_hex": "H'BB19",
                  "instruction": "AND.B #H'07, R1",
                  "byte_index": 0
                },
                "write_instruction_address": 47900,
                "write_instruction_address_hex": "H'BB1C",
                "instruction": "MOV:G.B R1, @H'F850",
                "evidence_addresses": [
                  47900
                ],
                "evidence_addresses_hex": [
                  "H'BB1C"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "computed",
                "source_expression": "computed",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R5",
                  "source_category": "computed",
                  "operation": "OR",
                  "evidence_address": 47913,
                  "evidence_address_hex": "H'BB29",
                  "instruction": "OR.B R2, R5",
                  "byte_index": 0
                },
                "write_instruction_address": 47915,
                "write_instruction_address_hex": "H'BB2B",
                "instruction": "MOV:G.B R5, @H'F851",
                "evidence_addresses": [
                  47915
                ],
                "evidence_addresses_hex": [
                  "H'BB2B"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "computed",
                "source_expression": "computed",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "@(-H'0790,R0)",
                  "source_category": "computed",
                  "evidence_address": 47880,
                  "evidence_address_hex": "H'BB08",
                  "instruction": "MOV:G.W @(-H'0790,R0), R0",
                  "byte_index": 0
                },
                "write_instruction_address": 47904,
                "write_instruction_address_hex": "H'BB20",
                "instruction": "MOV:G.B R5, @H'F852",
                "evidence_addresses": [
                  47904
                ],
                "evidence_addresses_hex": [
                  "H'BB20"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "table",
                "source_expression": "current_value_table_candidate",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4",
                  "transforms": [
                    "swap_bytes"
                  ],
                  "byte_index": 0
                },
                "write_instruction_address": 47935,
                "write_instruction_address_hex": "H'BB3F",
                "instruction": "MOV:G.B R4, @H'F853",
                "evidence_addresses": [
                  47935
                ],
                "evidence_addresses_hex": [
                  "H'BB3F"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "table",
                "source_expression": "current_value_table_candidate",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4",
                  "byte_index": 0
                },
                "write_instruction_address": 47929,
                "write_instruction_address_hex": "H'BB39",
                "instruction": "MOV:G.B R4, @H'F854",
                "evidence_addresses": [
                  47929
                ],
                "evidence_addresses_hex": [
                  "H'BB39"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": []
          },
          {
            "id": "response_at_BCCD",
            "kind": "response_staging_candidate",
            "call_address": 48333,
            "call_address_hex": "H'BCCD",
            "send_builder": "loc_BA26",
            "send_builder_address": 47654,
            "send_builder_address_hex": "H'BA26",
            "window_start": 48297,
            "window_start_hex": "H'BCA9",
            "writes": [
              {
                "instruction_address": 48304,
                "instruction_address_hex": "H'BCB0",
                "addresses": [
                  63568
                ],
                "addresses_hex": [
                  "H'F850"
                ],
                "source_operand": "#H'04",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04"
                },
                "instruction": "MOV:G.B #H'04, @H'F850"
              },
              {
                "instruction_address": 48313,
                "instruction_address_hex": "H'BCB9",
                "addresses": [
                  63569
                ],
                "addresses_hex": [
                  "H'F851"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_offsets": [
                    1
                  ],
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "evidence_address": 48309,
                  "evidence_address_hex": "H'BCB5",
                  "instruction": "MOV:G.B @H'F861, R0"
                },
                "instruction": "MOV:G.B R0, @H'F851"
              },
              {
                "instruction_address": 48321,
                "instruction_address_hex": "H'BCC1",
                "addresses": [
                  63570,
                  63571
                ],
                "addresses_hex": [
                  "H'F852",
                  "H'F853"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48317,
                  "evidence_address_hex": "H'BCBD",
                  "instruction": "MOV:G.W @H'F862, R0"
                },
                "instruction": "MOV:G.W R0, @H'F852"
              },
              {
                "instruction_address": 48329,
                "instruction_address_hex": "H'BCC9",
                "addresses": [
                  63572
                ],
                "addresses_hex": [
                  "H'F854"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_offsets": [
                    4
                  ],
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "evidence_address": 48325,
                  "evidence_address_hex": "H'BCC5",
                  "instruction": "MOV:G.B @H'F864, R0"
                },
                "instruction": "MOV:G.B R0, @H'F854"
              }
            ],
            "rx_reads": [
              {
                "instruction_address": 48309,
                "instruction_address_hex": "H'BCB5",
                "rx_offset": 1,
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "instruction": "MOV:G.B @H'F861, R0"
              },
              {
                "instruction_address": 48317,
                "instruction_address_hex": "H'BCBD",
                "rx_offset": 2,
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "instruction": "MOV:G.W @H'F862, R0"
              },
              {
                "instruction_address": 48325,
                "instruction_address_hex": "H'BCC5",
                "rx_offset": 4,
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            ],
            "evidence_addresses": [
              48304,
              48313,
              48321,
              48329,
              48309,
              48317,
              48325,
              48333
            ],
            "evidence_addresses_hex": [
              "H'BCB0",
              "H'BCB9",
              "H'BCC1",
              "H'BCC9",
              "H'BCB5",
              "H'BCBD",
              "H'BCC5",
              "H'BCCD"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
            "schema": {
              "kind": "response_schema_candidate",
              "response_id": "response_at_BCCD",
              "call_address": 48333,
              "call_address_hex": "H'BCCD",
              "buffer_start": 63568,
              "buffer_start_hex": "H'F850",
              "buffer_end": 63572,
              "buffer_end_hex": "H'F854",
              "bytes": [
                {
                  "offset": 0,
                  "byte": "byte0",
                  "tx_byte": "TX[0]",
                  "tx_staging_byte": "TX[0]",
                  "address": 63568,
                  "address_hex": "H'F850",
                  "source_kind": "immediate",
                  "source_expression": "0x04",
                  "source": {
                    "kind": "immediate",
                    "value": 4,
                    "value_hex": "H'04",
                    "byte_index": 0
                  },
                  "write_instruction_address": 48304,
                  "write_instruction_address_hex": "H'BCB0",
                  "instruction": "MOV:G.B #H'04, @H'F850",
                  "evidence_addresses": [
                    48304
                  ],
                  "evidence_addresses_hex": [
                    "H'BCB0"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 1,
                  "byte": "byte1",
                  "tx_byte": "TX[1]",
                  "tx_staging_byte": "TX[1]",
                  "address": 63569,
                  "address_hex": "H'F851",
                  "source_kind": "rx_frame_byte",
                  "source_expression": "rx[1]",
                  "source": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 1,
                    "rx_address": 63585,
                    "rx_address_hex": "H'F861",
                    "derived_from": {
                      "kind": "rx_frame_byte",
                      "rx_offset": 1,
                      "rx_offsets": [
                        1
                      ],
                      "rx_address": 63585,
                      "rx_address_hex": "H'F861",
                      "evidence_address": 48309,
                      "evidence_address_hex": "H'BCB5",
                      "instruction": "MOV:G.B @H'F861, R0"
                    }
                  },
                  "write_instruction_address": 48313,
                  "write_instruction_address_hex": "H'BCB9",
                  "instruction": "MOV:G.B R0, @H'F851",
                  "evidence_addresses": [
                    48313
                  ],
                  "evidence_addresses_hex": [
                    "H'BCB9"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 2,
                  "byte": "byte2",
                  "tx_byte": "TX[2]",
                  "tx_staging_byte": "TX[2]",
                  "address": 63570,
                  "address_hex": "H'F852",
                  "source_kind": "rx_frame_byte",
                  "source_expression": "rx[2]",
                  "source": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 2,
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "derived_from": {
                      "kind": "rx_frame_word",
                      "rx_offset": 2,
                      "rx_offsets": [
                        2,
                        3
                      ],
                      "rx_address": 63586,
                      "rx_address_hex": "H'F862",
                      "evidence_address": 48317,
                      "evidence_address_hex": "H'BCBD",
                      "instruction": "MOV:G.W @H'F862, R0"
                    }
                  },
                  "write_instruction_address": 48321,
                  "write_instruction_address_hex": "H'BCC1",
                  "instruction": "MOV:G.W R0, @H'F852",
                  "evidence_addresses": [
                    48321
                  ],
                  "evidence_addresses_hex": [
                    "H'BCC1"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 3,
                  "byte": "byte3",
                  "tx_byte": "TX[3]",
                  "tx_staging_byte": "TX[3]",
                  "address": 63571,
                  "address_hex": "H'F853",
                  "source_kind": "rx_frame_byte",
                  "source_expression": "rx[3]",
                  "source": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 3,
                    "rx_address": 63587,
                    "rx_address_hex": "H'F863",
                    "derived_from": {
                      "kind": "rx_frame_word",
                      "rx_offset": 2,
                      "rx_offsets": [
                        2,
                        3
                      ],
                      "rx_address": 63586,
                      "rx_address_hex": "H'F862",
                      "evidence_address": 48317,
                      "evidence_address_hex": "H'BCBD",
                      "instruction": "MOV:G.W @H'F862, R0"
                    }
                  },
                  "write_instruction_address": 48321,
                  "write_instruction_address_hex": "H'BCC1",
                  "instruction": "MOV:G.W R0, @H'F852",
                  "evidence_addresses": [
                    48321
                  ],
                  "evidence_addresses_hex": [
                    "H'BCC1"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 4,
                  "byte": "byte4",
                  "tx_byte": "TX[4]",
                  "tx_staging_byte": "TX[4]",
                  "address": 63572,
                  "address_hex": "H'F854",
                  "source_kind": "rx_frame_byte",
                  "source_expression": "rx[4]",
                  "source": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 4,
                    "rx_address": 63588,
                    "rx_address_hex": "H'F864",
                    "derived_from": {
                      "kind": "rx_frame_byte",
                      "rx_offset": 4,
                      "rx_offsets": [
                        4
                      ],
                      "rx_address": 63588,
                      "rx_address_hex": "H'F864",
                      "evidence_address": 48325,
                      "evidence_address_hex": "H'BCC5",
                      "instruction": "MOV:G.B @H'F864, R0"
                    }
                  },
                  "write_instruction_address": 48329,
                  "write_instruction_address_hex": "H'BCC9",
                  "instruction": "MOV:G.B R0, @H'F854",
                  "evidence_addresses": [
                    48329
                  ],
                  "evidence_addresses_hex": [
                    "H'BCC9"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                }
              ],
              "semantic_notes": [],
              "evidence_addresses": [
                48304,
                48313,
                48321,
                48329
              ],
              "evidence_addresses_hex": [
                "H'BCB0",
                "H'BCB9",
                "H'BCC1",
                "H'BCC9"
              ],
              "confidence": "candidate-medium",
              "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
            },
            "byte_schema": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "immediate",
                "source_expression": "0x04",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04",
                  "byte_index": 0
                },
                "write_instruction_address": 48304,
                "write_instruction_address_hex": "H'BCB0",
                "instruction": "MOV:G.B #H'04, @H'F850",
                "evidence_addresses": [
                  48304
                ],
                "evidence_addresses_hex": [
                  "H'BCB0"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[1]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 1,
                    "rx_offsets": [
                      1
                    ],
                    "rx_address": 63585,
                    "rx_address_hex": "H'F861",
                    "evidence_address": 48309,
                    "evidence_address_hex": "H'BCB5",
                    "instruction": "MOV:G.B @H'F861, R0"
                  }
                },
                "write_instruction_address": 48313,
                "write_instruction_address_hex": "H'BCB9",
                "instruction": "MOV:G.B R0, @H'F851",
                "evidence_addresses": [
                  48313
                ],
                "evidence_addresses_hex": [
                  "H'BCB9"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[2]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48317,
                    "evidence_address_hex": "H'BCBD",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48321,
                "write_instruction_address_hex": "H'BCC1",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48321
                ],
                "evidence_addresses_hex": [
                  "H'BCC1"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[3]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 3,
                  "rx_address": 63587,
                  "rx_address_hex": "H'F863",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48317,
                    "evidence_address_hex": "H'BCBD",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48321,
                "write_instruction_address_hex": "H'BCC1",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48321
                ],
                "evidence_addresses_hex": [
                  "H'BCC1"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[4]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 4,
                    "rx_offsets": [
                      4
                    ],
                    "rx_address": 63588,
                    "rx_address_hex": "H'F864",
                    "evidence_address": 48325,
                    "evidence_address_hex": "H'BCC5",
                    "instruction": "MOV:G.B @H'F864, R0"
                  }
                },
                "write_instruction_address": 48329,
                "write_instruction_address_hex": "H'BCC9",
                "instruction": "MOV:G.B R0, @H'F854",
                "evidence_addresses": [
                  48329
                ],
                "evidence_addresses_hex": [
                  "H'BCC9"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": []
          },
          {
            "id": "response_at_BCFA",
            "kind": "response_staging_candidate",
            "call_address": 48378,
            "call_address_hex": "H'BCFA",
            "send_builder": "loc_BA26",
            "send_builder_address": 47654,
            "send_builder_address_hex": "H'BA26",
            "window_start": 48343,
            "window_start_hex": "H'BCD7",
            "writes": [
              {
                "instruction_address": 48343,
                "instruction_address_hex": "H'BCD7",
                "addresses": [
                  63568
                ],
                "addresses_hex": [
                  "H'F850"
                ],
                "source_operand": "#H'04",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04"
                },
                "instruction": "MOV:G.B #H'04, @H'F850"
              },
              {
                "instruction_address": 48352,
                "instruction_address_hex": "H'BCE0",
                "addresses": [
                  63569
                ],
                "addresses_hex": [
                  "H'F851"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_offsets": [
                    1
                  ],
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "evidence_address": 48348,
                  "evidence_address_hex": "H'BCDC",
                  "instruction": "MOV:G.B @H'F861, R0"
                },
                "instruction": "MOV:G.B R0, @H'F851"
              },
              {
                "instruction_address": 48360,
                "instruction_address_hex": "H'BCE8",
                "addresses": [
                  63569
                ],
                "addresses_hex": [
                  "H'F851"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48356,
                  "evidence_address_hex": "H'BCE4",
                  "instruction": "MOV:G.B @H'F862, R0"
                },
                "instruction": "MOV:G.B R0, @H'F851"
              },
              {
                "instruction_address": 48368,
                "instruction_address_hex": "H'BCF0",
                "addresses": [
                  63572
                ],
                "addresses_hex": [
                  "H'F854"
                ],
                "source_operand": "R0",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0"
                },
                "instruction": "MOV:G.B R0, @H'F854"
              },
              {
                "instruction_address": 48374,
                "instruction_address_hex": "H'BCF6",
                "addresses": [
                  63571
                ],
                "addresses_hex": [
                  "H'F853"
                ],
                "source_operand": "R0",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0",
                  "transforms": [
                    "swap_bytes"
                  ]
                },
                "instruction": "MOV:G.B R0, @H'F853"
              }
            ],
            "rx_reads": [
              {
                "instruction_address": 48348,
                "instruction_address_hex": "H'BCDC",
                "rx_offset": 1,
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "instruction": "MOV:G.B @H'F861, R0"
              },
              {
                "instruction_address": 48356,
                "instruction_address_hex": "H'BCE4",
                "rx_offset": 2,
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "instruction": "MOV:G.B @H'F862, R0"
              }
            ],
            "evidence_addresses": [
              48343,
              48352,
              48360,
              48368,
              48374,
              48348,
              48356,
              48378
            ],
            "evidence_addresses_hex": [
              "H'BCD7",
              "H'BCE0",
              "H'BCE8",
              "H'BCF0",
              "H'BCF6",
              "H'BCDC",
              "H'BCE4",
              "H'BCFA"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
            "schema": {
              "kind": "response_schema_candidate",
              "response_id": "response_at_BCFA",
              "call_address": 48378,
              "call_address_hex": "H'BCFA",
              "buffer_start": 63568,
              "buffer_start_hex": "H'F850",
              "buffer_end": 63572,
              "buffer_end_hex": "H'F854",
              "bytes": [
                {
                  "offset": 0,
                  "byte": "byte0",
                  "tx_byte": "TX[0]",
                  "tx_staging_byte": "TX[0]",
                  "address": 63568,
                  "address_hex": "H'F850",
                  "source_kind": "immediate",
                  "source_expression": "0x04",
                  "source": {
                    "kind": "immediate",
                    "value": 4,
                    "value_hex": "H'04",
                    "byte_index": 0
                  },
                  "write_instruction_address": 48343,
                  "write_instruction_address_hex": "H'BCD7",
                  "instruction": "MOV:G.B #H'04, @H'F850",
                  "evidence_addresses": [
                    48343
                  ],
                  "evidence_addresses_hex": [
                    "H'BCD7"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 1,
                  "byte": "byte1",
                  "tx_byte": "TX[1]",
                  "tx_staging_byte": "TX[1]",
                  "address": 63569,
                  "address_hex": "H'F851",
                  "source_kind": "rx_frame_byte",
                  "source_expression": "rx[2]",
                  "source": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 2,
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "derived_from": {
                      "kind": "rx_frame_byte",
                      "rx_offset": 2,
                      "rx_offsets": [
                        2
                      ],
                      "rx_address": 63586,
                      "rx_address_hex": "H'F862",
                      "evidence_address": 48356,
                      "evidence_address_hex": "H'BCE4",
                      "instruction": "MOV:G.B @H'F862, R0"
                    }
                  },
                  "write_instruction_address": 48360,
                  "write_instruction_address_hex": "H'BCE8",
                  "instruction": "MOV:G.B R0, @H'F851",
                  "evidence_addresses": [
                    48360
                  ],
                  "evidence_addresses_hex": [
                    "H'BCE8"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 2,
                  "byte": "byte2",
                  "tx_byte": "TX[2]",
                  "tx_staging_byte": "TX[2]",
                  "address": 63570,
                  "address_hex": "H'F852",
                  "source_kind": "stale_or_unchanged",
                  "source_expression": "stale/unchanged",
                  "source": {
                    "kind": "unknown"
                  },
                  "evidence_addresses": [],
                  "evidence_addresses_hex": [],
                  "confidence": "candidate-low",
                  "caveat": "BCD7 does not freshly write F852 before loc_BA26."
                },
                {
                  "offset": 3,
                  "byte": "byte3",
                  "tx_byte": "TX[3]",
                  "tx_staging_byte": "TX[3]",
                  "address": 63571,
                  "address_hex": "H'F853",
                  "source_kind": "table",
                  "source_expression": "primary_value_table_candidate",
                  "source": {
                    "name_candidate": "primary_value_table_candidate",
                    "element_candidate": "word_value",
                    "logical_base_address": 57344,
                    "logical_base_address_hex": "H'E000",
                    "negative_offset": 8192,
                    "negative_offset_hex": "H'2000",
                    "index_register": "R4",
                    "operand": "@(-H'2000,R4)",
                    "kind": "table",
                    "access_width": 2,
                    "evidence_address": 48364,
                    "evidence_address_hex": "H'BCEC",
                    "instruction": "MOV:G.W @(-H'2000,R4), R0",
                    "transforms": [
                      "swap_bytes"
                    ],
                    "byte_index": 0
                  },
                  "write_instruction_address": 48374,
                  "write_instruction_address_hex": "H'BCF6",
                  "instruction": "MOV:G.B R0, @H'F853",
                  "evidence_addresses": [
                    48374
                  ],
                  "evidence_addresses_hex": [
                    "H'BCF6"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 4,
                  "byte": "byte4",
                  "tx_byte": "TX[4]",
                  "tx_staging_byte": "TX[4]",
                  "address": 63572,
                  "address_hex": "H'F854",
                  "source_kind": "table",
                  "source_expression": "primary_value_table_candidate",
                  "source": {
                    "name_candidate": "primary_value_table_candidate",
                    "element_candidate": "word_value",
                    "logical_base_address": 57344,
                    "logical_base_address_hex": "H'E000",
                    "negative_offset": 8192,
                    "negative_offset_hex": "H'2000",
                    "index_register": "R4",
                    "operand": "@(-H'2000,R4)",
                    "kind": "table",
                    "access_width": 2,
                    "evidence_address": 48364,
                    "evidence_address_hex": "H'BCEC",
                    "instruction": "MOV:G.W @(-H'2000,R4), R0",
                    "byte_index": 0
                  },
                  "write_instruction_address": 48368,
                  "write_instruction_address_hex": "H'BCF0",
                  "instruction": "MOV:G.B R0, @H'F854",
                  "evidence_addresses": [
                    48368
                  ],
                  "evidence_addresses_hex": [
                    "H'BCF0"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                }
              ],
              "semantic_notes": [
                "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.",
                "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.",
                "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape."
              ],
              "evidence_addresses": [
                48343,
                48360,
                48374,
                48368
              ],
              "evidence_addresses_hex": [
                "H'BCD7",
                "H'BCE8",
                "H'BCF6",
                "H'BCF0"
              ],
              "confidence": "candidate-medium",
              "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
            },
            "byte_schema": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "immediate",
                "source_expression": "0x04",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04",
                  "byte_index": 0
                },
                "write_instruction_address": 48343,
                "write_instruction_address_hex": "H'BCD7",
                "instruction": "MOV:G.B #H'04, @H'F850",
                "evidence_addresses": [
                  48343
                ],
                "evidence_addresses_hex": [
                  "H'BCD7"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[2]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48356,
                    "evidence_address_hex": "H'BCE4",
                    "instruction": "MOV:G.B @H'F862, R0"
                  }
                },
                "write_instruction_address": 48360,
                "write_instruction_address_hex": "H'BCE8",
                "instruction": "MOV:G.B R0, @H'F851",
                "evidence_addresses": [
                  48360
                ],
                "evidence_addresses_hex": [
                  "H'BCE8"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "stale_or_unchanged",
                "source_expression": "stale/unchanged",
                "source": {
                  "kind": "unknown"
                },
                "evidence_addresses": [],
                "evidence_addresses_hex": [],
                "confidence": "candidate-low",
                "caveat": "BCD7 does not freshly write F852 before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "table",
                "source_expression": "primary_value_table_candidate",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0",
                  "transforms": [
                    "swap_bytes"
                  ],
                  "byte_index": 0
                },
                "write_instruction_address": 48374,
                "write_instruction_address_hex": "H'BCF6",
                "instruction": "MOV:G.B R0, @H'F853",
                "evidence_addresses": [
                  48374
                ],
                "evidence_addresses_hex": [
                  "H'BCF6"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "table",
                "source_expression": "primary_value_table_candidate",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0",
                  "byte_index": 0
                },
                "write_instruction_address": 48368,
                "write_instruction_address_hex": "H'BCF0",
                "instruction": "MOV:G.B R0, @H'F854",
                "evidence_addresses": [
                  48368
                ],
                "evidence_addresses_hex": [
                  "H'BCF0"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [
              "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.",
              "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.",
              "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape."
            ]
          },
          {
            "id": "response_at_BE22",
            "kind": "response_staging_candidate",
            "call_address": 48674,
            "call_address_hex": "H'BE22",
            "send_builder": "loc_BA26",
            "send_builder_address": 47654,
            "send_builder_address_hex": "H'BA26",
            "window_start": 48645,
            "window_start_hex": "H'BE05",
            "writes": [
              {
                "instruction_address": 48649,
                "instruction_address_hex": "H'BE09",
                "addresses": [
                  63568,
                  63569
                ],
                "addresses_hex": [
                  "H'F850",
                  "H'F851"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "tx_frame_word",
                  "tx_offset": 0,
                  "tx_offsets": [
                    0,
                    1
                  ],
                  "tx_address": 63576,
                  "tx_address_hex": "H'F858",
                  "evidence_address": 48645,
                  "evidence_address_hex": "H'BE05",
                  "instruction": "MOV:G.W @H'F858, R0"
                },
                "instruction": "MOV:G.W R0, @H'F850"
              },
              {
                "instruction_address": 48657,
                "instruction_address_hex": "H'BE11",
                "addresses": [
                  63570,
                  63571
                ],
                "addresses_hex": [
                  "H'F852",
                  "H'F853"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "tx_frame_word",
                  "tx_offset": 2,
                  "tx_offsets": [
                    2,
                    3
                  ],
                  "tx_address": 63578,
                  "tx_address_hex": "H'F85A",
                  "evidence_address": 48653,
                  "evidence_address_hex": "H'BE0D",
                  "instruction": "MOV:G.W @H'F85A, R0"
                },
                "instruction": "MOV:G.W R0, @H'F852"
              },
              {
                "instruction_address": 48665,
                "instruction_address_hex": "H'BE19",
                "addresses": [
                  63572
                ],
                "addresses_hex": [
                  "H'F854"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "tx_frame_word",
                  "tx_offset": 4,
                  "tx_offsets": [
                    4,
                    5
                  ],
                  "tx_address": 63580,
                  "tx_address_hex": "H'F85C",
                  "evidence_address": 48661,
                  "evidence_address_hex": "H'BE15",
                  "instruction": "MOV:G.W @H'F85C, R0"
                },
                "instruction": "MOV:G.W R0, @H'F854"
              }
            ],
            "rx_reads": [],
            "evidence_addresses": [
              48649,
              48657,
              48665,
              48674
            ],
            "evidence_addresses_hex": [
              "H'BE09",
              "H'BE11",
              "H'BE19",
              "H'BE22"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
            "schema": {
              "kind": "response_schema_candidate",
              "response_id": "response_at_BE22",
              "call_address": 48674,
              "call_address_hex": "H'BE22",
              "buffer_start": 63568,
              "buffer_start_hex": "H'F850",
              "buffer_end": 63572,
              "buffer_end_hex": "H'F854",
              "bytes": [
                {
                  "offset": 0,
                  "byte": "byte0",
                  "tx_byte": "TX[0]",
                  "tx_staging_byte": "TX[0]",
                  "address": 63568,
                  "address_hex": "H'F850",
                  "source_kind": "tx_frame_byte",
                  "source_expression": "tx[0]",
                  "source": {
                    "kind": "tx_frame_byte",
                    "tx_offset": 0,
                    "tx_address": 63576,
                    "tx_address_hex": "H'F858",
                    "derived_from": {
                      "kind": "tx_frame_word",
                      "tx_offset": 0,
                      "tx_offsets": [
                        0,
                        1
                      ],
                      "tx_address": 63576,
                      "tx_address_hex": "H'F858",
                      "evidence_address": 48645,
                      "evidence_address_hex": "H'BE05",
                      "instruction": "MOV:G.W @H'F858, R0"
                    }
                  },
                  "write_instruction_address": 48649,
                  "write_instruction_address_hex": "H'BE09",
                  "instruction": "MOV:G.W R0, @H'F850",
                  "evidence_addresses": [
                    48649
                  ],
                  "evidence_addresses_hex": [
                    "H'BE09"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 1,
                  "byte": "byte1",
                  "tx_byte": "TX[1]",
                  "tx_staging_byte": "TX[1]",
                  "address": 63569,
                  "address_hex": "H'F851",
                  "source_kind": "tx_frame_byte",
                  "source_expression": "tx[1]",
                  "source": {
                    "kind": "tx_frame_byte",
                    "tx_offset": 1,
                    "tx_address": 63577,
                    "tx_address_hex": "H'F859",
                    "derived_from": {
                      "kind": "tx_frame_word",
                      "tx_offset": 0,
                      "tx_offsets": [
                        0,
                        1
                      ],
                      "tx_address": 63576,
                      "tx_address_hex": "H'F858",
                      "evidence_address": 48645,
                      "evidence_address_hex": "H'BE05",
                      "instruction": "MOV:G.W @H'F858, R0"
                    }
                  },
                  "write_instruction_address": 48649,
                  "write_instruction_address_hex": "H'BE09",
                  "instruction": "MOV:G.W R0, @H'F850",
                  "evidence_addresses": [
                    48649
                  ],
                  "evidence_addresses_hex": [
                    "H'BE09"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 2,
                  "byte": "byte2",
                  "tx_byte": "TX[2]",
                  "tx_staging_byte": "TX[2]",
                  "address": 63570,
                  "address_hex": "H'F852",
                  "source_kind": "tx_frame_byte",
                  "source_expression": "tx[2]",
                  "source": {
                    "kind": "tx_frame_byte",
                    "tx_offset": 2,
                    "tx_address": 63578,
                    "tx_address_hex": "H'F85A",
                    "derived_from": {
                      "kind": "tx_frame_word",
                      "tx_offset": 2,
                      "tx_offsets": [
                        2,
                        3
                      ],
                      "tx_address": 63578,
                      "tx_address_hex": "H'F85A",
                      "evidence_address": 48653,
                      "evidence_address_hex": "H'BE0D",
                      "instruction": "MOV:G.W @H'F85A, R0"
                    }
                  },
                  "write_instruction_address": 48657,
                  "write_instruction_address_hex": "H'BE11",
                  "instruction": "MOV:G.W R0, @H'F852",
                  "evidence_addresses": [
                    48657
                  ],
                  "evidence_addresses_hex": [
                    "H'BE11"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 3,
                  "byte": "byte3",
                  "tx_byte": "TX[3]",
                  "tx_staging_byte": "TX[3]",
                  "address": 63571,
                  "address_hex": "H'F853",
                  "source_kind": "tx_frame_byte",
                  "source_expression": "tx[3]",
                  "source": {
                    "kind": "tx_frame_byte",
                    "tx_offset": 3,
                    "tx_address": 63579,
                    "tx_address_hex": "H'F85B",
                    "derived_from": {
                      "kind": "tx_frame_word",
                      "tx_offset": 2,
                      "tx_offsets": [
                        2,
                        3
                      ],
                      "tx_address": 63578,
                      "tx_address_hex": "H'F85A",
                      "evidence_address": 48653,
                      "evidence_address_hex": "H'BE0D",
                      "instruction": "MOV:G.W @H'F85A, R0"
                    }
                  },
                  "write_instruction_address": 48657,
                  "write_instruction_address_hex": "H'BE11",
                  "instruction": "MOV:G.W R0, @H'F852",
                  "evidence_addresses": [
                    48657
                  ],
                  "evidence_addresses_hex": [
                    "H'BE11"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 4,
                  "byte": "byte4",
                  "tx_byte": "TX[4]",
                  "tx_staging_byte": "TX[4]",
                  "address": 63572,
                  "address_hex": "H'F854",
                  "source_kind": "tx_frame_byte",
                  "source_expression": "tx[4]",
                  "source": {
                    "kind": "tx_frame_byte",
                    "tx_offset": 4,
                    "tx_address": 63580,
                    "tx_address_hex": "H'F85C",
                    "derived_from": {
                      "kind": "tx_frame_word",
                      "tx_offset": 4,
                      "tx_offsets": [
                        4,
                        5
                      ],
                      "tx_address": 63580,
                      "tx_address_hex": "H'F85C",
                      "evidence_address": 48661,
                      "evidence_address_hex": "H'BE15",
                      "instruction": "MOV:G.W @H'F85C, R0"
                    }
                  },
                  "write_instruction_address": 48665,
                  "write_instruction_address_hex": "H'BE19",
                  "instruction": "MOV:G.W R0, @H'F854",
                  "evidence_addresses": [
                    48665
                  ],
                  "evidence_addresses_hex": [
                    "H'BE19"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                }
              ],
              "semantic_notes": [],
              "evidence_addresses": [
                48649,
                48657,
                48665
              ],
              "evidence_addresses_hex": [
                "H'BE09",
                "H'BE11",
                "H'BE19"
              ],
              "confidence": "candidate-medium",
              "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
            },
            "byte_schema": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[0]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 0,
                  "tx_address": 63576,
                  "tx_address_hex": "H'F858",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 0,
                    "tx_offsets": [
                      0,
                      1
                    ],
                    "tx_address": 63576,
                    "tx_address_hex": "H'F858",
                    "evidence_address": 48645,
                    "evidence_address_hex": "H'BE05",
                    "instruction": "MOV:G.W @H'F858, R0"
                  }
                },
                "write_instruction_address": 48649,
                "write_instruction_address_hex": "H'BE09",
                "instruction": "MOV:G.W R0, @H'F850",
                "evidence_addresses": [
                  48649
                ],
                "evidence_addresses_hex": [
                  "H'BE09"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[1]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 1,
                  "tx_address": 63577,
                  "tx_address_hex": "H'F859",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 0,
                    "tx_offsets": [
                      0,
                      1
                    ],
                    "tx_address": 63576,
                    "tx_address_hex": "H'F858",
                    "evidence_address": 48645,
                    "evidence_address_hex": "H'BE05",
                    "instruction": "MOV:G.W @H'F858, R0"
                  }
                },
                "write_instruction_address": 48649,
                "write_instruction_address_hex": "H'BE09",
                "instruction": "MOV:G.W R0, @H'F850",
                "evidence_addresses": [
                  48649
                ],
                "evidence_addresses_hex": [
                  "H'BE09"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[2]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 2,
                  "tx_address": 63578,
                  "tx_address_hex": "H'F85A",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 2,
                    "tx_offsets": [
                      2,
                      3
                    ],
                    "tx_address": 63578,
                    "tx_address_hex": "H'F85A",
                    "evidence_address": 48653,
                    "evidence_address_hex": "H'BE0D",
                    "instruction": "MOV:G.W @H'F85A, R0"
                  }
                },
                "write_instruction_address": 48657,
                "write_instruction_address_hex": "H'BE11",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48657
                ],
                "evidence_addresses_hex": [
                  "H'BE11"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[3]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 3,
                  "tx_address": 63579,
                  "tx_address_hex": "H'F85B",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 2,
                    "tx_offsets": [
                      2,
                      3
                    ],
                    "tx_address": 63578,
                    "tx_address_hex": "H'F85A",
                    "evidence_address": 48653,
                    "evidence_address_hex": "H'BE0D",
                    "instruction": "MOV:G.W @H'F85A, R0"
                  }
                },
                "write_instruction_address": 48657,
                "write_instruction_address_hex": "H'BE11",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48657
                ],
                "evidence_addresses_hex": [
                  "H'BE11"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[4]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 4,
                  "tx_address": 63580,
                  "tx_address_hex": "H'F85C",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 4,
                    "tx_offsets": [
                      4,
                      5
                    ],
                    "tx_address": 63580,
                    "tx_address_hex": "H'F85C",
                    "evidence_address": 48661,
                    "evidence_address_hex": "H'BE15",
                    "instruction": "MOV:G.W @H'F85C, R0"
                  }
                },
                "write_instruction_address": 48665,
                "write_instruction_address_hex": "H'BE19",
                "instruction": "MOV:G.W R0, @H'F854",
                "evidence_addresses": [
                  48665
                ],
                "evidence_addresses_hex": [
                  "H'BE19"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": []
          },
          {
            "id": "response_at_BE6A",
            "kind": "response_staging_candidate",
            "call_address": 48746,
            "call_address_hex": "H'BE6A",
            "send_builder": "loc_BA26",
            "send_builder_address": 47654,
            "send_builder_address_hex": "H'BA26",
            "window_start": 48717,
            "window_start_hex": "H'BE4D",
            "writes": [
              {
                "instruction_address": 48717,
                "instruction_address_hex": "H'BE4D",
                "addresses": [
                  63568
                ],
                "addresses_hex": [
                  "H'F850"
                ],
                "source_operand": "#H'07",
                "source": {
                  "kind": "immediate",
                  "value": 7,
                  "value_hex": "H'07"
                },
                "instruction": "MOV:G.B #H'07, @H'F850"
              },
              {
                "instruction_address": 48726,
                "instruction_address_hex": "H'BE56",
                "addresses": [
                  63569
                ],
                "addresses_hex": [
                  "H'F851"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_offsets": [
                    1
                  ],
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "evidence_address": 48722,
                  "evidence_address_hex": "H'BE52",
                  "instruction": "MOV:G.B @H'F861, R0"
                },
                "instruction": "MOV:G.B R0, @H'F851"
              },
              {
                "instruction_address": 48734,
                "instruction_address_hex": "H'BE5E",
                "addresses": [
                  63570,
                  63571
                ],
                "addresses_hex": [
                  "H'F852",
                  "H'F853"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48730,
                  "evidence_address_hex": "H'BE5A",
                  "instruction": "MOV:G.W @H'F862, R0"
                },
                "instruction": "MOV:G.W R0, @H'F852"
              },
              {
                "instruction_address": 48742,
                "instruction_address_hex": "H'BE66",
                "addresses": [
                  63572
                ],
                "addresses_hex": [
                  "H'F854"
                ],
                "source_operand": "R0",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_offsets": [
                    4
                  ],
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "evidence_address": 48738,
                  "evidence_address_hex": "H'BE62",
                  "instruction": "MOV:G.B @H'F864, R0"
                },
                "instruction": "MOV:G.B R0, @H'F854"
              }
            ],
            "rx_reads": [
              {
                "instruction_address": 48722,
                "instruction_address_hex": "H'BE52",
                "rx_offset": 1,
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "instruction": "MOV:G.B @H'F861, R0"
              },
              {
                "instruction_address": 48730,
                "instruction_address_hex": "H'BE5A",
                "rx_offset": 2,
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "instruction": "MOV:G.W @H'F862, R0"
              },
              {
                "instruction_address": 48738,
                "instruction_address_hex": "H'BE62",
                "rx_offset": 4,
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            ],
            "evidence_addresses": [
              48717,
              48726,
              48734,
              48742,
              48722,
              48730,
              48738,
              48746
            ],
            "evidence_addresses_hex": [
              "H'BE4D",
              "H'BE56",
              "H'BE5E",
              "H'BE66",
              "H'BE52",
              "H'BE5A",
              "H'BE62",
              "H'BE6A"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
            "schema": {
              "kind": "response_schema_candidate",
              "response_id": "response_at_BE6A",
              "call_address": 48746,
              "call_address_hex": "H'BE6A",
              "buffer_start": 63568,
              "buffer_start_hex": "H'F850",
              "buffer_end": 63572,
              "buffer_end_hex": "H'F854",
              "bytes": [
                {
                  "offset": 0,
                  "byte": "byte0",
                  "tx_byte": "TX[0]",
                  "tx_staging_byte": "TX[0]",
                  "address": 63568,
                  "address_hex": "H'F850",
                  "source_kind": "immediate",
                  "source_expression": "0x07",
                  "source": {
                    "kind": "immediate",
                    "value": 7,
                    "value_hex": "H'07",
                    "byte_index": 0
                  },
                  "write_instruction_address": 48717,
                  "write_instruction_address_hex": "H'BE4D",
                  "instruction": "MOV:G.B #H'07, @H'F850",
                  "evidence_addresses": [
                    48717
                  ],
                  "evidence_addresses_hex": [
                    "H'BE4D"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 1,
                  "byte": "byte1",
                  "tx_byte": "TX[1]",
                  "tx_staging_byte": "TX[1]",
                  "address": 63569,
                  "address_hex": "H'F851",
                  "source_kind": "rx_frame_byte",
                  "source_expression": "rx[1]",
                  "source": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 1,
                    "rx_address": 63585,
                    "rx_address_hex": "H'F861",
                    "derived_from": {
                      "kind": "rx_frame_byte",
                      "rx_offset": 1,
                      "rx_offsets": [
                        1
                      ],
                      "rx_address": 63585,
                      "rx_address_hex": "H'F861",
                      "evidence_address": 48722,
                      "evidence_address_hex": "H'BE52",
                      "instruction": "MOV:G.B @H'F861, R0"
                    }
                  },
                  "write_instruction_address": 48726,
                  "write_instruction_address_hex": "H'BE56",
                  "instruction": "MOV:G.B R0, @H'F851",
                  "evidence_addresses": [
                    48726
                  ],
                  "evidence_addresses_hex": [
                    "H'BE56"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 2,
                  "byte": "byte2",
                  "tx_byte": "TX[2]",
                  "tx_staging_byte": "TX[2]",
                  "address": 63570,
                  "address_hex": "H'F852",
                  "source_kind": "rx_frame_byte",
                  "source_expression": "rx[2]",
                  "source": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 2,
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "derived_from": {
                      "kind": "rx_frame_word",
                      "rx_offset": 2,
                      "rx_offsets": [
                        2,
                        3
                      ],
                      "rx_address": 63586,
                      "rx_address_hex": "H'F862",
                      "evidence_address": 48730,
                      "evidence_address_hex": "H'BE5A",
                      "instruction": "MOV:G.W @H'F862, R0"
                    }
                  },
                  "write_instruction_address": 48734,
                  "write_instruction_address_hex": "H'BE5E",
                  "instruction": "MOV:G.W R0, @H'F852",
                  "evidence_addresses": [
                    48734
                  ],
                  "evidence_addresses_hex": [
                    "H'BE5E"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 3,
                  "byte": "byte3",
                  "tx_byte": "TX[3]",
                  "tx_staging_byte": "TX[3]",
                  "address": 63571,
                  "address_hex": "H'F853",
                  "source_kind": "rx_frame_byte",
                  "source_expression": "rx[3]",
                  "source": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 3,
                    "rx_address": 63587,
                    "rx_address_hex": "H'F863",
                    "derived_from": {
                      "kind": "rx_frame_word",
                      "rx_offset": 2,
                      "rx_offsets": [
                        2,
                        3
                      ],
                      "rx_address": 63586,
                      "rx_address_hex": "H'F862",
                      "evidence_address": 48730,
                      "evidence_address_hex": "H'BE5A",
                      "instruction": "MOV:G.W @H'F862, R0"
                    }
                  },
                  "write_instruction_address": 48734,
                  "write_instruction_address_hex": "H'BE5E",
                  "instruction": "MOV:G.W R0, @H'F852",
                  "evidence_addresses": [
                    48734
                  ],
                  "evidence_addresses_hex": [
                    "H'BE5E"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                },
                {
                  "offset": 4,
                  "byte": "byte4",
                  "tx_byte": "TX[4]",
                  "tx_staging_byte": "TX[4]",
                  "address": 63572,
                  "address_hex": "H'F854",
                  "source_kind": "rx_frame_byte",
                  "source_expression": "rx[4]",
                  "source": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 4,
                    "rx_address": 63588,
                    "rx_address_hex": "H'F864",
                    "derived_from": {
                      "kind": "rx_frame_byte",
                      "rx_offset": 4,
                      "rx_offsets": [
                        4
                      ],
                      "rx_address": 63588,
                      "rx_address_hex": "H'F864",
                      "evidence_address": 48738,
                      "evidence_address_hex": "H'BE62",
                      "instruction": "MOV:G.B @H'F864, R0"
                    }
                  },
                  "write_instruction_address": 48742,
                  "write_instruction_address_hex": "H'BE66",
                  "instruction": "MOV:G.B R0, @H'F854",
                  "evidence_addresses": [
                    48742
                  ],
                  "evidence_addresses_hex": [
                    "H'BE66"
                  ],
                  "confidence": "candidate-medium",
                  "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
                }
              ],
              "semantic_notes": [
                "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.",
                "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value."
              ],
              "evidence_addresses": [
                48717,
                48726,
                48734,
                48742
              ],
              "evidence_addresses_hex": [
                "H'BE4D",
                "H'BE56",
                "H'BE5E",
                "H'BE66"
              ],
              "confidence": "candidate-medium",
              "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
            },
            "byte_schema": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "immediate",
                "source_expression": "0x07",
                "source": {
                  "kind": "immediate",
                  "value": 7,
                  "value_hex": "H'07",
                  "byte_index": 0
                },
                "write_instruction_address": 48717,
                "write_instruction_address_hex": "H'BE4D",
                "instruction": "MOV:G.B #H'07, @H'F850",
                "evidence_addresses": [
                  48717
                ],
                "evidence_addresses_hex": [
                  "H'BE4D"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[1]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 1,
                    "rx_offsets": [
                      1
                    ],
                    "rx_address": 63585,
                    "rx_address_hex": "H'F861",
                    "evidence_address": 48722,
                    "evidence_address_hex": "H'BE52",
                    "instruction": "MOV:G.B @H'F861, R0"
                  }
                },
                "write_instruction_address": 48726,
                "write_instruction_address_hex": "H'BE56",
                "instruction": "MOV:G.B R0, @H'F851",
                "evidence_addresses": [
                  48726
                ],
                "evidence_addresses_hex": [
                  "H'BE56"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[2]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48730,
                    "evidence_address_hex": "H'BE5A",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48734,
                "write_instruction_address_hex": "H'BE5E",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48734
                ],
                "evidence_addresses_hex": [
                  "H'BE5E"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[3]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 3,
                  "rx_address": 63587,
                  "rx_address_hex": "H'F863",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48730,
                    "evidence_address_hex": "H'BE5A",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48734,
                "write_instruction_address_hex": "H'BE5E",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48734
                ],
                "evidence_addresses_hex": [
                  "H'BE5E"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[4]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 4,
                    "rx_offsets": [
                      4
                    ],
                    "rx_address": 63588,
                    "rx_address_hex": "H'F864",
                    "evidence_address": 48738,
                    "evidence_address_hex": "H'BE62",
                    "instruction": "MOV:G.B @H'F864, R0"
                  }
                },
                "write_instruction_address": 48742,
                "write_instruction_address_hex": "H'BE66",
                "instruction": "MOV:G.B R0, @H'F854",
                "evidence_addresses": [
                  48742
                ],
                "evidence_addresses_hex": [
                  "H'BE66"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [
              "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.",
              "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value."
            ]
          }
        ],
        "response_schemas": [
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BB43",
            "call_address": 47939,
            "call_address_hex": "H'BB43",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "computed",
                "source_expression": "computed",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R1",
                  "source_category": "computed",
                  "operation": "AND",
                  "evidence_address": 47897,
                  "evidence_address_hex": "H'BB19",
                  "instruction": "AND.B #H'07, R1",
                  "byte_index": 0
                },
                "write_instruction_address": 47900,
                "write_instruction_address_hex": "H'BB1C",
                "instruction": "MOV:G.B R1, @H'F850",
                "evidence_addresses": [
                  47900
                ],
                "evidence_addresses_hex": [
                  "H'BB1C"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "computed",
                "source_expression": "computed",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R5",
                  "source_category": "computed",
                  "operation": "OR",
                  "evidence_address": 47913,
                  "evidence_address_hex": "H'BB29",
                  "instruction": "OR.B R2, R5",
                  "byte_index": 0
                },
                "write_instruction_address": 47915,
                "write_instruction_address_hex": "H'BB2B",
                "instruction": "MOV:G.B R5, @H'F851",
                "evidence_addresses": [
                  47915
                ],
                "evidence_addresses_hex": [
                  "H'BB2B"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "computed",
                "source_expression": "computed",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "@(-H'0790,R0)",
                  "source_category": "computed",
                  "evidence_address": 47880,
                  "evidence_address_hex": "H'BB08",
                  "instruction": "MOV:G.W @(-H'0790,R0), R0",
                  "byte_index": 0
                },
                "write_instruction_address": 47904,
                "write_instruction_address_hex": "H'BB20",
                "instruction": "MOV:G.B R5, @H'F852",
                "evidence_addresses": [
                  47904
                ],
                "evidence_addresses_hex": [
                  "H'BB20"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "table",
                "source_expression": "current_value_table_candidate",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4",
                  "transforms": [
                    "swap_bytes"
                  ],
                  "byte_index": 0
                },
                "write_instruction_address": 47935,
                "write_instruction_address_hex": "H'BB3F",
                "instruction": "MOV:G.B R4, @H'F853",
                "evidence_addresses": [
                  47935
                ],
                "evidence_addresses_hex": [
                  "H'BB3F"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "table",
                "source_expression": "current_value_table_candidate",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4",
                  "byte_index": 0
                },
                "write_instruction_address": 47929,
                "write_instruction_address_hex": "H'BB39",
                "instruction": "MOV:G.B R4, @H'F854",
                "evidence_addresses": [
                  47929
                ],
                "evidence_addresses_hex": [
                  "H'BB39"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [],
            "evidence_addresses": [
              47900,
              47915,
              47904,
              47935,
              47929
            ],
            "evidence_addresses_hex": [
              "H'BB1C",
              "H'BB2B",
              "H'BB20",
              "H'BB3F",
              "H'BB39"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          },
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BCCD",
            "call_address": 48333,
            "call_address_hex": "H'BCCD",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "immediate",
                "source_expression": "0x04",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04",
                  "byte_index": 0
                },
                "write_instruction_address": 48304,
                "write_instruction_address_hex": "H'BCB0",
                "instruction": "MOV:G.B #H'04, @H'F850",
                "evidence_addresses": [
                  48304
                ],
                "evidence_addresses_hex": [
                  "H'BCB0"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[1]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 1,
                    "rx_offsets": [
                      1
                    ],
                    "rx_address": 63585,
                    "rx_address_hex": "H'F861",
                    "evidence_address": 48309,
                    "evidence_address_hex": "H'BCB5",
                    "instruction": "MOV:G.B @H'F861, R0"
                  }
                },
                "write_instruction_address": 48313,
                "write_instruction_address_hex": "H'BCB9",
                "instruction": "MOV:G.B R0, @H'F851",
                "evidence_addresses": [
                  48313
                ],
                "evidence_addresses_hex": [
                  "H'BCB9"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[2]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48317,
                    "evidence_address_hex": "H'BCBD",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48321,
                "write_instruction_address_hex": "H'BCC1",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48321
                ],
                "evidence_addresses_hex": [
                  "H'BCC1"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[3]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 3,
                  "rx_address": 63587,
                  "rx_address_hex": "H'F863",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48317,
                    "evidence_address_hex": "H'BCBD",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48321,
                "write_instruction_address_hex": "H'BCC1",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48321
                ],
                "evidence_addresses_hex": [
                  "H'BCC1"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[4]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 4,
                    "rx_offsets": [
                      4
                    ],
                    "rx_address": 63588,
                    "rx_address_hex": "H'F864",
                    "evidence_address": 48325,
                    "evidence_address_hex": "H'BCC5",
                    "instruction": "MOV:G.B @H'F864, R0"
                  }
                },
                "write_instruction_address": 48329,
                "write_instruction_address_hex": "H'BCC9",
                "instruction": "MOV:G.B R0, @H'F854",
                "evidence_addresses": [
                  48329
                ],
                "evidence_addresses_hex": [
                  "H'BCC9"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [],
            "evidence_addresses": [
              48304,
              48313,
              48321,
              48329
            ],
            "evidence_addresses_hex": [
              "H'BCB0",
              "H'BCB9",
              "H'BCC1",
              "H'BCC9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          },
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BCFA",
            "call_address": 48378,
            "call_address_hex": "H'BCFA",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "immediate",
                "source_expression": "0x04",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04",
                  "byte_index": 0
                },
                "write_instruction_address": 48343,
                "write_instruction_address_hex": "H'BCD7",
                "instruction": "MOV:G.B #H'04, @H'F850",
                "evidence_addresses": [
                  48343
                ],
                "evidence_addresses_hex": [
                  "H'BCD7"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[2]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48356,
                    "evidence_address_hex": "H'BCE4",
                    "instruction": "MOV:G.B @H'F862, R0"
                  }
                },
                "write_instruction_address": 48360,
                "write_instruction_address_hex": "H'BCE8",
                "instruction": "MOV:G.B R0, @H'F851",
                "evidence_addresses": [
                  48360
                ],
                "evidence_addresses_hex": [
                  "H'BCE8"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "stale_or_unchanged",
                "source_expression": "stale/unchanged",
                "source": {
                  "kind": "unknown"
                },
                "evidence_addresses": [],
                "evidence_addresses_hex": [],
                "confidence": "candidate-low",
                "caveat": "BCD7 does not freshly write F852 before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "table",
                "source_expression": "primary_value_table_candidate",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0",
                  "transforms": [
                    "swap_bytes"
                  ],
                  "byte_index": 0
                },
                "write_instruction_address": 48374,
                "write_instruction_address_hex": "H'BCF6",
                "instruction": "MOV:G.B R0, @H'F853",
                "evidence_addresses": [
                  48374
                ],
                "evidence_addresses_hex": [
                  "H'BCF6"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "table",
                "source_expression": "primary_value_table_candidate",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0",
                  "byte_index": 0
                },
                "write_instruction_address": 48368,
                "write_instruction_address_hex": "H'BCF0",
                "instruction": "MOV:G.B R0, @H'F854",
                "evidence_addresses": [
                  48368
                ],
                "evidence_addresses_hex": [
                  "H'BCF0"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [
              "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.",
              "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.",
              "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape."
            ],
            "evidence_addresses": [
              48343,
              48360,
              48374,
              48368
            ],
            "evidence_addresses_hex": [
              "H'BCD7",
              "H'BCE8",
              "H'BCF6",
              "H'BCF0"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          },
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BE22",
            "call_address": 48674,
            "call_address_hex": "H'BE22",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[0]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 0,
                  "tx_address": 63576,
                  "tx_address_hex": "H'F858",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 0,
                    "tx_offsets": [
                      0,
                      1
                    ],
                    "tx_address": 63576,
                    "tx_address_hex": "H'F858",
                    "evidence_address": 48645,
                    "evidence_address_hex": "H'BE05",
                    "instruction": "MOV:G.W @H'F858, R0"
                  }
                },
                "write_instruction_address": 48649,
                "write_instruction_address_hex": "H'BE09",
                "instruction": "MOV:G.W R0, @H'F850",
                "evidence_addresses": [
                  48649
                ],
                "evidence_addresses_hex": [
                  "H'BE09"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[1]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 1,
                  "tx_address": 63577,
                  "tx_address_hex": "H'F859",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 0,
                    "tx_offsets": [
                      0,
                      1
                    ],
                    "tx_address": 63576,
                    "tx_address_hex": "H'F858",
                    "evidence_address": 48645,
                    "evidence_address_hex": "H'BE05",
                    "instruction": "MOV:G.W @H'F858, R0"
                  }
                },
                "write_instruction_address": 48649,
                "write_instruction_address_hex": "H'BE09",
                "instruction": "MOV:G.W R0, @H'F850",
                "evidence_addresses": [
                  48649
                ],
                "evidence_addresses_hex": [
                  "H'BE09"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[2]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 2,
                  "tx_address": 63578,
                  "tx_address_hex": "H'F85A",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 2,
                    "tx_offsets": [
                      2,
                      3
                    ],
                    "tx_address": 63578,
                    "tx_address_hex": "H'F85A",
                    "evidence_address": 48653,
                    "evidence_address_hex": "H'BE0D",
                    "instruction": "MOV:G.W @H'F85A, R0"
                  }
                },
                "write_instruction_address": 48657,
                "write_instruction_address_hex": "H'BE11",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48657
                ],
                "evidence_addresses_hex": [
                  "H'BE11"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[3]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 3,
                  "tx_address": 63579,
                  "tx_address_hex": "H'F85B",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 2,
                    "tx_offsets": [
                      2,
                      3
                    ],
                    "tx_address": 63578,
                    "tx_address_hex": "H'F85A",
                    "evidence_address": 48653,
                    "evidence_address_hex": "H'BE0D",
                    "instruction": "MOV:G.W @H'F85A, R0"
                  }
                },
                "write_instruction_address": 48657,
                "write_instruction_address_hex": "H'BE11",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48657
                ],
                "evidence_addresses_hex": [
                  "H'BE11"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[4]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 4,
                  "tx_address": 63580,
                  "tx_address_hex": "H'F85C",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 4,
                    "tx_offsets": [
                      4,
                      5
                    ],
                    "tx_address": 63580,
                    "tx_address_hex": "H'F85C",
                    "evidence_address": 48661,
                    "evidence_address_hex": "H'BE15",
                    "instruction": "MOV:G.W @H'F85C, R0"
                  }
                },
                "write_instruction_address": 48665,
                "write_instruction_address_hex": "H'BE19",
                "instruction": "MOV:G.W R0, @H'F854",
                "evidence_addresses": [
                  48665
                ],
                "evidence_addresses_hex": [
                  "H'BE19"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [],
            "evidence_addresses": [
              48649,
              48657,
              48665
            ],
            "evidence_addresses_hex": [
              "H'BE09",
              "H'BE11",
              "H'BE19"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          },
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BE6A",
            "call_address": 48746,
            "call_address_hex": "H'BE6A",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "immediate",
                "source_expression": "0x07",
                "source": {
                  "kind": "immediate",
                  "value": 7,
                  "value_hex": "H'07",
                  "byte_index": 0
                },
                "write_instruction_address": 48717,
                "write_instruction_address_hex": "H'BE4D",
                "instruction": "MOV:G.B #H'07, @H'F850",
                "evidence_addresses": [
                  48717
                ],
                "evidence_addresses_hex": [
                  "H'BE4D"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[1]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 1,
                    "rx_offsets": [
                      1
                    ],
                    "rx_address": 63585,
                    "rx_address_hex": "H'F861",
                    "evidence_address": 48722,
                    "evidence_address_hex": "H'BE52",
                    "instruction": "MOV:G.B @H'F861, R0"
                  }
                },
                "write_instruction_address": 48726,
                "write_instruction_address_hex": "H'BE56",
                "instruction": "MOV:G.B R0, @H'F851",
                "evidence_addresses": [
                  48726
                ],
                "evidence_addresses_hex": [
                  "H'BE56"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[2]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48730,
                    "evidence_address_hex": "H'BE5A",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48734,
                "write_instruction_address_hex": "H'BE5E",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48734
                ],
                "evidence_addresses_hex": [
                  "H'BE5E"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[3]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 3,
                  "rx_address": 63587,
                  "rx_address_hex": "H'F863",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48730,
                    "evidence_address_hex": "H'BE5A",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48734,
                "write_instruction_address_hex": "H'BE5E",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48734
                ],
                "evidence_addresses_hex": [
                  "H'BE5E"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[4]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 4,
                    "rx_offsets": [
                      4
                    ],
                    "rx_address": 63588,
                    "rx_address_hex": "H'F864",
                    "evidence_address": 48738,
                    "evidence_address_hex": "H'BE62",
                    "instruction": "MOV:G.B @H'F864, R0"
                  }
                },
                "write_instruction_address": 48742,
                "write_instruction_address_hex": "H'BE66",
                "instruction": "MOV:G.B R0, @H'F854",
                "evidence_addresses": [
                  48742
                ],
                "evidence_addresses_hex": [
                  "H'BE66"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [
              "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.",
              "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value."
            ],
            "evidence_addresses": [
              48717,
              48726,
              48734,
              48742
            ],
            "evidence_addresses_hex": [
              "H'BE4D",
              "H'BE56",
              "H'BE5E",
              "H'BE66"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          }
        ],
        "response_schema": [
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BB43",
            "call_address": 47939,
            "call_address_hex": "H'BB43",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "computed",
                "source_expression": "computed",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R1",
                  "source_category": "computed",
                  "operation": "AND",
                  "evidence_address": 47897,
                  "evidence_address_hex": "H'BB19",
                  "instruction": "AND.B #H'07, R1",
                  "byte_index": 0
                },
                "write_instruction_address": 47900,
                "write_instruction_address_hex": "H'BB1C",
                "instruction": "MOV:G.B R1, @H'F850",
                "evidence_addresses": [
                  47900
                ],
                "evidence_addresses_hex": [
                  "H'BB1C"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "computed",
                "source_expression": "computed",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R5",
                  "source_category": "computed",
                  "operation": "OR",
                  "evidence_address": 47913,
                  "evidence_address_hex": "H'BB29",
                  "instruction": "OR.B R2, R5",
                  "byte_index": 0
                },
                "write_instruction_address": 47915,
                "write_instruction_address_hex": "H'BB2B",
                "instruction": "MOV:G.B R5, @H'F851",
                "evidence_addresses": [
                  47915
                ],
                "evidence_addresses_hex": [
                  "H'BB2B"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "computed",
                "source_expression": "computed",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "@(-H'0790,R0)",
                  "source_category": "computed",
                  "evidence_address": 47880,
                  "evidence_address_hex": "H'BB08",
                  "instruction": "MOV:G.W @(-H'0790,R0), R0",
                  "byte_index": 0
                },
                "write_instruction_address": 47904,
                "write_instruction_address_hex": "H'BB20",
                "instruction": "MOV:G.B R5, @H'F852",
                "evidence_addresses": [
                  47904
                ],
                "evidence_addresses_hex": [
                  "H'BB20"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "table",
                "source_expression": "current_value_table_candidate",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4",
                  "transforms": [
                    "swap_bytes"
                  ],
                  "byte_index": 0
                },
                "write_instruction_address": 47935,
                "write_instruction_address_hex": "H'BB3F",
                "instruction": "MOV:G.B R4, @H'F853",
                "evidence_addresses": [
                  47935
                ],
                "evidence_addresses_hex": [
                  "H'BB3F"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "table",
                "source_expression": "current_value_table_candidate",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4",
                  "byte_index": 0
                },
                "write_instruction_address": 47929,
                "write_instruction_address_hex": "H'BB39",
                "instruction": "MOV:G.B R4, @H'F854",
                "evidence_addresses": [
                  47929
                ],
                "evidence_addresses_hex": [
                  "H'BB39"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [],
            "evidence_addresses": [
              47900,
              47915,
              47904,
              47935,
              47929
            ],
            "evidence_addresses_hex": [
              "H'BB1C",
              "H'BB2B",
              "H'BB20",
              "H'BB3F",
              "H'BB39"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          },
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BCCD",
            "call_address": 48333,
            "call_address_hex": "H'BCCD",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "immediate",
                "source_expression": "0x04",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04",
                  "byte_index": 0
                },
                "write_instruction_address": 48304,
                "write_instruction_address_hex": "H'BCB0",
                "instruction": "MOV:G.B #H'04, @H'F850",
                "evidence_addresses": [
                  48304
                ],
                "evidence_addresses_hex": [
                  "H'BCB0"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[1]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 1,
                    "rx_offsets": [
                      1
                    ],
                    "rx_address": 63585,
                    "rx_address_hex": "H'F861",
                    "evidence_address": 48309,
                    "evidence_address_hex": "H'BCB5",
                    "instruction": "MOV:G.B @H'F861, R0"
                  }
                },
                "write_instruction_address": 48313,
                "write_instruction_address_hex": "H'BCB9",
                "instruction": "MOV:G.B R0, @H'F851",
                "evidence_addresses": [
                  48313
                ],
                "evidence_addresses_hex": [
                  "H'BCB9"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[2]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48317,
                    "evidence_address_hex": "H'BCBD",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48321,
                "write_instruction_address_hex": "H'BCC1",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48321
                ],
                "evidence_addresses_hex": [
                  "H'BCC1"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[3]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 3,
                  "rx_address": 63587,
                  "rx_address_hex": "H'F863",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48317,
                    "evidence_address_hex": "H'BCBD",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48321,
                "write_instruction_address_hex": "H'BCC1",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48321
                ],
                "evidence_addresses_hex": [
                  "H'BCC1"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[4]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 4,
                    "rx_offsets": [
                      4
                    ],
                    "rx_address": 63588,
                    "rx_address_hex": "H'F864",
                    "evidence_address": 48325,
                    "evidence_address_hex": "H'BCC5",
                    "instruction": "MOV:G.B @H'F864, R0"
                  }
                },
                "write_instruction_address": 48329,
                "write_instruction_address_hex": "H'BCC9",
                "instruction": "MOV:G.B R0, @H'F854",
                "evidence_addresses": [
                  48329
                ],
                "evidence_addresses_hex": [
                  "H'BCC9"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [],
            "evidence_addresses": [
              48304,
              48313,
              48321,
              48329
            ],
            "evidence_addresses_hex": [
              "H'BCB0",
              "H'BCB9",
              "H'BCC1",
              "H'BCC9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          },
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BCFA",
            "call_address": 48378,
            "call_address_hex": "H'BCFA",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "immediate",
                "source_expression": "0x04",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04",
                  "byte_index": 0
                },
                "write_instruction_address": 48343,
                "write_instruction_address_hex": "H'BCD7",
                "instruction": "MOV:G.B #H'04, @H'F850",
                "evidence_addresses": [
                  48343
                ],
                "evidence_addresses_hex": [
                  "H'BCD7"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[2]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48356,
                    "evidence_address_hex": "H'BCE4",
                    "instruction": "MOV:G.B @H'F862, R0"
                  }
                },
                "write_instruction_address": 48360,
                "write_instruction_address_hex": "H'BCE8",
                "instruction": "MOV:G.B R0, @H'F851",
                "evidence_addresses": [
                  48360
                ],
                "evidence_addresses_hex": [
                  "H'BCE8"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "stale_or_unchanged",
                "source_expression": "stale/unchanged",
                "source": {
                  "kind": "unknown"
                },
                "evidence_addresses": [],
                "evidence_addresses_hex": [],
                "confidence": "candidate-low",
                "caveat": "BCD7 does not freshly write F852 before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "table",
                "source_expression": "primary_value_table_candidate",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0",
                  "transforms": [
                    "swap_bytes"
                  ],
                  "byte_index": 0
                },
                "write_instruction_address": 48374,
                "write_instruction_address_hex": "H'BCF6",
                "instruction": "MOV:G.B R0, @H'F853",
                "evidence_addresses": [
                  48374
                ],
                "evidence_addresses_hex": [
                  "H'BCF6"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "table",
                "source_expression": "primary_value_table_candidate",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0",
                  "byte_index": 0
                },
                "write_instruction_address": 48368,
                "write_instruction_address_hex": "H'BCF0",
                "instruction": "MOV:G.B R0, @H'F854",
                "evidence_addresses": [
                  48368
                ],
                "evidence_addresses_hex": [
                  "H'BCF0"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [
              "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.",
              "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.",
              "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape."
            ],
            "evidence_addresses": [
              48343,
              48360,
              48374,
              48368
            ],
            "evidence_addresses_hex": [
              "H'BCD7",
              "H'BCE8",
              "H'BCF6",
              "H'BCF0"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          },
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BE22",
            "call_address": 48674,
            "call_address_hex": "H'BE22",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[0]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 0,
                  "tx_address": 63576,
                  "tx_address_hex": "H'F858",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 0,
                    "tx_offsets": [
                      0,
                      1
                    ],
                    "tx_address": 63576,
                    "tx_address_hex": "H'F858",
                    "evidence_address": 48645,
                    "evidence_address_hex": "H'BE05",
                    "instruction": "MOV:G.W @H'F858, R0"
                  }
                },
                "write_instruction_address": 48649,
                "write_instruction_address_hex": "H'BE09",
                "instruction": "MOV:G.W R0, @H'F850",
                "evidence_addresses": [
                  48649
                ],
                "evidence_addresses_hex": [
                  "H'BE09"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[1]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 1,
                  "tx_address": 63577,
                  "tx_address_hex": "H'F859",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 0,
                    "tx_offsets": [
                      0,
                      1
                    ],
                    "tx_address": 63576,
                    "tx_address_hex": "H'F858",
                    "evidence_address": 48645,
                    "evidence_address_hex": "H'BE05",
                    "instruction": "MOV:G.W @H'F858, R0"
                  }
                },
                "write_instruction_address": 48649,
                "write_instruction_address_hex": "H'BE09",
                "instruction": "MOV:G.W R0, @H'F850",
                "evidence_addresses": [
                  48649
                ],
                "evidence_addresses_hex": [
                  "H'BE09"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[2]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 2,
                  "tx_address": 63578,
                  "tx_address_hex": "H'F85A",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 2,
                    "tx_offsets": [
                      2,
                      3
                    ],
                    "tx_address": 63578,
                    "tx_address_hex": "H'F85A",
                    "evidence_address": 48653,
                    "evidence_address_hex": "H'BE0D",
                    "instruction": "MOV:G.W @H'F85A, R0"
                  }
                },
                "write_instruction_address": 48657,
                "write_instruction_address_hex": "H'BE11",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48657
                ],
                "evidence_addresses_hex": [
                  "H'BE11"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[3]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 3,
                  "tx_address": 63579,
                  "tx_address_hex": "H'F85B",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 2,
                    "tx_offsets": [
                      2,
                      3
                    ],
                    "tx_address": 63578,
                    "tx_address_hex": "H'F85A",
                    "evidence_address": 48653,
                    "evidence_address_hex": "H'BE0D",
                    "instruction": "MOV:G.W @H'F85A, R0"
                  }
                },
                "write_instruction_address": 48657,
                "write_instruction_address_hex": "H'BE11",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48657
                ],
                "evidence_addresses_hex": [
                  "H'BE11"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "tx_frame_byte",
                "source_expression": "tx[4]",
                "source": {
                  "kind": "tx_frame_byte",
                  "tx_offset": 4,
                  "tx_address": 63580,
                  "tx_address_hex": "H'F85C",
                  "derived_from": {
                    "kind": "tx_frame_word",
                    "tx_offset": 4,
                    "tx_offsets": [
                      4,
                      5
                    ],
                    "tx_address": 63580,
                    "tx_address_hex": "H'F85C",
                    "evidence_address": 48661,
                    "evidence_address_hex": "H'BE15",
                    "instruction": "MOV:G.W @H'F85C, R0"
                  }
                },
                "write_instruction_address": 48665,
                "write_instruction_address_hex": "H'BE19",
                "instruction": "MOV:G.W R0, @H'F854",
                "evidence_addresses": [
                  48665
                ],
                "evidence_addresses_hex": [
                  "H'BE19"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [],
            "evidence_addresses": [
              48649,
              48657,
              48665
            ],
            "evidence_addresses_hex": [
              "H'BE09",
              "H'BE11",
              "H'BE19"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          },
          {
            "kind": "response_schema_candidate",
            "response_id": "response_at_BE6A",
            "call_address": 48746,
            "call_address_hex": "H'BE6A",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "bytes": [
              {
                "offset": 0,
                "byte": "byte0",
                "tx_byte": "TX[0]",
                "tx_staging_byte": "TX[0]",
                "address": 63568,
                "address_hex": "H'F850",
                "source_kind": "immediate",
                "source_expression": "0x07",
                "source": {
                  "kind": "immediate",
                  "value": 7,
                  "value_hex": "H'07",
                  "byte_index": 0
                },
                "write_instruction_address": 48717,
                "write_instruction_address_hex": "H'BE4D",
                "instruction": "MOV:G.B #H'07, @H'F850",
                "evidence_addresses": [
                  48717
                ],
                "evidence_addresses_hex": [
                  "H'BE4D"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 1,
                "byte": "byte1",
                "tx_byte": "TX[1]",
                "tx_staging_byte": "TX[1]",
                "address": 63569,
                "address_hex": "H'F851",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[1]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 1,
                    "rx_offsets": [
                      1
                    ],
                    "rx_address": 63585,
                    "rx_address_hex": "H'F861",
                    "evidence_address": 48722,
                    "evidence_address_hex": "H'BE52",
                    "instruction": "MOV:G.B @H'F861, R0"
                  }
                },
                "write_instruction_address": 48726,
                "write_instruction_address_hex": "H'BE56",
                "instruction": "MOV:G.B R0, @H'F851",
                "evidence_addresses": [
                  48726
                ],
                "evidence_addresses_hex": [
                  "H'BE56"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 2,
                "byte": "byte2",
                "tx_byte": "TX[2]",
                "tx_staging_byte": "TX[2]",
                "address": 63570,
                "address_hex": "H'F852",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[2]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48730,
                    "evidence_address_hex": "H'BE5A",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48734,
                "write_instruction_address_hex": "H'BE5E",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48734
                ],
                "evidence_addresses_hex": [
                  "H'BE5E"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 3,
                "byte": "byte3",
                "tx_byte": "TX[3]",
                "tx_staging_byte": "TX[3]",
                "address": 63571,
                "address_hex": "H'F853",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[3]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 3,
                  "rx_address": 63587,
                  "rx_address_hex": "H'F863",
                  "derived_from": {
                    "kind": "rx_frame_word",
                    "rx_offset": 2,
                    "rx_offsets": [
                      2,
                      3
                    ],
                    "rx_address": 63586,
                    "rx_address_hex": "H'F862",
                    "evidence_address": 48730,
                    "evidence_address_hex": "H'BE5A",
                    "instruction": "MOV:G.W @H'F862, R0"
                  }
                },
                "write_instruction_address": 48734,
                "write_instruction_address_hex": "H'BE5E",
                "instruction": "MOV:G.W R0, @H'F852",
                "evidence_addresses": [
                  48734
                ],
                "evidence_addresses_hex": [
                  "H'BE5E"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              },
              {
                "offset": 4,
                "byte": "byte4",
                "tx_byte": "TX[4]",
                "tx_staging_byte": "TX[4]",
                "address": 63572,
                "address_hex": "H'F854",
                "source_kind": "rx_frame_byte",
                "source_expression": "rx[4]",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "derived_from": {
                    "kind": "rx_frame_byte",
                    "rx_offset": 4,
                    "rx_offsets": [
                      4
                    ],
                    "rx_address": 63588,
                    "rx_address_hex": "H'F864",
                    "evidence_address": 48738,
                    "evidence_address_hex": "H'BE62",
                    "instruction": "MOV:G.B @H'F864, R0"
                  }
                },
                "write_instruction_address": 48742,
                "write_instruction_address_hex": "H'BE66",
                "instruction": "MOV:G.B R0, @H'F854",
                "evidence_addresses": [
                  48742
                ],
                "evidence_addresses_hex": [
                  "H'BE66"
                ],
                "confidence": "candidate-medium",
                "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
              }
            ],
            "semantic_notes": [
              "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.",
              "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value."
            ],
            "evidence_addresses": [
              48717,
              48726,
              48734,
              48742
            ],
            "evidence_addresses_hex": [
              "H'BE4D",
              "H'BE56",
              "H'BE5E",
              "H'BE66"
            ],
            "confidence": "candidate-medium",
            "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
          }
        ],
        "rx_fields": [
          {
            "kind": "rx_field_semantic_candidate",
            "offset": 0,
            "name": "command_low3",
            "address": 63584,
            "address_hex": "H'F860",
            "confidence": "candidate-high",
            "caveat": "RX[0] is masked with 0x07 before command comparisons",
            "evidence_addresses": [
              48088,
              48136,
              48140,
              48160,
              48162,
              48164,
              48166,
              48169,
              48171,
              48174,
              48176,
              48197,
              48199,
              48202,
              48204,
              48207,
              48209,
              48212,
              48214
            ],
            "evidence_addresses_hex": [
              "H'BBD8",
              "H'BC08",
              "H'BC0C",
              "H'BC20",
              "H'BC22",
              "H'BC24",
              "H'BC26",
              "H'BC29",
              "H'BC2B",
              "H'BC2E",
              "H'BC30",
              "H'BC45",
              "H'BC47",
              "H'BC4A",
              "H'BC4C",
              "H'BC4F",
              "H'BC51",
              "H'BC54",
              "H'BC56"
            ],
            "mask": 7,
            "mask_hex": "H'07"
          },
          {
            "kind": "rx_field_semantic_candidate",
            "offset": 1,
            "name": "likely_id_or_index",
            "address": 63585,
            "address_hex": "H'F861",
            "confidence": "candidate-medium",
            "caveat": "RX[1:2] are read near logical point/index and response-echo handling",
            "evidence_addresses": [
              48092,
              48119,
              48153,
              48190,
              48309,
              48348,
              48722
            ],
            "evidence_addresses_hex": [
              "H'BBDC",
              "H'BBF7",
              "H'BC19",
              "H'BC3E",
              "H'BCB5",
              "H'BCDC",
              "H'BE52"
            ]
          },
          {
            "kind": "rx_field_semantic_candidate",
            "offset": 2,
            "name": "likely_id_or_index",
            "address": 63586,
            "address_hex": "H'F862",
            "confidence": "candidate-medium",
            "caveat": "RX[1:2] are read near logical point/index and response-echo handling",
            "evidence_addresses": [
              48096,
              48125,
              48317,
              48356,
              48730
            ],
            "evidence_addresses_hex": [
              "H'BBE0",
              "H'BBFD",
              "H'BCBD",
              "H'BCE4",
              "H'BE5A"
            ]
          },
          {
            "kind": "rx_field_semantic_candidate",
            "offset": 3,
            "name": "likely_value",
            "address": 63587,
            "address_hex": "H'F863",
            "confidence": "candidate-medium",
            "caveat": "RX[3:4] are read near table-value write/read response handling",
            "evidence_addresses": [
              48100,
              48237,
              48267,
              48402,
              48427,
              48603
            ],
            "evidence_addresses_hex": [
              "H'BBE4",
              "H'BC6D",
              "H'BC8B",
              "H'BD12",
              "H'BD2B",
              "H'BDDB"
            ]
          },
          {
            "kind": "rx_field_semantic_candidate",
            "offset": 4,
            "name": "likely_value",
            "address": 63588,
            "address_hex": "H'F864",
            "confidence": "candidate-medium",
            "caveat": "RX[3:4] are read near table-value write/read response handling",
            "evidence_addresses": [
              48104,
              48273,
              48325,
              48433,
              48609,
              48738
            ],
            "evidence_addresses_hex": [
              "H'BBE8",
              "H'BC91",
              "H'BCC5",
              "H'BD31",
              "H'BDE1",
              "H'BE62"
            ]
          },
          {
            "kind": "rx_field_semantic_candidate",
            "offset": 5,
            "name": "checksum",
            "address": 63589,
            "address_hex": "H'F865",
            "confidence": "candidate-high",
            "caveat": "RX[5] is validated by the serial reconstruction checksum evidence",
            "evidence_addresses": [
              48108
            ],
            "evidence_addresses_hex": [
              "H'BBEC"
            ]
          }
        ],
        "response_builders": [
          {
            "kind": "response_builder_candidate",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "send_call_target": 47654,
            "send_call_target_hex": "H'BA26",
            "call_address": 47939,
            "call_address_hex": "H'BB43",
            "writes": [
              {
                "address": 63568,
                "address_hex": "H'F850",
                "instruction_address": 47900,
                "instruction_address_hex": "H'BB1C",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R1",
                  "source_category": "computed",
                  "operation": "AND",
                  "evidence_address": 47897,
                  "evidence_address_hex": "H'BB19",
                  "instruction": "AND.B #H'07, R1"
                },
                "instruction": "MOV:G.B R1, @H'F850"
              },
              {
                "address": 63570,
                "address_hex": "H'F852",
                "instruction_address": 47904,
                "instruction_address_hex": "H'BB20",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "@(-H'0790,R0)",
                  "source_category": "computed",
                  "evidence_address": 47880,
                  "evidence_address_hex": "H'BB08",
                  "instruction": "MOV:G.W @(-H'0790,R0), R0"
                },
                "instruction": "MOV:G.B R5, @H'F852"
              },
              {
                "address": 63569,
                "address_hex": "H'F851",
                "instruction_address": 47915,
                "instruction_address_hex": "H'BB2B",
                "source": {
                  "kind": "register_or_computed",
                  "operand": "R5",
                  "source_category": "computed",
                  "operation": "OR",
                  "evidence_address": 47913,
                  "evidence_address_hex": "H'BB29",
                  "instruction": "OR.B R2, R5"
                },
                "instruction": "MOV:G.B R5, @H'F851"
              },
              {
                "address": 63572,
                "address_hex": "H'F854",
                "instruction_address": 47929,
                "instruction_address_hex": "H'BB39",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4"
                },
                "instruction": "MOV:G.B R4, @H'F854"
              },
              {
                "address": 63571,
                "address_hex": "H'F853",
                "instruction_address": 47935,
                "instruction_address_hex": "H'BB3F",
                "source": {
                  "name_candidate": "current_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 59392,
                  "logical_base_address_hex": "H'E800",
                  "negative_offset": 6144,
                  "negative_offset_hex": "H'1800",
                  "index_register": "R0",
                  "operand": "@(-H'1800,R0)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 47925,
                  "evidence_address_hex": "H'BB35",
                  "instruction": "MOV:G.W @(-H'1800,R0), R4",
                  "transforms": [
                    "swap_bytes"
                  ]
                },
                "instruction": "MOV:G.B R4, @H'F853"
              }
            ],
            "semantic_notes": [],
            "evidence_addresses": [
              47900,
              47904,
              47915,
              47929,
              47935,
              47939
            ],
            "evidence_addresses_hex": [
              "H'BB1C",
              "H'BB20",
              "H'BB2B",
              "H'BB39",
              "H'BB3F",
              "H'BB43"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path."
          },
          {
            "kind": "response_builder_candidate",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "send_call_target": 47654,
            "send_call_target_hex": "H'BA26",
            "call_address": 48333,
            "call_address_hex": "H'BCCD",
            "writes": [
              {
                "address": 63568,
                "address_hex": "H'F850",
                "instruction_address": 48304,
                "instruction_address_hex": "H'BCB0",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04"
                },
                "instruction": "MOV:G.B #H'04, @H'F850"
              },
              {
                "address": 63569,
                "address_hex": "H'F851",
                "instruction_address": 48313,
                "instruction_address_hex": "H'BCB9",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_offsets": [
                    1
                  ],
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "evidence_address": 48309,
                  "evidence_address_hex": "H'BCB5",
                  "instruction": "MOV:G.B @H'F861, R0"
                },
                "instruction": "MOV:G.B R0, @H'F851"
              },
              {
                "address": 63570,
                "address_hex": "H'F852",
                "instruction_address": 48321,
                "instruction_address_hex": "H'BCC1",
                "source": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48317,
                  "evidence_address_hex": "H'BCBD",
                  "instruction": "MOV:G.W @H'F862, R0"
                },
                "instruction": "MOV:G.W R0, @H'F852"
              },
              {
                "address": 63571,
                "address_hex": "H'F853",
                "instruction_address": 48321,
                "instruction_address_hex": "H'BCC1",
                "source": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48317,
                  "evidence_address_hex": "H'BCBD",
                  "instruction": "MOV:G.W @H'F862, R0"
                },
                "instruction": "MOV:G.W R0, @H'F852"
              },
              {
                "address": 63572,
                "address_hex": "H'F854",
                "instruction_address": 48329,
                "instruction_address_hex": "H'BCC9",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_offsets": [
                    4
                  ],
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "evidence_address": 48325,
                  "evidence_address_hex": "H'BCC5",
                  "instruction": "MOV:G.B @H'F864, R0"
                },
                "instruction": "MOV:G.B R0, @H'F854"
              }
            ],
            "semantic_notes": [],
            "evidence_addresses": [
              48304,
              48313,
              48321,
              48329,
              48309,
              48317,
              48325,
              48333
            ],
            "evidence_addresses_hex": [
              "H'BCB0",
              "H'BCB9",
              "H'BCC1",
              "H'BCC9",
              "H'BCB5",
              "H'BCBD",
              "H'BCC5",
              "H'BCCD"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path."
          },
          {
            "kind": "response_builder_candidate",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "send_call_target": 47654,
            "send_call_target_hex": "H'BA26",
            "call_address": 48378,
            "call_address_hex": "H'BCFA",
            "writes": [
              {
                "address": 63568,
                "address_hex": "H'F850",
                "instruction_address": 48343,
                "instruction_address_hex": "H'BCD7",
                "source": {
                  "kind": "immediate",
                  "value": 4,
                  "value_hex": "H'04"
                },
                "instruction": "MOV:G.B #H'04, @H'F850"
              },
              {
                "address": 63569,
                "address_hex": "H'F851",
                "instruction_address": 48352,
                "instruction_address_hex": "H'BCE0",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_offsets": [
                    1
                  ],
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "evidence_address": 48348,
                  "evidence_address_hex": "H'BCDC",
                  "instruction": "MOV:G.B @H'F861, R0"
                },
                "instruction": "MOV:G.B R0, @H'F851"
              },
              {
                "address": 63569,
                "address_hex": "H'F851",
                "instruction_address": 48360,
                "instruction_address_hex": "H'BCE8",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48356,
                  "evidence_address_hex": "H'BCE4",
                  "instruction": "MOV:G.B @H'F862, R0"
                },
                "instruction": "MOV:G.B R0, @H'F851"
              },
              {
                "address": 63572,
                "address_hex": "H'F854",
                "instruction_address": 48368,
                "instruction_address_hex": "H'BCF0",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0"
                },
                "instruction": "MOV:G.B R0, @H'F854"
              },
              {
                "address": 63571,
                "address_hex": "H'F853",
                "instruction_address": 48374,
                "instruction_address_hex": "H'BCF6",
                "source": {
                  "name_candidate": "primary_value_table_candidate",
                  "element_candidate": "word_value",
                  "logical_base_address": 57344,
                  "logical_base_address_hex": "H'E000",
                  "negative_offset": 8192,
                  "negative_offset_hex": "H'2000",
                  "index_register": "R4",
                  "operand": "@(-H'2000,R4)",
                  "kind": "table",
                  "access_width": 2,
                  "evidence_address": 48364,
                  "evidence_address_hex": "H'BCEC",
                  "instruction": "MOV:G.W @(-H'2000,R4), R0",
                  "transforms": [
                    "swap_bytes"
                  ]
                },
                "instruction": "MOV:G.B R0, @H'F853"
              }
            ],
            "semantic_notes": [
              "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.",
              "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.",
              "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape."
            ],
            "evidence_addresses": [
              48343,
              48352,
              48360,
              48368,
              48374,
              48348,
              48356,
              48378
            ],
            "evidence_addresses_hex": [
              "H'BCD7",
              "H'BCE0",
              "H'BCE8",
              "H'BCF0",
              "H'BCF6",
              "H'BCDC",
              "H'BCE4",
              "H'BCFA"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path."
          },
          {
            "kind": "response_builder_candidate",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "send_call_target": 47654,
            "send_call_target_hex": "H'BA26",
            "call_address": 48674,
            "call_address_hex": "H'BE22",
            "writes": [
              {
                "address": 63568,
                "address_hex": "H'F850",
                "instruction_address": 48649,
                "instruction_address_hex": "H'BE09",
                "source": {
                  "kind": "tx_frame_word",
                  "tx_offset": 0,
                  "tx_offsets": [
                    0,
                    1
                  ],
                  "tx_address": 63576,
                  "tx_address_hex": "H'F858",
                  "evidence_address": 48645,
                  "evidence_address_hex": "H'BE05",
                  "instruction": "MOV:G.W @H'F858, R0"
                },
                "instruction": "MOV:G.W R0, @H'F850"
              },
              {
                "address": 63569,
                "address_hex": "H'F851",
                "instruction_address": 48649,
                "instruction_address_hex": "H'BE09",
                "source": {
                  "kind": "tx_frame_word",
                  "tx_offset": 0,
                  "tx_offsets": [
                    0,
                    1
                  ],
                  "tx_address": 63576,
                  "tx_address_hex": "H'F858",
                  "evidence_address": 48645,
                  "evidence_address_hex": "H'BE05",
                  "instruction": "MOV:G.W @H'F858, R0"
                },
                "instruction": "MOV:G.W R0, @H'F850"
              },
              {
                "address": 63570,
                "address_hex": "H'F852",
                "instruction_address": 48657,
                "instruction_address_hex": "H'BE11",
                "source": {
                  "kind": "tx_frame_word",
                  "tx_offset": 2,
                  "tx_offsets": [
                    2,
                    3
                  ],
                  "tx_address": 63578,
                  "tx_address_hex": "H'F85A",
                  "evidence_address": 48653,
                  "evidence_address_hex": "H'BE0D",
                  "instruction": "MOV:G.W @H'F85A, R0"
                },
                "instruction": "MOV:G.W R0, @H'F852"
              },
              {
                "address": 63571,
                "address_hex": "H'F853",
                "instruction_address": 48657,
                "instruction_address_hex": "H'BE11",
                "source": {
                  "kind": "tx_frame_word",
                  "tx_offset": 2,
                  "tx_offsets": [
                    2,
                    3
                  ],
                  "tx_address": 63578,
                  "tx_address_hex": "H'F85A",
                  "evidence_address": 48653,
                  "evidence_address_hex": "H'BE0D",
                  "instruction": "MOV:G.W @H'F85A, R0"
                },
                "instruction": "MOV:G.W R0, @H'F852"
              },
              {
                "address": 63572,
                "address_hex": "H'F854",
                "instruction_address": 48665,
                "instruction_address_hex": "H'BE19",
                "source": {
                  "kind": "tx_frame_word",
                  "tx_offset": 4,
                  "tx_offsets": [
                    4,
                    5
                  ],
                  "tx_address": 63580,
                  "tx_address_hex": "H'F85C",
                  "evidence_address": 48661,
                  "evidence_address_hex": "H'BE15",
                  "instruction": "MOV:G.W @H'F85C, R0"
                },
                "instruction": "MOV:G.W R0, @H'F854"
              }
            ],
            "semantic_notes": [],
            "evidence_addresses": [
              48649,
              48657,
              48665,
              48674
            ],
            "evidence_addresses_hex": [
              "H'BE09",
              "H'BE11",
              "H'BE19",
              "H'BE22"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path."
          },
          {
            "kind": "response_builder_candidate",
            "buffer_start": 63568,
            "buffer_start_hex": "H'F850",
            "buffer_end": 63572,
            "buffer_end_hex": "H'F854",
            "send_call_target": 47654,
            "send_call_target_hex": "H'BA26",
            "call_address": 48746,
            "call_address_hex": "H'BE6A",
            "writes": [
              {
                "address": 63568,
                "address_hex": "H'F850",
                "instruction_address": 48717,
                "instruction_address_hex": "H'BE4D",
                "source": {
                  "kind": "immediate",
                  "value": 7,
                  "value_hex": "H'07"
                },
                "instruction": "MOV:G.B #H'07, @H'F850"
              },
              {
                "address": 63569,
                "address_hex": "H'F851",
                "instruction_address": 48726,
                "instruction_address_hex": "H'BE56",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_offsets": [
                    1
                  ],
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "evidence_address": 48722,
                  "evidence_address_hex": "H'BE52",
                  "instruction": "MOV:G.B @H'F861, R0"
                },
                "instruction": "MOV:G.B R0, @H'F851"
              },
              {
                "address": 63570,
                "address_hex": "H'F852",
                "instruction_address": 48734,
                "instruction_address_hex": "H'BE5E",
                "source": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48730,
                  "evidence_address_hex": "H'BE5A",
                  "instruction": "MOV:G.W @H'F862, R0"
                },
                "instruction": "MOV:G.W R0, @H'F852"
              },
              {
                "address": 63571,
                "address_hex": "H'F853",
                "instruction_address": 48734,
                "instruction_address_hex": "H'BE5E",
                "source": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48730,
                  "evidence_address_hex": "H'BE5A",
                  "instruction": "MOV:G.W @H'F862, R0"
                },
                "instruction": "MOV:G.W R0, @H'F852"
              },
              {
                "address": 63572,
                "address_hex": "H'F854",
                "instruction_address": 48742,
                "instruction_address_hex": "H'BE66",
                "source": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_offsets": [
                    4
                  ],
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "evidence_address": 48738,
                  "evidence_address_hex": "H'BE62",
                  "instruction": "MOV:G.B @H'F864, R0"
                },
                "instruction": "MOV:G.B R0, @H'F854"
              }
            ],
            "semantic_notes": [
              "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.",
              "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value."
            ],
            "evidence_addresses": [
              48717,
              48726,
              48734,
              48742,
              48722,
              48730,
              48738,
              48746
            ],
            "evidence_addresses_hex": [
              "H'BE4D",
              "H'BE56",
              "H'BE5E",
              "H'BE66",
              "H'BE52",
              "H'BE5A",
              "H'BE62",
              "H'BE6A"
            ],
            "confidence": "medium",
            "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path."
          }
        ],
        "retry_error_model": {
          "kind": "serial_retry_error_model_candidate",
          "checksum_failure_path": {
            "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]",
            "error_target": "loc_BE29",
            "error_target_address": 48681,
            "error_target_address_hex": "H'BE29",
            "checksum_error_response_candidates": [
              "response_at_BE6A"
            ],
            "branch_evidence_addresses": [
              48112
            ],
            "branch_evidence_addresses_hex": [
              "H'BBF0"
            ],
            "evidence_addresses": [
              48088,
              48092,
              48096,
              48100,
              48104,
              48108,
              48112,
              48717,
              48726,
              48734,
              48742,
              48722,
              48730,
              48738,
              48746
            ],
            "evidence_addresses_hex": [
              "H'BBD8",
              "H'BBDC",
              "H'BBE0",
              "H'BBE4",
              "H'BBE8",
              "H'BBEC",
              "H'BBF0",
              "H'BE4D",
              "H'BE56",
              "H'BE5E",
              "H'BE66",
              "H'BE52",
              "H'BE5A",
              "H'BE62",
              "H'BE6A"
            ],
            "confidence": "candidate-high"
          },
          "retry_path": {
            "entry_label": "loc_BE29",
            "entry_address": 48681,
            "entry_address_hex": "H'BE29",
            "counter_address": 64166,
            "counter_address_hex": "H'FAA6",
            "threshold_candidate": 2,
            "response_candidates": [
              "response_at_BE6A"
            ],
            "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.",
            "echo_response_candidate": {
              "entry_label": "loc_BE4D",
              "entry_address": 48717,
              "entry_address_hex": "H'BE4D",
              "staging_candidate": "F850=0x07; F851-F854=F861-F864",
              "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value."
            },
            "evidence_addresses": [
              48681,
              48685,
              48691,
              48695,
              48707,
              48711,
              48717,
              48726,
              48734,
              48742,
              48722,
              48730,
              48738,
              48746
            ],
            "evidence_addresses_hex": [
              "H'BE29",
              "H'BE2D",
              "H'BE33",
              "H'BE37",
              "H'BE43",
              "H'BE47",
              "H'BE4D",
              "H'BE56",
              "H'BE5E",
              "H'BE66",
              "H'BE52",
              "H'BE5A",
              "H'BE62",
              "H'BE6A"
            ],
            "confidence": "candidate-medium"
          },
          "command_0x07_path": {
            "entry_label": "loc_BE05",
            "entry_address": 48645,
            "entry_address_hex": "H'BE05",
            "response_candidates": [
              "response_at_BE22"
            ],
            "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.",
            "evidence_addresses": [
              48645,
              48653,
              48661,
              48649,
              48657,
              48665,
              48674
            ],
            "evidence_addresses_hex": [
              "H'BE05",
              "H'BE0D",
              "H'BE15",
              "H'BE09",
              "H'BE11",
              "H'BE19",
              "H'BE22"
            ],
            "confidence": "candidate-medium"
          },
          "evidence_addresses": [
            48088,
            48092,
            48096,
            48100,
            48104,
            48108,
            48112,
            48717,
            48726,
            48734,
            48742,
            48722,
            48730,
            48738,
            48746,
            48681,
            48685,
            48691,
            48695,
            48707,
            48711,
            48645,
            48653,
            48661,
            48649,
            48657,
            48665,
            48674
          ],
          "evidence_addresses_hex": [
            "H'BBD8",
            "H'BBDC",
            "H'BBE0",
            "H'BBE4",
            "H'BBE8",
            "H'BBEC",
            "H'BBF0",
            "H'BE4D",
            "H'BE56",
            "H'BE5E",
            "H'BE66",
            "H'BE52",
            "H'BE5A",
            "H'BE62",
            "H'BE6A",
            "H'BE29",
            "H'BE2D",
            "H'BE33",
            "H'BE37",
            "H'BE43",
            "H'BE47",
            "H'BE05",
            "H'BE0D",
            "H'BE15",
            "H'BE09",
            "H'BE11",
            "H'BE19",
            "H'BE22"
          ],
          "confidence": "candidate-medium",
          "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing."
        },
        "gate_queue_model": {
          "kind": "serial_gate_queue_state_machine_candidate",
          "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.",
          "predicates": [
            {
              "name": "main_loop_may_enter_report_builder",
              "entry_label": "loc_3FD3",
              "target_label": "loc_BAF2",
              "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))",
              "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.",
              "state_addresses_hex": [
                "H'FAA2",
                "H'FAA5",
                "H'F9C3",
                "H'F9C0"
              ],
              "evidence_addresses": [
                16339,
                16343,
                16345,
                16349,
                16351,
                16355,
                16357,
                16361,
                16363
              ]
            },
            {
              "name": "idle_heartbeat_report_may_enqueue",
              "entry_label": "loc_4046",
              "target_label": "loc_4067",
              "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5",
              "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.",
              "state_addresses_hex": [
                "H'F9C4",
                "H'FAA5",
                "H'F9C3",
                "H'F9B0",
                "H'F9B5"
              ],
              "enqueued_report_candidate_hex": "H'0000",
              "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.",
              "runtime_trace_confirmation": {
                "source": "h8536_emulator_probe target-frame run",
                "report_id_hex": "H'0000",
                "queue_write_address_hex": "H'4067",
                "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF",
                "dequeue_path": [
                  "loc_4046",
                  "loc_BAF2",
                  "loc_BB08",
                  "loc_BB1C",
                  "loc_BB20",
                  "loc_BB2B",
                  "loc_BA26"
                ],
                "emitted_frame_hex": "00 00 00 00 80 DA",
                "checksum_seed_hex": "H'5A",
                "checksum_hex": "H'DA"
              },
              "evidence_addresses": [
                16454,
                16458,
                16460,
                16464,
                16466,
                16470,
                16472,
                16473,
                16477,
                16479,
                16483,
                16485,
                16487,
                16492,
                16496
              ]
            },
            {
              "name": "queue_has_pending_report",
              "entry_label": "loc_BAF2",
              "condition_candidate": "F9B5 != F9B0",
              "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.",
              "state_addresses_hex": [
                "H'F9B5",
                "H'F9B0"
              ],
              "staging_path": [
                "loc_BAF2",
                "loc_BB43",
                "loc_BA26"
              ],
              "evidence_addresses": [
                47858,
                47862,
                47864,
                47868,
                47870,
                47872,
                47876,
                47878,
                47880,
                47884,
                47886,
                47889,
                47891,
                47893,
                47895,
                47897,
                47900,
                47904,
                47908,
                47910,
                47913,
                47915,
                47919,
                47923,
                47925,
                47929,
                47933,
                47935,
                47939
              ]
            },
            {
              "name": "periodic_resend_may_fire",
              "entry_label": "loc_BE9E",
              "target_label": "loc_BED5",
              "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown",
              "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.",
              "state_addresses_hex": [
                "H'FAA5",
                "H'FAA3",
                "H'F9C6",
                "H'F9C8"
              ],
              "evidence_addresses": [
                48798,
                48802,
                48805,
                48809,
                48813,
                48815,
                48819,
                48821,
                48825,
                48827,
                48831,
                48833,
                48837,
                48843,
                48847,
                48849,
                48853
              ]
            }
          ],
          "session_effects": [
            {
              "name": "rx_completion_sets_session_timer",
              "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.",
              "state_addresses_hex": [
                "H'F9C5"
              ],
              "evidence_addresses": [
                48030
              ]
            },
            {
              "name": "session_timeout_clears_gate_and_queue",
              "entry_label": "loc_3FEF",
              "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.",
              "state_addresses_hex": [
                "H'F9C5",
                "H'F9B5",
                "H'F9B0",
                "H'FAA5"
              ],
              "evidence_addresses": [
                16367,
                16371,
                16373,
                16377,
                16381,
                16385,
                16387,
                16389,
                16391
              ]
            },
            {
              "name": "idle_heartbeat_gate_initial_delay_loaded",
              "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.",
              "state_addresses_hex": [
                "H'F9C4"
              ],
              "reload_value_hex": "H'14",
              "evidence_addresses": [
                16608
              ]
            },
            {
              "name": "idle_heartbeat_gate_post_send_delay_loaded",
              "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.",
              "state_addresses_hex": [
                "H'F9C4"
              ],
              "reload_value_hex": "H'07",
              "evidence_addresses": [
                47665
              ]
            },
            {
              "name": "host_ack_can_advance_queue",
              "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.",
              "command_values_hex": [
                "H'05"
              ],
              "state_addresses_hex": [
                "H'FAA2",
                "H'FAA3",
                "H'F9B5"
              ],
              "evidence_addresses": [
                48136,
                48140,
                48202,
                48204
              ]
            }
          ],
          "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.",
          "confidence": "candidate-medium",
          "evidence_addresses": [
            16339,
            16343,
            16345,
            16349,
            16351,
            16355,
            16357,
            16361,
            16363,
            16367,
            16371,
            16373,
            16377,
            16381,
            16385,
            16387,
            16389,
            16391,
            16454,
            16458,
            16460,
            16464,
            16466,
            16470,
            16472,
            16473,
            16477,
            16479,
            16483,
            16485,
            16487,
            16492,
            16496,
            47858,
            47862,
            47864,
            47868,
            47870,
            47872,
            47876,
            47878,
            47880,
            47884,
            47886,
            47889,
            47891,
            47893,
            47895,
            47897,
            47900,
            47904,
            47908,
            47910,
            47913,
            47915,
            47919,
            47923,
            47925,
            47929,
            47933,
            47935,
            47939,
            48798,
            48802,
            48805,
            48809,
            48813,
            48815,
            48819,
            48821,
            48825,
            48827,
            48831,
            48833,
            48837,
            48843,
            48847,
            48849,
            48853
          ],
          "evidence_addresses_hex": [
            "H'3FD3",
            "H'3FD7",
            "H'3FD9",
            "H'3FDD",
            "H'3FDF",
            "H'3FE3",
            "H'3FE5",
            "H'3FE9",
            "H'3FEB",
            "H'3FEF",
            "H'3FF3",
            "H'3FF5",
            "H'3FF9",
            "H'3FFD",
            "H'4001",
            "H'4003",
            "H'4005",
            "H'4007",
            "H'4046",
            "H'404A",
            "H'404C",
            "H'4050",
            "H'4052",
            "H'4056",
            "H'4058",
            "H'4059",
            "H'405D",
            "H'405F",
            "H'4063",
            "H'4065",
            "H'4067",
            "H'406C",
            "H'4070",
            "H'BAF2",
            "H'BAF6",
            "H'BAF8",
            "H'BAFC",
            "H'BAFE",
            "H'BB00",
            "H'BB04",
            "H'BB06",
            "H'BB08",
            "H'BB0C",
            "H'BB0E",
            "H'BB11",
            "H'BB13",
            "H'BB15",
            "H'BB17",
            "H'BB19",
            "H'BB1C",
            "H'BB20",
            "H'BB24",
            "H'BB26",
            "H'BB29",
            "H'BB2B",
            "H'BB2F",
            "H'BB33",
            "H'BB35",
            "H'BB39",
            "H'BB3D",
            "H'BB3F",
            "H'BB43",
            "H'BE9E",
            "H'BEA2",
            "H'BEA5",
            "H'BEA9",
            "H'BEAD",
            "H'BEAF",
            "H'BEB3",
            "H'BEB5",
            "H'BEB9",
            "H'BEBB",
            "H'BEBF",
            "H'BEC1",
            "H'BEC5",
            "H'BECB",
            "H'BECF",
            "H'BED1",
            "H'BED5"
          ]
        },
        "tx_report_model": {
          "kind": "bb43_to_ba26_tx_report_model_candidate",
          "direction": "device_to_host_autonomous_report_candidate",
          "entry_label": "loc_BB43",
          "entry_address": 47939,
          "entry_address_hex": "H'BB43",
          "send_builder": "loc_BA26",
          "send_builder_address": 47654,
          "send_builder_address_hex": "H'BA26",
          "response_candidates": [
            "response_at_BB43"
          ],
          "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.",
          "byte_roles": [
            {
              "offset": 0,
              "field_candidate": "encoded_logical_index_or_report_id_byte0",
              "source_candidate": "computed from candidate logical index/report id"
            },
            {
              "offset": 1,
              "field_candidate": "encoded_logical_index_or_report_id_byte1",
              "source_candidate": "computed from candidate logical index/report id"
            },
            {
              "offset": 2,
              "field_candidate": "encoded_logical_index_or_report_id_byte2",
              "source_candidate": "computed from candidate logical index/report id"
            },
            {
              "offset": 3,
              "field_candidate": "current_value_hi",
              "source_candidate": "current_value_table_candidate high byte",
              "table_candidate": "current_value_table_candidate"
            },
            {
              "offset": 4,
              "field_candidate": "current_value_lo",
              "source_candidate": "current_value_table_candidate low byte",
              "table_candidate": "current_value_table_candidate"
            },
            {
              "offset": 5,
              "field_candidate": "checksum",
              "source_candidate": "0x5A XOR TX[0..4]"
            }
          ],
          "value_source_candidate": "current_value_table_candidate",
          "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4",
          "observed_capture_overlay_candidates": [
            {
              "logical_index": 0,
              "name_candidate": "heartbeat_or_idle_report_candidate",
              "observed_frames_hex": [
                "00 00 00 00 80 DA"
              ],
              "observed_period_ms_candidate": 700
            },
            {
              "logical_index": 21,
              "name_candidate": "call_button_report_candidate",
              "observed_frames_hex": [
                "00 00 15 80 00 CF",
                "00 00 15 00 00 4F"
              ]
            },
            {
              "logical_index": 7,
              "name_candidate": "camera_power_report_candidate",
              "observed_frames_hex": [
                "00 00 07 80 00 DD"
              ]
            }
          ],
          "runtime_confirmed_paths": [
            {
              "name": "idle_heartbeat_report_runtime_confirmation",
              "report_id_hex": "H'0000",
              "queue_write_address_hex": "H'4067",
              "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot",
              "staging_path": [
                "loc_4046",
                "loc_BAF2",
                "loc_BB08",
                "loc_BB1C",
                "loc_BB20",
                "loc_BB2B",
                "loc_BA26"
              ],
              "emitted_frame_hex": "00 00 00 00 80 DA",
              "checksum_hex": "H'DA"
            }
          ],
          "consistency_checks": [
            {
              "name": "idle_heartbeat_report_id_width",
              "status": "pass",
              "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000."
            }
          ],
          "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.",
          "confidence": "candidate-medium",
          "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.",
          "evidence_addresses": [
            47900,
            47904,
            47915,
            47929,
            47935,
            47939
          ],
          "evidence_addresses_hex": [
            "H'BB1C",
            "H'BB20",
            "H'BB2B",
            "H'BB39",
            "H'BB3F",
            "H'BB43"
          ]
        },
        "periodic_resend_model": {
          "kind": "autonomous_periodic_resend_model_candidate",
          "period_timer": {
            "address": 63942,
            "address_hex": "H'F9C6",
            "reload_value_candidate": 500,
            "reload_value_hex": "H'01F4",
            "summary": "Candidate periodic report/heartbeat timer reload.",
            "evidence_addresses": [
              47942,
              48837
            ],
            "evidence_addresses_hex": [
              "H'BB46",
              "H'BEC5"
            ]
          },
          "resend_countdown": {
            "address": 63944,
            "address_hex": "H'F9C8",
            "reload_value_candidate": 20,
            "reload_value_hex": "H'14",
            "summary": "Candidate periodic resend countdown/retry spacing value.",
            "evidence_addresses": [
              47948
            ],
            "evidence_addresses_hex": [
              "H'BB4C"
            ]
          },
          "pending_mask": {
            "address": 64163,
            "address_hex": "H'FAA3",
            "mask_candidate": 128,
            "mask_hex": "H'80",
            "summary": "Candidate bit/mask that marks an autonomous report pending.",
            "evidence_addresses": [
              47953,
              48843
            ],
            "evidence_addresses_hex": [
              "H'BB51",
              "H'BECB"
            ]
          },
          "resend_path": {
            "entry_label": "loc_BED5",
            "entry_address": 48853,
            "entry_address_hex": "H'BED5",
            "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.",
            "evidence_addresses": [
              48853
            ],
            "evidence_addresses_hex": [
              "H'BED5"
            ]
          },
          "evidence_addresses": [
            47942,
            48837,
            47948,
            47953,
            48843,
            48853
          ],
          "evidence_addresses_hex": [
            "H'BB46",
            "H'BEC5",
            "H'BB4C",
            "H'BB51",
            "H'BECB",
            "H'BED5"
          ],
          "confidence": "candidate-medium",
          "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing."
        },
        "timer_interrupt_model": {
          "kind": "timer_interrupt_model_candidate",
          "source": "FRT1 OCIA / FRT2 OCIA",
          "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.",
          "sources": [
            {
              "source": "FRT1 OCIA",
              "vector_address_hex": "H'0062",
              "handler_address": 48874,
              "handler_address_hex": "H'BEEA",
              "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.",
              "counters": [
                {
                  "address": 63936,
                  "address_hex": "H'F9C0",
                  "name_candidate": "tx_report_gate_counter_candidate",
                  "role": "candidate gate counter used before entering the report builder.",
                  "evidence_address": 48884,
                  "evidence_address_hex": "H'BEF4"
                },
                {
                  "address": 63937,
                  "address_hex": "H'F9C1",
                  "name_candidate": "rx_interbyte_timeout_candidate",
                  "role": "candidate RX interbyte timeout counter.",
                  "evidence_address": 48894,
                  "evidence_address_hex": "H'BEFE"
                },
                {
                  "address": 63942,
                  "address_hex": "H'F9C6",
                  "name_candidate": "periodic_resend_cadence_counter_candidate",
                  "role": "candidate periodic resend/heartbeat cadence counter.",
                  "evidence_address": 48904,
                  "evidence_address_hex": "H'BF08"
                }
              ],
              "evidence_addresses": [
                48874,
                48878,
                48882,
                48884,
                48888,
                48892,
                48894,
                48898,
                48902,
                48904
              ],
              "evidence_addresses_hex": [
                "H'BEEA",
                "H'BEEE",
                "H'BEF2",
                "H'BEF4",
                "H'BEF8",
                "H'BEFC",
                "H'BEFE",
                "H'BF02",
                "H'BF06",
                "H'BF08"
              ]
            },
            {
              "source": "FRT2 OCIA",
              "vector_address_hex": "H'006A",
              "handler_address": 48931,
              "handler_address_hex": "H'BF23",
              "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.",
              "clock_select": "CKS1=1 CKS0=0 => phi/32",
              "ocra_value_hex": "H'7A12",
              "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select",
              "counters": [
                {
                  "address": 63940,
                  "address_hex": "H'F9C4",
                  "name_candidate": "idle_heartbeat_gate_countdown_candidate",
                  "role": "candidate idle/default report enqueue countdown.",
                  "evidence_address": 48941,
                  "evidence_address_hex": "H'BF2D"
                },
                {
                  "address": 63941,
                  "address_hex": "H'F9C5",
                  "name_candidate": "rx_session_timeout_candidate",
                  "role": "candidate RX/session maintenance timeout counter.",
                  "evidence_address": 48951,
                  "evidence_address_hex": "H'BF37"
                }
              ],
              "evidence_addresses": [
                48931,
                48935,
                48939,
                48941,
                48945,
                48949,
                48951
              ],
              "evidence_addresses_hex": [
                "H'BF23",
                "H'BF27",
                "H'BF2B",
                "H'BF2D",
                "H'BF31",
                "H'BF35",
                "H'BF37"
              ]
            }
          ],
          "counters": [
            {
              "address": 63936,
              "address_hex": "H'F9C0",
              "name_candidate": "tx_report_gate_counter_candidate",
              "role": "candidate gate counter used before entering the report builder.",
              "evidence_address": 48884,
              "evidence_address_hex": "H'BEF4"
            },
            {
              "address": 63937,
              "address_hex": "H'F9C1",
              "name_candidate": "rx_interbyte_timeout_candidate",
              "role": "candidate RX interbyte timeout counter.",
              "evidence_address": 48894,
              "evidence_address_hex": "H'BEFE"
            },
            {
              "address": 63942,
              "address_hex": "H'F9C6",
              "name_candidate": "periodic_resend_cadence_counter_candidate",
              "role": "candidate periodic resend/heartbeat cadence counter.",
              "evidence_address": 48904,
              "evidence_address_hex": "H'BF08"
            },
            {
              "address": 63940,
              "address_hex": "H'F9C4",
              "name_candidate": "idle_heartbeat_gate_countdown_candidate",
              "role": "candidate idle/default report enqueue countdown.",
              "evidence_address": 48941,
              "evidence_address_hex": "H'BF2D"
            },
            {
              "address": 63941,
              "address_hex": "H'F9C5",
              "name_candidate": "rx_session_timeout_candidate",
              "role": "candidate RX/session maintenance timeout counter.",
              "evidence_address": 48951,
              "evidence_address_hex": "H'BF37"
            }
          ],
          "evidence_addresses": [
            48874,
            48878,
            48882,
            48884,
            48888,
            48892,
            48894,
            48898,
            48902,
            48904,
            48931,
            48935,
            48939,
            48941,
            48945,
            48949,
            48951
          ],
          "evidence_addresses_hex": [
            "H'BEEA",
            "H'BEEE",
            "H'BEF2",
            "H'BEF4",
            "H'BEF8",
            "H'BEFC",
            "H'BEFE",
            "H'BF02",
            "H'BF06",
            "H'BF08",
            "H'BF23",
            "H'BF27",
            "H'BF2B",
            "H'BF2D",
            "H'BF31",
            "H'BF35",
            "H'BF37"
          ],
          "confidence": "candidate-medium"
        },
        "evidence": [
          {
            "kind": "rx_frame_reconstruction_present",
            "summary": "serial_reconstruction contains an evidence-supported SCI1 RX frame candidate",
            "candidate_id": "sci1_rx_frame_f868_len6_candidate"
          },
          {
            "kind": "tx_frame_reconstruction_present",
            "summary": "serial_reconstruction contains an evidence-supported SCI1 TX frame candidate",
            "candidate_id": "sci1_tx_frame_f858_len6_candidate"
          },
          {
            "kind": "rx0_masked_command_dispatch",
            "summary": "RX[0] is read, masked with 0x07, and compared against command values",
            "addresses": [
              48136,
              48140,
              48160,
              48162,
              48164,
              48166,
              48169,
              48171,
              48174,
              48176,
              48197,
              48199,
              48202,
              48204,
              48207,
              48209,
              48212,
              48214
            ],
            "addresses_hex": [
              "H'BC08",
              "H'BC0C",
              "H'BC20",
              "H'BC22",
              "H'BC24",
              "H'BC26",
              "H'BC29",
              "H'BC2B",
              "H'BC2E",
              "H'BC30",
              "H'BC45",
              "H'BC47",
              "H'BC4A",
              "H'BC4C",
              "H'BC4F",
              "H'BC51",
              "H'BC54",
              "H'BC56"
            ]
          },
          {
            "kind": "responses_stage_f850_f854_before_send",
            "summary": "F850-F854 writes are observed before calls to loc_BA26",
            "addresses": [
              47900,
              47904,
              47915,
              47929,
              47935,
              47939,
              48304,
              48313,
              48321,
              48329,
              48309,
              48317,
              48325,
              48333,
              48343,
              48352,
              48360,
              48368,
              48374,
              48348,
              48356,
              48378,
              48649,
              48657,
              48665,
              48674,
              48717,
              48726,
              48734,
              48742,
              48722,
              48730,
              48738,
              48746
            ],
            "addresses_hex": [
              "H'BB1C",
              "H'BB20",
              "H'BB2B",
              "H'BB39",
              "H'BB3F",
              "H'BB43",
              "H'BCB0",
              "H'BCB9",
              "H'BCC1",
              "H'BCC9",
              "H'BCB5",
              "H'BCBD",
              "H'BCC5",
              "H'BCCD",
              "H'BCD7",
              "H'BCE0",
              "H'BCE8",
              "H'BCF0",
              "H'BCF6",
              "H'BCDC",
              "H'BCE4",
              "H'BCFA",
              "H'BE09",
              "H'BE11",
              "H'BE19",
              "H'BE22",
              "H'BE4D",
              "H'BE56",
              "H'BE5E",
              "H'BE66",
              "H'BE52",
              "H'BE5A",
              "H'BE62",
              "H'BE6A"
            ],
            "response_count": 5
          },
          {
            "kind": "bb43_autonomous_tx_report_path",
            "summary": "BB43 stages a candidate device-to-host report before loc_BA26; this is separate from RX command dispatch.",
            "addresses": [
              47900,
              47904,
              47915,
              47929,
              47935,
              47939
            ],
            "addresses_hex": [
              "H'BB1C",
              "H'BB20",
              "H'BB2B",
              "H'BB39",
              "H'BB3F",
              "H'BB43"
            ]
          },
          {
            "kind": "rx_payload_bytes_read",
            "summary": "RX[1..4] are read in the command-processing region",
            "addresses": [
              48092,
              48096,
              48100,
              48104,
              48119,
              48125,
              48153,
              48190,
              48237,
              48267,
              48273,
              48309,
              48317,
              48325,
              48348,
              48356,
              48402,
              48427,
              48433,
              48603,
              48609,
              48722,
              48730,
              48738
            ],
            "addresses_hex": [
              "H'BBDC",
              "H'BBE0",
              "H'BBE4",
              "H'BBE8",
              "H'BBF7",
              "H'BBFD",
              "H'BC19",
              "H'BC3E",
              "H'BC6D",
              "H'BC8B",
              "H'BC91",
              "H'BCB5",
              "H'BCBD",
              "H'BCC5",
              "H'BCDC",
              "H'BCE4",
              "H'BD12",
              "H'BD2B",
              "H'BD31",
              "H'BDDB",
              "H'BDE1",
              "H'BE52",
              "H'BE5A",
              "H'BE62"
            ]
          }
        ]
      }
    ],
    "fields": [
      {
        "id": "rx_0",
        "kind": "rx_frame_field_candidate",
        "offset": 0,
        "address": 63584,
        "address_hex": "H'F860",
        "role_candidate": "command_selector_candidate",
        "evidence_addresses": [
          48088,
          48136,
          48055,
          48160,
          48162,
          48164,
          48197,
          48166,
          48199,
          48169,
          48202,
          48171,
          48140,
          48204,
          48174,
          48207,
          48176,
          48209,
          48212,
          48214
        ],
        "evidence_addresses_hex": [
          "H'BBD8",
          "H'BC08",
          "H'BBB7",
          "H'BC20",
          "H'BC22",
          "H'BC24",
          "H'BC45",
          "H'BC26",
          "H'BC47",
          "H'BC29",
          "H'BC4A",
          "H'BC2B",
          "H'BC0C",
          "H'BC4C",
          "H'BC2E",
          "H'BC4F",
          "H'BC30",
          "H'BC51",
          "H'BC54",
          "H'BC56"
        ],
        "read_count": 2,
        "write_count": 2,
        "confidence": "medium",
        "caveat": "RX[0] is masked with 0x07 before command comparisons."
      },
      {
        "id": "rx_1",
        "kind": "rx_frame_field_candidate",
        "offset": 1,
        "address": 63585,
        "address_hex": "H'F861",
        "role_candidate": "payload_byte_candidate",
        "evidence_addresses": [
          48092,
          48119,
          48153,
          48190,
          48309,
          48348,
          48722
        ],
        "evidence_addresses_hex": [
          "H'BBDC",
          "H'BBF7",
          "H'BC19",
          "H'BC3E",
          "H'BCB5",
          "H'BCDC",
          "H'BE52"
        ],
        "read_count": 7,
        "write_count": 1,
        "confidence": "medium",
        "caveat": "Role is inferred from reads in command processing."
      },
      {
        "id": "rx_2",
        "kind": "rx_frame_field_candidate",
        "offset": 2,
        "address": 63586,
        "address_hex": "H'F862",
        "role_candidate": "payload_byte_candidate",
        "evidence_addresses": [
          48096,
          48125,
          48317,
          48356,
          48730,
          48063
        ],
        "evidence_addresses_hex": [
          "H'BBE0",
          "H'BBFD",
          "H'BCBD",
          "H'BCE4",
          "H'BE5A",
          "H'BBBF"
        ],
        "read_count": 5,
        "write_count": 2,
        "confidence": "medium",
        "caveat": "Role is inferred from reads in command processing."
      },
      {
        "id": "rx_3",
        "kind": "rx_frame_field_candidate",
        "offset": 3,
        "address": 63587,
        "address_hex": "H'F863",
        "role_candidate": "payload_byte_candidate",
        "evidence_addresses": [
          48100,
          48237,
          48267,
          48402,
          48427,
          48603
        ],
        "evidence_addresses_hex": [
          "H'BBE4",
          "H'BC6D",
          "H'BC8B",
          "H'BD12",
          "H'BD2B",
          "H'BDDB"
        ],
        "read_count": 6,
        "write_count": 1,
        "confidence": "medium",
        "caveat": "Role is inferred from reads in command processing."
      },
      {
        "id": "rx_4",
        "kind": "rx_frame_field_candidate",
        "offset": 4,
        "address": 63588,
        "address_hex": "H'F864",
        "role_candidate": "payload_byte_candidate",
        "evidence_addresses": [
          48104,
          48273,
          48325,
          48433,
          48609,
          48738,
          48071,
          48253
        ],
        "evidence_addresses_hex": [
          "H'BBE8",
          "H'BC91",
          "H'BCC5",
          "H'BD31",
          "H'BDE1",
          "H'BE62",
          "H'BBC7",
          "H'BC7D"
        ],
        "read_count": 6,
        "write_count": 3,
        "confidence": "medium",
        "caveat": "Role is inferred from reads in command processing."
      },
      {
        "id": "rx_5",
        "kind": "rx_frame_field_candidate",
        "offset": 5,
        "address": 63589,
        "address_hex": "H'F865",
        "role_candidate": "checksum_byte_candidate",
        "evidence_addresses": [
          48108
        ],
        "evidence_addresses_hex": [
          "H'BBEC"
        ],
        "read_count": 1,
        "write_count": 0,
        "confidence": "medium",
        "caveat": "RX[5] is compared with a checksum over RX[0..4]."
      },
      {
        "id": "tx_staging_0",
        "kind": "tx_staging_field_candidate",
        "offset": 0,
        "address": 63568,
        "address_hex": "H'F850",
        "role_candidate": "response_staging_byte_candidate",
        "evidence_addresses": [
          47900,
          48304,
          48343,
          48649,
          48717
        ],
        "evidence_addresses_hex": [
          "H'BB1C",
          "H'BCB0",
          "H'BCD7",
          "H'BE09",
          "H'BE4D"
        ],
        "write_count": 5,
        "confidence": "medium",
        "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
      },
      {
        "id": "tx_staging_1",
        "kind": "tx_staging_field_candidate",
        "offset": 1,
        "address": 63569,
        "address_hex": "H'F851",
        "role_candidate": "response_staging_byte_candidate",
        "evidence_addresses": [
          47915,
          48313,
          48352,
          48360,
          48649,
          48726
        ],
        "evidence_addresses_hex": [
          "H'BB2B",
          "H'BCB9",
          "H'BCE0",
          "H'BCE8",
          "H'BE09",
          "H'BE56"
        ],
        "write_count": 6,
        "confidence": "medium",
        "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
      },
      {
        "id": "tx_staging_2",
        "kind": "tx_staging_field_candidate",
        "offset": 2,
        "address": 63570,
        "address_hex": "H'F852",
        "role_candidate": "response_staging_byte_candidate",
        "evidence_addresses": [
          47904,
          48321,
          48657,
          48734
        ],
        "evidence_addresses_hex": [
          "H'BB20",
          "H'BCC1",
          "H'BE11",
          "H'BE5E"
        ],
        "write_count": 4,
        "confidence": "medium",
        "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
      },
      {
        "id": "tx_staging_3",
        "kind": "tx_staging_field_candidate",
        "offset": 3,
        "address": 63571,
        "address_hex": "H'F853",
        "role_candidate": "response_staging_byte_candidate",
        "evidence_addresses": [
          47935,
          48321,
          48374,
          48657,
          48734
        ],
        "evidence_addresses_hex": [
          "H'BB3F",
          "H'BCC1",
          "H'BCF6",
          "H'BE11",
          "H'BE5E"
        ],
        "write_count": 5,
        "confidence": "medium",
        "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
      },
      {
        "id": "tx_staging_4",
        "kind": "tx_staging_field_candidate",
        "offset": 4,
        "address": 63572,
        "address_hex": "H'F854",
        "role_candidate": "response_staging_byte_candidate",
        "evidence_addresses": [
          47929,
          48329,
          48368,
          48665,
          48742
        ],
        "evidence_addresses_hex": [
          "H'BB39",
          "H'BCC9",
          "H'BCF0",
          "H'BE19",
          "H'BE66"
        ],
        "write_count": 5,
        "confidence": "medium",
        "caveat": "This byte is staged before calls to loc_BA26; the analyzer does not infer a stable field name beyond response position."
      }
    ],
    "command_dispatch": {
      "kind": "command_dispatch_candidate",
      "selector": "rx0_low3_bits",
      "field": "command_low3",
      "rx_offset": 0,
      "rx_address": 63584,
      "rx_address_hex": "H'F860",
      "source_address": 63584,
      "source_address_hex": "H'F860",
      "source_field": "byte0",
      "mask": 7,
      "mask_hex": "H'0007",
      "selector_register": "R0",
      "read_address": 48136,
      "read_address_hex": "H'BC08",
      "mask_address": 48140,
      "mask_address_hex": "H'BC0C",
      "command_values": [
        0,
        1,
        2,
        4,
        5,
        6,
        7
      ],
      "command_values_hex": [
        "H'00",
        "H'01",
        "H'02",
        "H'04",
        "H'05",
        "H'06",
        "H'07"
      ],
      "comparisons": [
        {
          "command_value": 0,
          "command_value_hex": "H'00",
          "compare_address": 48160,
          "compare_address_hex": "H'BC20",
          "branch_address": 48162,
          "branch_address_hex": "H'BC22",
          "handler_start": 48233,
          "handler_start_hex": "H'BC69",
          "evidence_addresses": [
            48160,
            48162
          ],
          "evidence_addresses_hex": [
            "H'BC20",
            "H'BC22"
          ],
          "availability": "initial_idle_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 == 0"
          ],
          "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
          "handler_start_index": 2147
        },
        {
          "command_value": 1,
          "command_value_hex": "H'01",
          "compare_address": 48164,
          "compare_address_hex": "H'BC24",
          "branch_address": 48166,
          "branch_address_hex": "H'BC26",
          "handler_start": 48343,
          "handler_start_hex": "H'BCD7",
          "evidence_addresses": [
            48164,
            48166
          ],
          "evidence_addresses_hex": [
            "H'BC24",
            "H'BC26"
          ],
          "availability": "initial_idle_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 == 0",
            "F861.bit7 == 0"
          ],
          "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0",
          "handler_start_index": 2179
        },
        {
          "command_value": 2,
          "command_value_hex": "H'02",
          "compare_address": 48169,
          "compare_address_hex": "H'BC29",
          "branch_address": 48171,
          "branch_address_hex": "H'BC2B",
          "handler_start": 48388,
          "handler_start_hex": "H'BD04",
          "evidence_addresses": [
            48169,
            48171
          ],
          "evidence_addresses_hex": [
            "H'BC29",
            "H'BC2B"
          ],
          "availability": "initial_idle_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 == 0"
          ],
          "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
          "handler_start_index": 2191
        },
        {
          "command_value": 7,
          "command_value_hex": "H'07",
          "compare_address": 48174,
          "compare_address_hex": "H'BC2E",
          "branch_address": 48176,
          "branch_address_hex": "H'BC30",
          "handler_start": 48645,
          "handler_start_hex": "H'BE05",
          "evidence_addresses": [
            48174,
            48176
          ],
          "evidence_addresses_hex": [
            "H'BC2E",
            "H'BC30"
          ],
          "availability": "initial_idle_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 == 0"
          ],
          "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
          "handler_start_index": 2275
        },
        {
          "command_value": 4,
          "command_value_hex": "H'04",
          "compare_address": 48197,
          "compare_address_hex": "H'BC45",
          "branch_address": 48199,
          "branch_address_hex": "H'BC47",
          "handler_start": 48398,
          "handler_start_hex": "H'BD0E",
          "evidence_addresses": [
            48197,
            48199
          ],
          "evidence_addresses_hex": [
            "H'BC45",
            "H'BC47"
          ],
          "availability": "continuation_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 != 0"
          ],
          "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
          "handler_start_index": 2194
        },
        {
          "command_value": 5,
          "command_value_hex": "H'05",
          "compare_address": 48202,
          "compare_address_hex": "H'BC4A",
          "branch_address": 48204,
          "branch_address_hex": "H'BC4C",
          "handler_start": 48512,
          "handler_start_hex": "H'BD80",
          "evidence_addresses": [
            48202,
            48204
          ],
          "evidence_addresses_hex": [
            "H'BC4A",
            "H'BC4C"
          ],
          "availability": "continuation_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 != 0"
          ],
          "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
          "handler_start_index": 2231
        },
        {
          "command_value": 6,
          "command_value_hex": "H'06",
          "compare_address": 48207,
          "compare_address_hex": "H'BC4F",
          "branch_address": 48209,
          "branch_address_hex": "H'BC51",
          "handler_start": 48603,
          "handler_start_hex": "H'BDDB",
          "evidence_addresses": [
            48207,
            48209
          ],
          "evidence_addresses_hex": [
            "H'BC4F",
            "H'BC51"
          ],
          "availability": "continuation_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 != 0"
          ],
          "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
          "handler_start_index": 2263
        },
        {
          "command_value": 7,
          "command_value_hex": "H'07",
          "compare_address": 48212,
          "compare_address_hex": "H'BC54",
          "branch_address": 48214,
          "branch_address_hex": "H'BC56",
          "handler_start": 48645,
          "handler_start_hex": "H'BE05",
          "evidence_addresses": [
            48212,
            48214
          ],
          "evidence_addresses_hex": [
            "H'BC54",
            "H'BC56"
          ],
          "availability": "continuation_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 != 0"
          ],
          "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
          "handler_start_index": 2275
        }
      ],
      "state_split": {
        "kind": "serial_command_dispatch_state_split",
        "state_address": 64162,
        "state_address_hex": "H'FAA2",
        "test_address": 48143,
        "test_address_hex": "H'BC0F",
        "branch_address": 48147,
        "branch_address_hex": "H'BC13",
        "continuation_target": 48186,
        "continuation_target_hex": "H'BC3A",
        "initial_idle_commands": [
          0,
          1,
          2,
          7
        ],
        "initial_idle_commands_hex": [
          "H'00",
          "H'01",
          "H'02",
          "H'07"
        ],
        "continuation_commands": [
          4,
          5,
          6,
          7
        ],
        "continuation_commands_hex": [
          "H'04",
          "H'05",
          "H'06",
          "H'07"
        ],
        "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.",
        "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.",
        "evidence_addresses": [
          48143,
          48147
        ],
        "evidence_addresses_hex": [
          "H'BC0F",
          "H'BC13"
        ]
      },
      "dispatcher_split": {
        "kind": "serial_command_dispatch_state_split",
        "state_address": 64162,
        "state_address_hex": "H'FAA2",
        "test_address": 48143,
        "test_address_hex": "H'BC0F",
        "branch_address": 48147,
        "branch_address_hex": "H'BC13",
        "continuation_target": 48186,
        "continuation_target_hex": "H'BC3A",
        "initial_idle_commands": [
          0,
          1,
          2,
          7
        ],
        "initial_idle_commands_hex": [
          "H'00",
          "H'01",
          "H'02",
          "H'07"
        ],
        "continuation_commands": [
          4,
          5,
          6,
          7
        ],
        "continuation_commands_hex": [
          "H'04",
          "H'05",
          "H'06",
          "H'07"
        ],
        "summary": "FAA2 == 0 takes the initial/idle dispatcher path; FAA2 != 0 takes the continuation dispatcher path.",
        "caveat": "Initial dispatch follows checksum validation and RX error handling. Command 1 is only on the initial/idle path and is also gated by F861.bit7 == 0.",
        "evidence_addresses": [
          48143,
          48147
        ],
        "evidence_addresses_hex": [
          "H'BC0F",
          "H'BC13"
        ]
      },
      "cases": [
        {
          "value": 0,
          "value_hex": "H'00",
          "target": 48233,
          "target_hex": "H'BC69",
          "compare_address": 48160,
          "branch_address": 48162,
          "availability": "initial_idle_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 == 0"
          ]
        },
        {
          "value": 1,
          "value_hex": "H'01",
          "target": 48343,
          "target_hex": "H'BCD7",
          "compare_address": 48164,
          "branch_address": 48166,
          "availability": "initial_idle_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 == 0",
            "F861.bit7 == 0"
          ]
        },
        {
          "value": 2,
          "value_hex": "H'02",
          "target": 48388,
          "target_hex": "H'BD04",
          "compare_address": 48169,
          "branch_address": 48171,
          "availability": "initial_idle_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 == 0"
          ]
        },
        {
          "value": 7,
          "value_hex": "H'07",
          "target": 48645,
          "target_hex": "H'BE05",
          "compare_address": 48174,
          "branch_address": 48176,
          "availability": "initial_idle_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 == 0"
          ]
        },
        {
          "value": 4,
          "value_hex": "H'04",
          "target": 48398,
          "target_hex": "H'BD0E",
          "compare_address": 48197,
          "branch_address": 48199,
          "availability": "continuation_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 != 0"
          ]
        },
        {
          "value": 5,
          "value_hex": "H'05",
          "target": 48512,
          "target_hex": "H'BD80",
          "compare_address": 48202,
          "branch_address": 48204,
          "availability": "continuation_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 != 0"
          ]
        },
        {
          "value": 6,
          "value_hex": "H'06",
          "target": 48603,
          "target_hex": "H'BDDB",
          "compare_address": 48207,
          "branch_address": 48209,
          "availability": "continuation_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 != 0"
          ]
        },
        {
          "value": 7,
          "value_hex": "H'07",
          "target": 48645,
          "target_hex": "H'BE05",
          "compare_address": 48212,
          "branch_address": 48214,
          "availability": "continuation_dispatch",
          "availability_conditions": [
            "valid checksum/no RX physical error",
            "FAA2 != 0"
          ]
        }
      ],
      "evidence_addresses": [
        48136,
        48140,
        48160,
        48162,
        48164,
        48166,
        48169,
        48171,
        48174,
        48176,
        48197,
        48199,
        48202,
        48204,
        48207,
        48209,
        48212,
        48214
      ],
      "confidence": "medium",
      "caveat": "Dispatch is inferred from a read of RX[0], an AND 0x07 mask, and nearby compare/branch pairs. Gating state around the dispatch may affect reachability.",
      "evidence_addresses_hex": [
        "H'BC08",
        "H'BC0C",
        "H'BC20",
        "H'BC22",
        "H'BC24",
        "H'BC26",
        "H'BC29",
        "H'BC2B",
        "H'BC2E",
        "H'BC30",
        "H'BC45",
        "H'BC47",
        "H'BC4A",
        "H'BC4C",
        "H'BC4F",
        "H'BC51",
        "H'BC54",
        "H'BC56"
      ]
    },
    "commands": [
      {
        "kind": "command_candidate",
        "command_value": 0,
        "command_value_hex": "H'00",
        "name_candidate": "set_value_acked",
        "summary": "candidate write of RX[3:4] into primary/current tables, followed by a response",
        "handler_alternatives": [
          {
            "handler_start": 48233,
            "handler_start_hex": "H'BC69",
            "handler_end": 48340,
            "handler_end_hex": "H'BCD4",
            "dispatch_compare_address": 48160,
            "dispatch_compare_address_hex": "H'BC20",
            "dispatch_branch_address": 48162,
            "dispatch_branch_address_hex": "H'BC22",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0"
            ]
          }
        ],
        "evidence_addresses": [
          48136,
          48140,
          48160,
          48162,
          48304,
          48313,
          48321,
          48329,
          48309,
          48317,
          48325,
          48333
        ],
        "response_candidates": [
          "response_at_BCCD"
        ],
        "rx_reads": [
          {
            "instruction_address": 48237,
            "instruction_address_hex": "H'BC6D",
            "rx_offset": 3,
            "rx_address": 63587,
            "rx_address_hex": "H'F863",
            "instruction": "MOV:G.B @H'F863, R0"
          },
          {
            "instruction_address": 48267,
            "instruction_address_hex": "H'BC8B",
            "rx_offset": 3,
            "rx_address": 63587,
            "rx_address_hex": "H'F863",
            "instruction": "MOV:G.B @H'F863, R0"
          },
          {
            "instruction_address": 48273,
            "instruction_address_hex": "H'BC91",
            "rx_offset": 4,
            "rx_address": 63588,
            "rx_address_hex": "H'F864",
            "instruction": "MOV:G.B @H'F864, R0"
          },
          {
            "instruction_address": 48309,
            "instruction_address_hex": "H'BCB5",
            "rx_offset": 1,
            "rx_address": 63585,
            "rx_address_hex": "H'F861",
            "instruction": "MOV:G.B @H'F861, R0"
          },
          {
            "instruction_address": 48317,
            "instruction_address_hex": "H'BCBD",
            "rx_offset": 2,
            "rx_address": 63586,
            "rx_address_hex": "H'F862",
            "instruction": "MOV:G.W @H'F862, R0"
          },
          {
            "instruction_address": 48325,
            "instruction_address_hex": "H'BCC5",
            "rx_offset": 4,
            "rx_address": 63588,
            "rx_address_hex": "H'F864",
            "instruction": "MOV:G.B @H'F864, R0"
          }
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
        "handler_start": 48233,
        "handler_start_hex": "H'BC69",
        "handler_end": 48340,
        "handler_end_hex": "H'BCD4",
        "availability": "initial_idle_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 == 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
        "semantic_notes": [],
        "effects": [
          {
            "kind": "table_write_candidate",
            "target_candidate": "primary_value_table_candidate",
            "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero",
            "table_base": 57344,
            "table_base_hex": "H'E000",
            "evidence_addresses": [
              48245,
              48277
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BC75",
              "H'BC95"
            ]
          },
          {
            "kind": "table_write_candidate",
            "target_candidate": "current_value_table_candidate",
            "source_candidate": "same candidate value written to the primary table",
            "table_base": 59392,
            "table_base_hex": "H'E800",
            "evidence_addresses": [
              48249,
              48281
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BC79",
              "H'BC99"
            ]
          },
          {
            "kind": "flag_update_candidate",
            "target_candidate": "per_index_flag_table_candidate",
            "operation_candidate": "set bit 7",
            "table_base": 60416,
            "table_base_hex": "H'EC00",
            "evidence_addresses": [
              48258,
              48285
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BC82",
              "H'BC9D"
            ]
          },
          {
            "kind": "response_staging_candidate",
            "response_candidates": [
              "response_at_BCCD"
            ],
            "operation_candidate": "stage F850-F854 and call loc_BA26",
            "evidence_addresses": [
              48333
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BCCD"
            ]
          }
        ],
        "effect_summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.",
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC20",
          "H'BC22",
          "H'BCB0",
          "H'BCB9",
          "H'BCC1",
          "H'BCC9",
          "H'BCB5",
          "H'BCBD",
          "H'BCC5",
          "H'BCCD"
        ]
      },
      {
        "kind": "command_candidate",
        "command_value": 1,
        "command_value_hex": "H'01",
        "name_candidate": "read_value",
        "summary": "initial/idle-path primary table read only, followed by an odd response staging sequence",
        "handler_alternatives": [
          {
            "handler_start": 48343,
            "handler_start_hex": "H'BCD7",
            "handler_end": 48385,
            "handler_end_hex": "H'BD01",
            "dispatch_compare_address": 48164,
            "dispatch_compare_address_hex": "H'BC24",
            "dispatch_branch_address": 48166,
            "dispatch_branch_address_hex": "H'BC26",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0",
              "F861.bit7 == 0"
            ]
          }
        ],
        "evidence_addresses": [
          48136,
          48140,
          48164,
          48166,
          48343,
          48352,
          48360,
          48368,
          48374,
          48348,
          48356,
          48378
        ],
        "response_candidates": [
          "response_at_BCFA"
        ],
        "rx_reads": [
          {
            "instruction_address": 48348,
            "instruction_address_hex": "H'BCDC",
            "rx_offset": 1,
            "rx_address": 63585,
            "rx_address_hex": "H'F861",
            "instruction": "MOV:G.B @H'F861, R0"
          },
          {
            "instruction_address": 48356,
            "instruction_address_hex": "H'BCE4",
            "rx_offset": 2,
            "rx_address": 63586,
            "rx_address_hex": "H'F862",
            "instruction": "MOV:G.B @H'F862, R0"
          }
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
        "handler_start": 48343,
        "handler_start_hex": "H'BCD7",
        "handler_end": 48385,
        "handler_end_hex": "H'BD01",
        "availability": "initial_idle_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 == 0",
          "F861.bit7 == 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0",
        "semantic_notes": [
          "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.",
          "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.",
          "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.",
          "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame."
        ],
        "effects": [
          {
            "kind": "table_read_candidate",
            "target_candidate": "primary_value_table_candidate",
            "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7",
            "table_base": 57344,
            "table_base_hex": "H'E000",
            "address_expression_candidate": "E000 + 2*selector",
            "evidence_addresses": [
              48364
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BCEC"
            ]
          },
          {
            "kind": "response_staging_candidate",
            "response_candidates": [
              "response_at_BCFA"
            ],
            "operation_candidate": "stage F850-F854 and call loc_BA26",
            "evidence_addresses": [
              48378
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BCFA"
            ]
          }
        ],
        "effect_summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.",
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC24",
          "H'BC26",
          "H'BCD7",
          "H'BCE0",
          "H'BCE8",
          "H'BCF0",
          "H'BCF6",
          "H'BCDC",
          "H'BCE4",
          "H'BCFA"
        ]
      },
      {
        "kind": "command_candidate",
        "command_value": 2,
        "command_value_hex": "H'02",
        "name_candidate": "clear_or_abort",
        "summary": "candidate clear/abort path with no immediate response builder",
        "handler_alternatives": [
          {
            "handler_start": 48388,
            "handler_start_hex": "H'BD04",
            "handler_end": 48395,
            "handler_end_hex": "H'BD0B",
            "dispatch_compare_address": 48169,
            "dispatch_compare_address_hex": "H'BC29",
            "dispatch_branch_address": 48171,
            "dispatch_branch_address_hex": "H'BC2B",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0"
            ]
          }
        ],
        "evidence_addresses": [
          48136,
          48140,
          48169,
          48171
        ],
        "response_candidates": [],
        "rx_reads": [],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
        "handler_start": 48388,
        "handler_start_hex": "H'BD04",
        "handler_end": 48395,
        "handler_end_hex": "H'BD0B",
        "availability": "initial_idle_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 == 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
        "semantic_notes": [],
        "effects": [
          {
            "kind": "state_clear_candidate",
            "target_candidate": "serial_session_flags_candidate",
            "state_address": 64162,
            "state_address_hex": "H'FAA2",
            "operation_candidate": "clear bit 7",
            "evidence_addresses": [
              48388
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BD04"
            ]
          }
        ],
        "effect_summary": "Candidate clear/abort: clears serial session state without an observed immediate response.",
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC29",
          "H'BC2B"
        ]
      },
      {
        "kind": "command_candidate",
        "command_value": 4,
        "command_value_hex": "H'04",
        "name_candidate": "set_value_no_immediate_reply",
        "summary": "candidate write/update path that stores a value without an immediate serial response",
        "handler_alternatives": [
          {
            "handler_start": 48398,
            "handler_start_hex": "H'BD0E",
            "handler_end": 48509,
            "handler_end_hex": "H'BD7D",
            "dispatch_compare_address": 48197,
            "dispatch_compare_address_hex": "H'BC45",
            "dispatch_branch_address": 48199,
            "dispatch_branch_address_hex": "H'BC47",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ]
          }
        ],
        "evidence_addresses": [
          48136,
          48140,
          48197,
          48199
        ],
        "response_candidates": [],
        "rx_reads": [
          {
            "instruction_address": 48402,
            "instruction_address_hex": "H'BD12",
            "rx_offset": 3,
            "rx_address": 63587,
            "rx_address_hex": "H'F863",
            "instruction": "MOV:G.B @H'F863, R0"
          },
          {
            "instruction_address": 48427,
            "instruction_address_hex": "H'BD2B",
            "rx_offset": 3,
            "rx_address": 63587,
            "rx_address_hex": "H'F863",
            "instruction": "MOV:G.B @H'F863, R0"
          },
          {
            "instruction_address": 48433,
            "instruction_address_hex": "H'BD31",
            "rx_offset": 4,
            "rx_address": 63588,
            "rx_address_hex": "H'F864",
            "instruction": "MOV:G.B @H'F864, R0"
          }
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
        "handler_start": 48398,
        "handler_start_hex": "H'BD0E",
        "handler_end": 48509,
        "handler_end_hex": "H'BD7D",
        "availability": "continuation_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 != 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
        "semantic_notes": [],
        "effects": [
          {
            "kind": "table_write_candidate",
            "target_candidate": "primary_value_table_candidate",
            "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero",
            "table_base": 57344,
            "table_base_hex": "H'E000",
            "evidence_addresses": [
              48410,
              48437
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BD1A",
              "H'BD35"
            ]
          },
          {
            "kind": "flag_update_candidate",
            "target_candidate": "per_index_flag_table_candidate",
            "operation_candidate": "set bit 7",
            "table_base": 60416,
            "table_base_hex": "H'EC00",
            "evidence_addresses": [
              48418,
              48441
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BD22",
              "H'BD39"
            ]
          }
        ],
        "effect_summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.",
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC45",
          "H'BC47"
        ]
      },
      {
        "kind": "command_candidate",
        "command_value": 5,
        "command_value_hex": "H'05",
        "name_candidate": "ack_or_clear_pending",
        "summary": "continuation-only conditional acknowledgement/session clear path",
        "handler_alternatives": [
          {
            "handler_start": 48512,
            "handler_start_hex": "H'BD80",
            "handler_end": 48600,
            "handler_end_hex": "H'BDD8",
            "dispatch_compare_address": 48202,
            "dispatch_compare_address_hex": "H'BC4A",
            "dispatch_branch_address": 48204,
            "dispatch_branch_address_hex": "H'BC4C",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ]
          }
        ],
        "evidence_addresses": [
          48136,
          48140,
          48202,
          48204
        ],
        "response_candidates": [],
        "rx_reads": [],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
        "handler_start": 48512,
        "handler_start_hex": "H'BD80",
        "handler_end": 48600,
        "handler_end_hex": "H'BDD8",
        "availability": "continuation_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 != 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
        "semantic_notes": [
          "Only accepted on the continuation dispatcher path when FAA2 != 0.",
          "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.",
          "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.",
          "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work."
        ],
        "effects": [
          {
            "kind": "conditional_ack_session_clear_candidate",
            "target_candidate": "selected event/pending state",
            "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response",
            "selector_without_response_hex": "H'0040",
            "requires": [
              "FAA2 != 0"
            ],
            "fallthrough_when": "FAA2 == 0",
            "evidence_addresses": [
              48578,
              48596,
              48592,
              48584,
              48588
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BDC2",
              "H'BDD4",
              "H'BDD0",
              "H'BDC8",
              "H'BDCC"
            ]
          }
        ],
        "effect_summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.",
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC4A",
          "H'BC4C"
        ]
      },
      {
        "kind": "command_candidate",
        "command_value": 6,
        "command_value_hex": "H'06",
        "name_candidate": "set_secondary_value",
        "summary": "candidate secondary-table value write path",
        "handler_alternatives": [
          {
            "handler_start": 48603,
            "handler_start_hex": "H'BDDB",
            "handler_end": 48643,
            "handler_end_hex": "H'BE03",
            "dispatch_compare_address": 48207,
            "dispatch_compare_address_hex": "H'BC4F",
            "dispatch_branch_address": 48209,
            "dispatch_branch_address_hex": "H'BC51",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ]
          }
        ],
        "evidence_addresses": [
          48136,
          48140,
          48207,
          48209
        ],
        "response_candidates": [],
        "rx_reads": [
          {
            "instruction_address": 48603,
            "instruction_address_hex": "H'BDDB",
            "rx_offset": 3,
            "rx_address": 63587,
            "rx_address_hex": "H'F863",
            "instruction": "MOV:G.B @H'F863, R0"
          },
          {
            "instruction_address": 48609,
            "instruction_address_hex": "H'BDE1",
            "rx_offset": 4,
            "rx_address": 63588,
            "rx_address_hex": "H'F864",
            "instruction": "MOV:G.B @H'F864, R0"
          }
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
        "handler_start": 48603,
        "handler_start_hex": "H'BDDB",
        "handler_end": 48643,
        "handler_end_hex": "H'BE03",
        "availability": "continuation_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 != 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
        "semantic_notes": [],
        "effects": [
          {
            "kind": "table_write_candidate",
            "target_candidate": "secondary_value_table_candidate",
            "source_candidate": "RX[3:4] value bytes",
            "table_base": 58368,
            "table_base_hex": "H'E400",
            "evidence_addresses": [
              48613
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BDE5"
            ]
          },
          {
            "kind": "flag_update_candidate",
            "target_candidate": "per_index_flag_table_candidate",
            "operation_candidate": "set bit 6",
            "table_base": 60416,
            "table_base_hex": "H'EC00",
            "evidence_addresses": [
              48617
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BDE9"
            ]
          }
        ],
        "effect_summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.",
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC4F",
          "H'BC51"
        ]
      },
      {
        "kind": "command_candidate",
        "command_value": 7,
        "command_value_hex": "H'07",
        "name_candidate": "retransmit_or_error_reply",
        "summary": "candidate retransmit path; retry/error handling also builds a command 0x07 RX-payload echo",
        "handler_alternatives": [
          {
            "handler_start": 48645,
            "handler_start_hex": "H'BE05",
            "handler_end": 48677,
            "handler_end_hex": "H'BE25",
            "dispatch_compare_address": 48174,
            "dispatch_compare_address_hex": "H'BC2E",
            "dispatch_branch_address": 48176,
            "dispatch_branch_address_hex": "H'BC30",
            "availability": "initial_idle_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 == 0"
            ]
          },
          {
            "handler_start": 48645,
            "handler_start_hex": "H'BE05",
            "handler_end": 48677,
            "handler_end_hex": "H'BE25",
            "dispatch_compare_address": 48212,
            "dispatch_compare_address_hex": "H'BC54",
            "dispatch_branch_address": 48214,
            "dispatch_branch_address_hex": "H'BC56",
            "availability": "continuation_dispatch",
            "availability_conditions": [
              "valid checksum/no RX physical error",
              "FAA2 != 0"
            ]
          }
        ],
        "evidence_addresses": [
          48136,
          48140,
          48174,
          48176,
          48212,
          48214,
          48649,
          48657,
          48665,
          48674
        ],
        "response_candidates": [
          "response_at_BE22"
        ],
        "rx_reads": [],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted.",
        "handler_start": 48645,
        "handler_start_hex": "H'BE05",
        "handler_end": 48677,
        "handler_end_hex": "H'BE25",
        "availability": [
          "initial_idle_dispatch",
          "continuation_dispatch"
        ],
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 == 0",
          "FAA2 != 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0",
        "semantic_notes": [
          "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.",
          "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value."
        ],
        "effects": [
          {
            "kind": "retransmit_candidate",
            "source_candidate": "previous TX frame bytes H'F858-H'F85C",
            "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26",
            "response_candidates": [
              "response_at_BE22"
            ],
            "evidence_addresses": [
              48645,
              48649,
              48653,
              48657,
              48661,
              48665,
              48669,
              48674
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BE05",
              "H'BE09",
              "H'BE0D",
              "H'BE11",
              "H'BE15",
              "H'BE19",
              "H'BE1D",
              "H'BE22"
            ]
          },
          {
            "kind": "retry_error_echo_candidate",
            "source_candidate": "RX payload bytes F861-F864",
            "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26",
            "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value",
            "response_candidates": [],
            "evidence_addresses": [],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": []
          },
          {
            "kind": "response_staging_candidate",
            "response_candidates": [
              "response_at_BE22"
            ],
            "operation_candidate": "stage F850-F854 and call loc_BA26",
            "evidence_addresses": [
              48674
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BE22"
            ]
          }
        ],
        "effect_summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.",
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC2E",
          "H'BC30",
          "H'BC54",
          "H'BC56",
          "H'BE09",
          "H'BE11",
          "H'BE19",
          "H'BE22"
        ]
      }
    ],
    "command_effects": [
      {
        "kind": "command_effects_candidate",
        "command_value": 0,
        "command_value_hex": "H'00",
        "name_candidate": "set_value_acked",
        "summary": "Candidate acknowledged set: writes value bytes to primary/current tables, flags the index, and stages an echo-style response.",
        "availability": "initial_idle_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 == 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
        "semantic_notes": [],
        "effects": [
          {
            "kind": "table_write_candidate",
            "target_candidate": "primary_value_table_candidate",
            "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero",
            "table_base": 57344,
            "table_base_hex": "H'E000",
            "evidence_addresses": [
              48245,
              48277
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BC75",
              "H'BC95"
            ]
          },
          {
            "kind": "table_write_candidate",
            "target_candidate": "current_value_table_candidate",
            "source_candidate": "same candidate value written to the primary table",
            "table_base": 59392,
            "table_base_hex": "H'E800",
            "evidence_addresses": [
              48249,
              48281
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BC79",
              "H'BC99"
            ]
          },
          {
            "kind": "flag_update_candidate",
            "target_candidate": "per_index_flag_table_candidate",
            "operation_candidate": "set bit 7",
            "table_base": 60416,
            "table_base_hex": "H'EC00",
            "evidence_addresses": [
              48258,
              48285
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BC82",
              "H'BC9D"
            ]
          },
          {
            "kind": "response_staging_candidate",
            "response_candidates": [
              "response_at_BCCD"
            ],
            "operation_candidate": "stage F850-F854 and call loc_BA26",
            "evidence_addresses": [
              48333
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BCCD"
            ]
          }
        ],
        "response_candidates": [
          "response_at_BCCD"
        ],
        "evidence_addresses": [
          48136,
          48140,
          48160,
          48162,
          48304,
          48313,
          48321,
          48329,
          48309,
          48317,
          48325,
          48333
        ],
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC20",
          "H'BC22",
          "H'BCB0",
          "H'BCB9",
          "H'BCC1",
          "H'BCC9",
          "H'BCB5",
          "H'BCBD",
          "H'BCC5",
          "H'BCCD"
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
      },
      {
        "kind": "command_effects_candidate",
        "command_value": 1,
        "command_value_hex": "H'01",
        "name_candidate": "read_value",
        "summary": "Initial/idle candidate read: reads the primary table and stages an odd value response with F852 possibly stale.",
        "availability": "initial_idle_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 == 0",
          "F861.bit7 == 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 && F861.bit7 == 0",
        "semantic_notes": [
          "Only accepted on the initial/idle dispatcher path: valid checksum/no RX error, FAA2 == 0, and F861.bit7 == 0.",
          "BCD7 stages F850=0x04, writes F851 from F861 and then overwrites F851 from F862.",
          "BCD7 reads the primary table word at E000 + 2*selector; F854 receives the low byte and F853 receives the high byte.",
          "F852 is not freshly written in the BCD7 handler, so do not describe the response as a fixed 04 00 QQ hi lo frame."
        ],
        "effects": [
          {
            "kind": "table_read_candidate",
            "target_candidate": "primary_value_table_candidate",
            "destination_candidate": "response value bytes F854/F853, with F852 not freshly written by BCD7",
            "table_base": 57344,
            "table_base_hex": "H'E000",
            "address_expression_candidate": "E000 + 2*selector",
            "evidence_addresses": [
              48364
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BCEC"
            ]
          },
          {
            "kind": "response_staging_candidate",
            "response_candidates": [
              "response_at_BCFA"
            ],
            "operation_candidate": "stage F850-F854 and call loc_BA26",
            "evidence_addresses": [
              48378
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BCFA"
            ]
          }
        ],
        "response_candidates": [
          "response_at_BCFA"
        ],
        "evidence_addresses": [
          48136,
          48140,
          48164,
          48166,
          48343,
          48352,
          48360,
          48368,
          48374,
          48348,
          48356,
          48378
        ],
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC24",
          "H'BC26",
          "H'BCD7",
          "H'BCE0",
          "H'BCE8",
          "H'BCF0",
          "H'BCF6",
          "H'BCDC",
          "H'BCE4",
          "H'BCFA"
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
      },
      {
        "kind": "command_effects_candidate",
        "command_value": 2,
        "command_value_hex": "H'02",
        "name_candidate": "clear_or_abort",
        "summary": "Candidate clear/abort: clears serial session state without an observed immediate response.",
        "availability": "initial_idle_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 == 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 == 0",
        "semantic_notes": [],
        "effects": [
          {
            "kind": "state_clear_candidate",
            "target_candidate": "serial_session_flags_candidate",
            "state_address": 64162,
            "state_address_hex": "H'FAA2",
            "operation_candidate": "clear bit 7",
            "evidence_addresses": [
              48388
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BD04"
            ]
          }
        ],
        "response_candidates": [],
        "evidence_addresses": [
          48136,
          48140,
          48169,
          48171
        ],
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC29",
          "H'BC2B"
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
      },
      {
        "kind": "command_effects_candidate",
        "command_value": 4,
        "command_value_hex": "H'04",
        "name_candidate": "set_value_no_immediate_reply",
        "summary": "Candidate deferred set: writes value bytes and flags the index without an observed immediate response.",
        "availability": "continuation_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 != 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
        "semantic_notes": [],
        "effects": [
          {
            "kind": "table_write_candidate",
            "target_candidate": "primary_value_table_candidate",
            "source_candidate": "RX[3:4] value bytes, with an observed 0x80 fallback when decoded index is zero",
            "table_base": 57344,
            "table_base_hex": "H'E000",
            "evidence_addresses": [
              48410,
              48437
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BD1A",
              "H'BD35"
            ]
          },
          {
            "kind": "flag_update_candidate",
            "target_candidate": "per_index_flag_table_candidate",
            "operation_candidate": "set bit 7",
            "table_base": 60416,
            "table_base_hex": "H'EC00",
            "evidence_addresses": [
              48418,
              48441
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BD22",
              "H'BD39"
            ]
          }
        ],
        "response_candidates": [],
        "evidence_addresses": [
          48136,
          48140,
          48197,
          48199
        ],
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC45",
          "H'BC47"
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
      },
      {
        "kind": "command_effects_candidate",
        "command_value": 5,
        "command_value_hex": "H'05",
        "name_candidate": "ack_or_clear_pending",
        "summary": "Continuation-only ACK/session clear: clears FAA3/FAA2 and only advances F9B5 when queued-report FAA2.bit3 was set; selector 0x0040 has no response.",
        "availability": "continuation_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 != 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
        "semantic_notes": [
          "Only accepted on the continuation dispatcher path when FAA2 != 0.",
          "For selector 0x0040, frame 05 00 40 00 00 1F performs no response staging.",
          "The handler clears FAA3/FAA2; F9B5 advances only when FAA2.bit3 was set from a queued report.",
          "If FAA2 == 0, command 5 falls through the initial dispatcher instead of doing acknowledgement work."
        ],
        "effects": [
          {
            "kind": "conditional_ack_session_clear_candidate",
            "target_candidate": "selected event/pending state",
            "operation_candidate": "when FAA2 != 0, clear FAA3/FAA2; advance F9B5 only if FAA2.bit3 was set from queued-report state; selector 0x0040 stages no response",
            "selector_without_response_hex": "H'0040",
            "requires": [
              "FAA2 != 0"
            ],
            "fallthrough_when": "FAA2 == 0",
            "evidence_addresses": [
              48578,
              48596,
              48592,
              48584,
              48588
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BDC2",
              "H'BDD4",
              "H'BDD0",
              "H'BDC8",
              "H'BDCC"
            ]
          }
        ],
        "response_candidates": [],
        "evidence_addresses": [
          48136,
          48140,
          48202,
          48204
        ],
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC4A",
          "H'BC4C"
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
      },
      {
        "kind": "command_effects_candidate",
        "command_value": 6,
        "command_value_hex": "H'06",
        "name_candidate": "set_secondary_value",
        "summary": "Candidate secondary set: writes value bytes to the secondary table and flags the index.",
        "availability": "continuation_dispatch",
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 != 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 != 0",
        "semantic_notes": [],
        "effects": [
          {
            "kind": "table_write_candidate",
            "target_candidate": "secondary_value_table_candidate",
            "source_candidate": "RX[3:4] value bytes",
            "table_base": 58368,
            "table_base_hex": "H'E400",
            "evidence_addresses": [
              48613
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BDE5"
            ]
          },
          {
            "kind": "flag_update_candidate",
            "target_candidate": "per_index_flag_table_candidate",
            "operation_candidate": "set bit 6",
            "table_base": 60416,
            "table_base_hex": "H'EC00",
            "evidence_addresses": [
              48617
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BDE9"
            ]
          }
        ],
        "response_candidates": [],
        "evidence_addresses": [
          48136,
          48140,
          48207,
          48209
        ],
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC4F",
          "H'BC51"
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
      },
      {
        "kind": "command_effects_candidate",
        "command_value": 7,
        "command_value_hex": "H'07",
        "name_candidate": "retransmit_or_error_reply",
        "summary": "Candidate retransmit/error reply: reuses prior TX bytes or copies RX payload bytes behind an explicit 0x07 retry/error echo.",
        "availability": [
          "initial_idle_dispatch",
          "continuation_dispatch"
        ],
        "availability_conditions": [
          "valid checksum/no RX physical error",
          "FAA2 == 0",
          "FAA2 != 0"
        ],
        "availability_summary": "valid checksum/no RX physical error && FAA2 == 0 OR valid checksum/no RX physical error && FAA2 != 0",
        "semantic_notes": [
          "loc_BE4D is a retry/error echo path: F850=0x07 and F861-F864 are copied into F851-F854 before loc_BA26.",
          "Observed frame 07 80 40 20 90 2D means RX bytes F861-F864 were 80 40 20 90; it is not a table value."
        ],
        "effects": [
          {
            "kind": "retransmit_candidate",
            "source_candidate": "previous TX frame bytes H'F858-H'F85C",
            "destination_candidate": "TX staging bytes H'F850-H'F854 before loc_BA26",
            "response_candidates": [
              "response_at_BE22"
            ],
            "evidence_addresses": [
              48645,
              48649,
              48653,
              48657,
              48661,
              48665,
              48669,
              48674
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BE05",
              "H'BE09",
              "H'BE0D",
              "H'BE11",
              "H'BE15",
              "H'BE19",
              "H'BE1D",
              "H'BE22"
            ]
          },
          {
            "kind": "retry_error_echo_candidate",
            "source_candidate": "RX payload bytes F861-F864",
            "destination_candidate": "F850=0x07, F851-F854=F861-F864 before loc_BA26",
            "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90; it is not a table value",
            "response_candidates": [],
            "evidence_addresses": [],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": []
          },
          {
            "kind": "response_staging_candidate",
            "response_candidates": [
              "response_at_BE22"
            ],
            "operation_candidate": "stage F850-F854 and call loc_BA26",
            "evidence_addresses": [
              48674
            ],
            "confidence": "candidate-medium",
            "caveat": "Effect is inferred from local data movement and remains a protocol candidate.",
            "evidence_addresses_hex": [
              "H'BE22"
            ]
          }
        ],
        "response_candidates": [
          "response_at_BE22"
        ],
        "evidence_addresses": [
          48136,
          48140,
          48174,
          48176,
          48212,
          48214,
          48649,
          48657,
          48665,
          48674
        ],
        "evidence_addresses_hex": [
          "H'BC08",
          "H'BC0C",
          "H'BC2E",
          "H'BC30",
          "H'BC54",
          "H'BC56",
          "H'BE09",
          "H'BE11",
          "H'BE19",
          "H'BE22"
        ],
        "confidence": "medium",
        "caveat": "Command value and handler range are inferred from compare/BEQ dispatch. No command name or intent is asserted."
      }
    ],
    "response_candidates": [
      {
        "id": "response_at_BB43",
        "kind": "response_staging_candidate",
        "call_address": 47939,
        "call_address_hex": "H'BB43",
        "send_builder": "loc_BA26",
        "send_builder_address": 47654,
        "send_builder_address_hex": "H'BA26",
        "window_start": 47872,
        "window_start_hex": "H'BB00",
        "writes": [
          {
            "instruction_address": 47900,
            "instruction_address_hex": "H'BB1C",
            "addresses": [
              63568
            ],
            "addresses_hex": [
              "H'F850"
            ],
            "source_operand": "R1",
            "source": {
              "kind": "register_or_computed",
              "operand": "R1",
              "source_category": "computed",
              "operation": "AND",
              "evidence_address": 47897,
              "evidence_address_hex": "H'BB19",
              "instruction": "AND.B #H'07, R1"
            },
            "instruction": "MOV:G.B R1, @H'F850"
          },
          {
            "instruction_address": 47904,
            "instruction_address_hex": "H'BB20",
            "addresses": [
              63570
            ],
            "addresses_hex": [
              "H'F852"
            ],
            "source_operand": "R5",
            "source": {
              "kind": "register_or_computed",
              "operand": "@(-H'0790,R0)",
              "source_category": "computed",
              "evidence_address": 47880,
              "evidence_address_hex": "H'BB08",
              "instruction": "MOV:G.W @(-H'0790,R0), R0"
            },
            "instruction": "MOV:G.B R5, @H'F852"
          },
          {
            "instruction_address": 47915,
            "instruction_address_hex": "H'BB2B",
            "addresses": [
              63569
            ],
            "addresses_hex": [
              "H'F851"
            ],
            "source_operand": "R5",
            "source": {
              "kind": "register_or_computed",
              "operand": "R5",
              "source_category": "computed",
              "operation": "OR",
              "evidence_address": 47913,
              "evidence_address_hex": "H'BB29",
              "instruction": "OR.B R2, R5"
            },
            "instruction": "MOV:G.B R5, @H'F851"
          },
          {
            "instruction_address": 47929,
            "instruction_address_hex": "H'BB39",
            "addresses": [
              63572
            ],
            "addresses_hex": [
              "H'F854"
            ],
            "source_operand": "R4",
            "source": {
              "name_candidate": "current_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 59392,
              "logical_base_address_hex": "H'E800",
              "negative_offset": 6144,
              "negative_offset_hex": "H'1800",
              "index_register": "R0",
              "operand": "@(-H'1800,R0)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 47925,
              "evidence_address_hex": "H'BB35",
              "instruction": "MOV:G.W @(-H'1800,R0), R4"
            },
            "instruction": "MOV:G.B R4, @H'F854"
          },
          {
            "instruction_address": 47935,
            "instruction_address_hex": "H'BB3F",
            "addresses": [
              63571
            ],
            "addresses_hex": [
              "H'F853"
            ],
            "source_operand": "R4",
            "source": {
              "name_candidate": "current_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 59392,
              "logical_base_address_hex": "H'E800",
              "negative_offset": 6144,
              "negative_offset_hex": "H'1800",
              "index_register": "R0",
              "operand": "@(-H'1800,R0)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 47925,
              "evidence_address_hex": "H'BB35",
              "instruction": "MOV:G.W @(-H'1800,R0), R4",
              "transforms": [
                "swap_bytes"
              ]
            },
            "instruction": "MOV:G.B R4, @H'F853"
          }
        ],
        "rx_reads": [],
        "evidence_addresses": [
          47900,
          47904,
          47915,
          47929,
          47935,
          47939
        ],
        "evidence_addresses_hex": [
          "H'BB1C",
          "H'BB20",
          "H'BB2B",
          "H'BB39",
          "H'BB3F",
          "H'BB43"
        ],
        "confidence": "medium",
        "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
        "schema": {
          "kind": "response_schema_candidate",
          "response_id": "response_at_BB43",
          "call_address": 47939,
          "call_address_hex": "H'BB43",
          "buffer_start": 63568,
          "buffer_start_hex": "H'F850",
          "buffer_end": 63572,
          "buffer_end_hex": "H'F854",
          "bytes": [
            {
              "offset": 0,
              "byte": "byte0",
              "tx_byte": "TX[0]",
              "tx_staging_byte": "TX[0]",
              "address": 63568,
              "address_hex": "H'F850",
              "source_kind": "computed",
              "source_expression": "computed",
              "source": {
                "kind": "register_or_computed",
                "operand": "R1",
                "source_category": "computed",
                "operation": "AND",
                "evidence_address": 47897,
                "evidence_address_hex": "H'BB19",
                "instruction": "AND.B #H'07, R1",
                "byte_index": 0
              },
              "write_instruction_address": 47900,
              "write_instruction_address_hex": "H'BB1C",
              "instruction": "MOV:G.B R1, @H'F850",
              "evidence_addresses": [
                47900
              ],
              "evidence_addresses_hex": [
                "H'BB1C"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 1,
              "byte": "byte1",
              "tx_byte": "TX[1]",
              "tx_staging_byte": "TX[1]",
              "address": 63569,
              "address_hex": "H'F851",
              "source_kind": "computed",
              "source_expression": "computed",
              "source": {
                "kind": "register_or_computed",
                "operand": "R5",
                "source_category": "computed",
                "operation": "OR",
                "evidence_address": 47913,
                "evidence_address_hex": "H'BB29",
                "instruction": "OR.B R2, R5",
                "byte_index": 0
              },
              "write_instruction_address": 47915,
              "write_instruction_address_hex": "H'BB2B",
              "instruction": "MOV:G.B R5, @H'F851",
              "evidence_addresses": [
                47915
              ],
              "evidence_addresses_hex": [
                "H'BB2B"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 2,
              "byte": "byte2",
              "tx_byte": "TX[2]",
              "tx_staging_byte": "TX[2]",
              "address": 63570,
              "address_hex": "H'F852",
              "source_kind": "computed",
              "source_expression": "computed",
              "source": {
                "kind": "register_or_computed",
                "operand": "@(-H'0790,R0)",
                "source_category": "computed",
                "evidence_address": 47880,
                "evidence_address_hex": "H'BB08",
                "instruction": "MOV:G.W @(-H'0790,R0), R0",
                "byte_index": 0
              },
              "write_instruction_address": 47904,
              "write_instruction_address_hex": "H'BB20",
              "instruction": "MOV:G.B R5, @H'F852",
              "evidence_addresses": [
                47904
              ],
              "evidence_addresses_hex": [
                "H'BB20"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 3,
              "byte": "byte3",
              "tx_byte": "TX[3]",
              "tx_staging_byte": "TX[3]",
              "address": 63571,
              "address_hex": "H'F853",
              "source_kind": "table",
              "source_expression": "current_value_table_candidate",
              "source": {
                "name_candidate": "current_value_table_candidate",
                "element_candidate": "word_value",
                "logical_base_address": 59392,
                "logical_base_address_hex": "H'E800",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R0",
                "operand": "@(-H'1800,R0)",
                "kind": "table",
                "access_width": 2,
                "evidence_address": 47925,
                "evidence_address_hex": "H'BB35",
                "instruction": "MOV:G.W @(-H'1800,R0), R4",
                "transforms": [
                  "swap_bytes"
                ],
                "byte_index": 0
              },
              "write_instruction_address": 47935,
              "write_instruction_address_hex": "H'BB3F",
              "instruction": "MOV:G.B R4, @H'F853",
              "evidence_addresses": [
                47935
              ],
              "evidence_addresses_hex": [
                "H'BB3F"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 4,
              "byte": "byte4",
              "tx_byte": "TX[4]",
              "tx_staging_byte": "TX[4]",
              "address": 63572,
              "address_hex": "H'F854",
              "source_kind": "table",
              "source_expression": "current_value_table_candidate",
              "source": {
                "name_candidate": "current_value_table_candidate",
                "element_candidate": "word_value",
                "logical_base_address": 59392,
                "logical_base_address_hex": "H'E800",
                "negative_offset": 6144,
                "negative_offset_hex": "H'1800",
                "index_register": "R0",
                "operand": "@(-H'1800,R0)",
                "kind": "table",
                "access_width": 2,
                "evidence_address": 47925,
                "evidence_address_hex": "H'BB35",
                "instruction": "MOV:G.W @(-H'1800,R0), R4",
                "byte_index": 0
              },
              "write_instruction_address": 47929,
              "write_instruction_address_hex": "H'BB39",
              "instruction": "MOV:G.B R4, @H'F854",
              "evidence_addresses": [
                47929
              ],
              "evidence_addresses_hex": [
                "H'BB39"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            }
          ],
          "semantic_notes": [],
          "evidence_addresses": [
            47900,
            47915,
            47904,
            47935,
            47929
          ],
          "evidence_addresses_hex": [
            "H'BB1C",
            "H'BB2B",
            "H'BB20",
            "H'BB3F",
            "H'BB39"
          ],
          "confidence": "candidate-medium",
          "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
        },
        "byte_schema": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "computed",
            "source_expression": "computed",
            "source": {
              "kind": "register_or_computed",
              "operand": "R1",
              "source_category": "computed",
              "operation": "AND",
              "evidence_address": 47897,
              "evidence_address_hex": "H'BB19",
              "instruction": "AND.B #H'07, R1",
              "byte_index": 0
            },
            "write_instruction_address": 47900,
            "write_instruction_address_hex": "H'BB1C",
            "instruction": "MOV:G.B R1, @H'F850",
            "evidence_addresses": [
              47900
            ],
            "evidence_addresses_hex": [
              "H'BB1C"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "computed",
            "source_expression": "computed",
            "source": {
              "kind": "register_or_computed",
              "operand": "R5",
              "source_category": "computed",
              "operation": "OR",
              "evidence_address": 47913,
              "evidence_address_hex": "H'BB29",
              "instruction": "OR.B R2, R5",
              "byte_index": 0
            },
            "write_instruction_address": 47915,
            "write_instruction_address_hex": "H'BB2B",
            "instruction": "MOV:G.B R5, @H'F851",
            "evidence_addresses": [
              47915
            ],
            "evidence_addresses_hex": [
              "H'BB2B"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "computed",
            "source_expression": "computed",
            "source": {
              "kind": "register_or_computed",
              "operand": "@(-H'0790,R0)",
              "source_category": "computed",
              "evidence_address": 47880,
              "evidence_address_hex": "H'BB08",
              "instruction": "MOV:G.W @(-H'0790,R0), R0",
              "byte_index": 0
            },
            "write_instruction_address": 47904,
            "write_instruction_address_hex": "H'BB20",
            "instruction": "MOV:G.B R5, @H'F852",
            "evidence_addresses": [
              47904
            ],
            "evidence_addresses_hex": [
              "H'BB20"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "table",
            "source_expression": "current_value_table_candidate",
            "source": {
              "name_candidate": "current_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 59392,
              "logical_base_address_hex": "H'E800",
              "negative_offset": 6144,
              "negative_offset_hex": "H'1800",
              "index_register": "R0",
              "operand": "@(-H'1800,R0)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 47925,
              "evidence_address_hex": "H'BB35",
              "instruction": "MOV:G.W @(-H'1800,R0), R4",
              "transforms": [
                "swap_bytes"
              ],
              "byte_index": 0
            },
            "write_instruction_address": 47935,
            "write_instruction_address_hex": "H'BB3F",
            "instruction": "MOV:G.B R4, @H'F853",
            "evidence_addresses": [
              47935
            ],
            "evidence_addresses_hex": [
              "H'BB3F"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "table",
            "source_expression": "current_value_table_candidate",
            "source": {
              "name_candidate": "current_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 59392,
              "logical_base_address_hex": "H'E800",
              "negative_offset": 6144,
              "negative_offset_hex": "H'1800",
              "index_register": "R0",
              "operand": "@(-H'1800,R0)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 47925,
              "evidence_address_hex": "H'BB35",
              "instruction": "MOV:G.W @(-H'1800,R0), R4",
              "byte_index": 0
            },
            "write_instruction_address": 47929,
            "write_instruction_address_hex": "H'BB39",
            "instruction": "MOV:G.B R4, @H'F854",
            "evidence_addresses": [
              47929
            ],
            "evidence_addresses_hex": [
              "H'BB39"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": []
      },
      {
        "id": "response_at_BCCD",
        "kind": "response_staging_candidate",
        "call_address": 48333,
        "call_address_hex": "H'BCCD",
        "send_builder": "loc_BA26",
        "send_builder_address": 47654,
        "send_builder_address_hex": "H'BA26",
        "window_start": 48297,
        "window_start_hex": "H'BCA9",
        "writes": [
          {
            "instruction_address": 48304,
            "instruction_address_hex": "H'BCB0",
            "addresses": [
              63568
            ],
            "addresses_hex": [
              "H'F850"
            ],
            "source_operand": "#H'04",
            "source": {
              "kind": "immediate",
              "value": 4,
              "value_hex": "H'04"
            },
            "instruction": "MOV:G.B #H'04, @H'F850"
          },
          {
            "instruction_address": 48313,
            "instruction_address_hex": "H'BCB9",
            "addresses": [
              63569
            ],
            "addresses_hex": [
              "H'F851"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 1,
              "rx_offsets": [
                1
              ],
              "rx_address": 63585,
              "rx_address_hex": "H'F861",
              "evidence_address": 48309,
              "evidence_address_hex": "H'BCB5",
              "instruction": "MOV:G.B @H'F861, R0"
            },
            "instruction": "MOV:G.B R0, @H'F851"
          },
          {
            "instruction_address": 48321,
            "instruction_address_hex": "H'BCC1",
            "addresses": [
              63570,
              63571
            ],
            "addresses_hex": [
              "H'F852",
              "H'F853"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "rx_frame_word",
              "rx_offset": 2,
              "rx_offsets": [
                2,
                3
              ],
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "evidence_address": 48317,
              "evidence_address_hex": "H'BCBD",
              "instruction": "MOV:G.W @H'F862, R0"
            },
            "instruction": "MOV:G.W R0, @H'F852"
          },
          {
            "instruction_address": 48329,
            "instruction_address_hex": "H'BCC9",
            "addresses": [
              63572
            ],
            "addresses_hex": [
              "H'F854"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 4,
              "rx_offsets": [
                4
              ],
              "rx_address": 63588,
              "rx_address_hex": "H'F864",
              "evidence_address": 48325,
              "evidence_address_hex": "H'BCC5",
              "instruction": "MOV:G.B @H'F864, R0"
            },
            "instruction": "MOV:G.B R0, @H'F854"
          }
        ],
        "rx_reads": [
          {
            "instruction_address": 48309,
            "instruction_address_hex": "H'BCB5",
            "rx_offset": 1,
            "rx_address": 63585,
            "rx_address_hex": "H'F861",
            "instruction": "MOV:G.B @H'F861, R0"
          },
          {
            "instruction_address": 48317,
            "instruction_address_hex": "H'BCBD",
            "rx_offset": 2,
            "rx_address": 63586,
            "rx_address_hex": "H'F862",
            "instruction": "MOV:G.W @H'F862, R0"
          },
          {
            "instruction_address": 48325,
            "instruction_address_hex": "H'BCC5",
            "rx_offset": 4,
            "rx_address": 63588,
            "rx_address_hex": "H'F864",
            "instruction": "MOV:G.B @H'F864, R0"
          }
        ],
        "evidence_addresses": [
          48304,
          48313,
          48321,
          48329,
          48309,
          48317,
          48325,
          48333
        ],
        "evidence_addresses_hex": [
          "H'BCB0",
          "H'BCB9",
          "H'BCC1",
          "H'BCC9",
          "H'BCB5",
          "H'BCBD",
          "H'BCC5",
          "H'BCCD"
        ],
        "confidence": "medium",
        "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
        "schema": {
          "kind": "response_schema_candidate",
          "response_id": "response_at_BCCD",
          "call_address": 48333,
          "call_address_hex": "H'BCCD",
          "buffer_start": 63568,
          "buffer_start_hex": "H'F850",
          "buffer_end": 63572,
          "buffer_end_hex": "H'F854",
          "bytes": [
            {
              "offset": 0,
              "byte": "byte0",
              "tx_byte": "TX[0]",
              "tx_staging_byte": "TX[0]",
              "address": 63568,
              "address_hex": "H'F850",
              "source_kind": "immediate",
              "source_expression": "0x04",
              "source": {
                "kind": "immediate",
                "value": 4,
                "value_hex": "H'04",
                "byte_index": 0
              },
              "write_instruction_address": 48304,
              "write_instruction_address_hex": "H'BCB0",
              "instruction": "MOV:G.B #H'04, @H'F850",
              "evidence_addresses": [
                48304
              ],
              "evidence_addresses_hex": [
                "H'BCB0"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 1,
              "byte": "byte1",
              "tx_byte": "TX[1]",
              "tx_staging_byte": "TX[1]",
              "address": 63569,
              "address_hex": "H'F851",
              "source_kind": "rx_frame_byte",
              "source_expression": "rx[1]",
              "source": {
                "kind": "rx_frame_byte",
                "rx_offset": 1,
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "derived_from": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_offsets": [
                    1
                  ],
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "evidence_address": 48309,
                  "evidence_address_hex": "H'BCB5",
                  "instruction": "MOV:G.B @H'F861, R0"
                }
              },
              "write_instruction_address": 48313,
              "write_instruction_address_hex": "H'BCB9",
              "instruction": "MOV:G.B R0, @H'F851",
              "evidence_addresses": [
                48313
              ],
              "evidence_addresses_hex": [
                "H'BCB9"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 2,
              "byte": "byte2",
              "tx_byte": "TX[2]",
              "tx_staging_byte": "TX[2]",
              "address": 63570,
              "address_hex": "H'F852",
              "source_kind": "rx_frame_byte",
              "source_expression": "rx[2]",
              "source": {
                "kind": "rx_frame_byte",
                "rx_offset": 2,
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "derived_from": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48317,
                  "evidence_address_hex": "H'BCBD",
                  "instruction": "MOV:G.W @H'F862, R0"
                }
              },
              "write_instruction_address": 48321,
              "write_instruction_address_hex": "H'BCC1",
              "instruction": "MOV:G.W R0, @H'F852",
              "evidence_addresses": [
                48321
              ],
              "evidence_addresses_hex": [
                "H'BCC1"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 3,
              "byte": "byte3",
              "tx_byte": "TX[3]",
              "tx_staging_byte": "TX[3]",
              "address": 63571,
              "address_hex": "H'F853",
              "source_kind": "rx_frame_byte",
              "source_expression": "rx[3]",
              "source": {
                "kind": "rx_frame_byte",
                "rx_offset": 3,
                "rx_address": 63587,
                "rx_address_hex": "H'F863",
                "derived_from": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48317,
                  "evidence_address_hex": "H'BCBD",
                  "instruction": "MOV:G.W @H'F862, R0"
                }
              },
              "write_instruction_address": 48321,
              "write_instruction_address_hex": "H'BCC1",
              "instruction": "MOV:G.W R0, @H'F852",
              "evidence_addresses": [
                48321
              ],
              "evidence_addresses_hex": [
                "H'BCC1"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 4,
              "byte": "byte4",
              "tx_byte": "TX[4]",
              "tx_staging_byte": "TX[4]",
              "address": 63572,
              "address_hex": "H'F854",
              "source_kind": "rx_frame_byte",
              "source_expression": "rx[4]",
              "source": {
                "kind": "rx_frame_byte",
                "rx_offset": 4,
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "derived_from": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_offsets": [
                    4
                  ],
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "evidence_address": 48325,
                  "evidence_address_hex": "H'BCC5",
                  "instruction": "MOV:G.B @H'F864, R0"
                }
              },
              "write_instruction_address": 48329,
              "write_instruction_address_hex": "H'BCC9",
              "instruction": "MOV:G.B R0, @H'F854",
              "evidence_addresses": [
                48329
              ],
              "evidence_addresses_hex": [
                "H'BCC9"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            }
          ],
          "semantic_notes": [],
          "evidence_addresses": [
            48304,
            48313,
            48321,
            48329
          ],
          "evidence_addresses_hex": [
            "H'BCB0",
            "H'BCB9",
            "H'BCC1",
            "H'BCC9"
          ],
          "confidence": "candidate-medium",
          "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
        },
        "byte_schema": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "immediate",
            "source_expression": "0x04",
            "source": {
              "kind": "immediate",
              "value": 4,
              "value_hex": "H'04",
              "byte_index": 0
            },
            "write_instruction_address": 48304,
            "write_instruction_address_hex": "H'BCB0",
            "instruction": "MOV:G.B #H'04, @H'F850",
            "evidence_addresses": [
              48304
            ],
            "evidence_addresses_hex": [
              "H'BCB0"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[1]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 1,
              "rx_address": 63585,
              "rx_address_hex": "H'F861",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 1,
                "rx_offsets": [
                  1
                ],
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "evidence_address": 48309,
                "evidence_address_hex": "H'BCB5",
                "instruction": "MOV:G.B @H'F861, R0"
              }
            },
            "write_instruction_address": 48313,
            "write_instruction_address_hex": "H'BCB9",
            "instruction": "MOV:G.B R0, @H'F851",
            "evidence_addresses": [
              48313
            ],
            "evidence_addresses_hex": [
              "H'BCB9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[2]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48317,
                "evidence_address_hex": "H'BCBD",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48321,
            "write_instruction_address_hex": "H'BCC1",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48321
            ],
            "evidence_addresses_hex": [
              "H'BCC1"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[3]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 3,
              "rx_address": 63587,
              "rx_address_hex": "H'F863",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48317,
                "evidence_address_hex": "H'BCBD",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48321,
            "write_instruction_address_hex": "H'BCC1",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48321
            ],
            "evidence_addresses_hex": [
              "H'BCC1"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[4]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 4,
              "rx_address": 63588,
              "rx_address_hex": "H'F864",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 4,
                "rx_offsets": [
                  4
                ],
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "evidence_address": 48325,
                "evidence_address_hex": "H'BCC5",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            },
            "write_instruction_address": 48329,
            "write_instruction_address_hex": "H'BCC9",
            "instruction": "MOV:G.B R0, @H'F854",
            "evidence_addresses": [
              48329
            ],
            "evidence_addresses_hex": [
              "H'BCC9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": []
      },
      {
        "id": "response_at_BCFA",
        "kind": "response_staging_candidate",
        "call_address": 48378,
        "call_address_hex": "H'BCFA",
        "send_builder": "loc_BA26",
        "send_builder_address": 47654,
        "send_builder_address_hex": "H'BA26",
        "window_start": 48343,
        "window_start_hex": "H'BCD7",
        "writes": [
          {
            "instruction_address": 48343,
            "instruction_address_hex": "H'BCD7",
            "addresses": [
              63568
            ],
            "addresses_hex": [
              "H'F850"
            ],
            "source_operand": "#H'04",
            "source": {
              "kind": "immediate",
              "value": 4,
              "value_hex": "H'04"
            },
            "instruction": "MOV:G.B #H'04, @H'F850"
          },
          {
            "instruction_address": 48352,
            "instruction_address_hex": "H'BCE0",
            "addresses": [
              63569
            ],
            "addresses_hex": [
              "H'F851"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 1,
              "rx_offsets": [
                1
              ],
              "rx_address": 63585,
              "rx_address_hex": "H'F861",
              "evidence_address": 48348,
              "evidence_address_hex": "H'BCDC",
              "instruction": "MOV:G.B @H'F861, R0"
            },
            "instruction": "MOV:G.B R0, @H'F851"
          },
          {
            "instruction_address": 48360,
            "instruction_address_hex": "H'BCE8",
            "addresses": [
              63569
            ],
            "addresses_hex": [
              "H'F851"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_offsets": [
                2
              ],
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "evidence_address": 48356,
              "evidence_address_hex": "H'BCE4",
              "instruction": "MOV:G.B @H'F862, R0"
            },
            "instruction": "MOV:G.B R0, @H'F851"
          },
          {
            "instruction_address": 48368,
            "instruction_address_hex": "H'BCF0",
            "addresses": [
              63572
            ],
            "addresses_hex": [
              "H'F854"
            ],
            "source_operand": "R0",
            "source": {
              "name_candidate": "primary_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 57344,
              "logical_base_address_hex": "H'E000",
              "negative_offset": 8192,
              "negative_offset_hex": "H'2000",
              "index_register": "R4",
              "operand": "@(-H'2000,R4)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 48364,
              "evidence_address_hex": "H'BCEC",
              "instruction": "MOV:G.W @(-H'2000,R4), R0"
            },
            "instruction": "MOV:G.B R0, @H'F854"
          },
          {
            "instruction_address": 48374,
            "instruction_address_hex": "H'BCF6",
            "addresses": [
              63571
            ],
            "addresses_hex": [
              "H'F853"
            ],
            "source_operand": "R0",
            "source": {
              "name_candidate": "primary_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 57344,
              "logical_base_address_hex": "H'E000",
              "negative_offset": 8192,
              "negative_offset_hex": "H'2000",
              "index_register": "R4",
              "operand": "@(-H'2000,R4)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 48364,
              "evidence_address_hex": "H'BCEC",
              "instruction": "MOV:G.W @(-H'2000,R4), R0",
              "transforms": [
                "swap_bytes"
              ]
            },
            "instruction": "MOV:G.B R0, @H'F853"
          }
        ],
        "rx_reads": [
          {
            "instruction_address": 48348,
            "instruction_address_hex": "H'BCDC",
            "rx_offset": 1,
            "rx_address": 63585,
            "rx_address_hex": "H'F861",
            "instruction": "MOV:G.B @H'F861, R0"
          },
          {
            "instruction_address": 48356,
            "instruction_address_hex": "H'BCE4",
            "rx_offset": 2,
            "rx_address": 63586,
            "rx_address_hex": "H'F862",
            "instruction": "MOV:G.B @H'F862, R0"
          }
        ],
        "evidence_addresses": [
          48343,
          48352,
          48360,
          48368,
          48374,
          48348,
          48356,
          48378
        ],
        "evidence_addresses_hex": [
          "H'BCD7",
          "H'BCE0",
          "H'BCE8",
          "H'BCF0",
          "H'BCF6",
          "H'BCDC",
          "H'BCE4",
          "H'BCFA"
        ],
        "confidence": "medium",
        "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
        "schema": {
          "kind": "response_schema_candidate",
          "response_id": "response_at_BCFA",
          "call_address": 48378,
          "call_address_hex": "H'BCFA",
          "buffer_start": 63568,
          "buffer_start_hex": "H'F850",
          "buffer_end": 63572,
          "buffer_end_hex": "H'F854",
          "bytes": [
            {
              "offset": 0,
              "byte": "byte0",
              "tx_byte": "TX[0]",
              "tx_staging_byte": "TX[0]",
              "address": 63568,
              "address_hex": "H'F850",
              "source_kind": "immediate",
              "source_expression": "0x04",
              "source": {
                "kind": "immediate",
                "value": 4,
                "value_hex": "H'04",
                "byte_index": 0
              },
              "write_instruction_address": 48343,
              "write_instruction_address_hex": "H'BCD7",
              "instruction": "MOV:G.B #H'04, @H'F850",
              "evidence_addresses": [
                48343
              ],
              "evidence_addresses_hex": [
                "H'BCD7"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 1,
              "byte": "byte1",
              "tx_byte": "TX[1]",
              "tx_staging_byte": "TX[1]",
              "address": 63569,
              "address_hex": "H'F851",
              "source_kind": "rx_frame_byte",
              "source_expression": "rx[2]",
              "source": {
                "kind": "rx_frame_byte",
                "rx_offset": 2,
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "derived_from": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48356,
                  "evidence_address_hex": "H'BCE4",
                  "instruction": "MOV:G.B @H'F862, R0"
                }
              },
              "write_instruction_address": 48360,
              "write_instruction_address_hex": "H'BCE8",
              "instruction": "MOV:G.B R0, @H'F851",
              "evidence_addresses": [
                48360
              ],
              "evidence_addresses_hex": [
                "H'BCE8"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 2,
              "byte": "byte2",
              "tx_byte": "TX[2]",
              "tx_staging_byte": "TX[2]",
              "address": 63570,
              "address_hex": "H'F852",
              "source_kind": "stale_or_unchanged",
              "source_expression": "stale/unchanged",
              "source": {
                "kind": "unknown"
              },
              "evidence_addresses": [],
              "evidence_addresses_hex": [],
              "confidence": "candidate-low",
              "caveat": "BCD7 does not freshly write F852 before loc_BA26."
            },
            {
              "offset": 3,
              "byte": "byte3",
              "tx_byte": "TX[3]",
              "tx_staging_byte": "TX[3]",
              "address": 63571,
              "address_hex": "H'F853",
              "source_kind": "table",
              "source_expression": "primary_value_table_candidate",
              "source": {
                "name_candidate": "primary_value_table_candidate",
                "element_candidate": "word_value",
                "logical_base_address": 57344,
                "logical_base_address_hex": "H'E000",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "operand": "@(-H'2000,R4)",
                "kind": "table",
                "access_width": 2,
                "evidence_address": 48364,
                "evidence_address_hex": "H'BCEC",
                "instruction": "MOV:G.W @(-H'2000,R4), R0",
                "transforms": [
                  "swap_bytes"
                ],
                "byte_index": 0
              },
              "write_instruction_address": 48374,
              "write_instruction_address_hex": "H'BCF6",
              "instruction": "MOV:G.B R0, @H'F853",
              "evidence_addresses": [
                48374
              ],
              "evidence_addresses_hex": [
                "H'BCF6"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 4,
              "byte": "byte4",
              "tx_byte": "TX[4]",
              "tx_staging_byte": "TX[4]",
              "address": 63572,
              "address_hex": "H'F854",
              "source_kind": "table",
              "source_expression": "primary_value_table_candidate",
              "source": {
                "name_candidate": "primary_value_table_candidate",
                "element_candidate": "word_value",
                "logical_base_address": 57344,
                "logical_base_address_hex": "H'E000",
                "negative_offset": 8192,
                "negative_offset_hex": "H'2000",
                "index_register": "R4",
                "operand": "@(-H'2000,R4)",
                "kind": "table",
                "access_width": 2,
                "evidence_address": 48364,
                "evidence_address_hex": "H'BCEC",
                "instruction": "MOV:G.W @(-H'2000,R4), R0",
                "byte_index": 0
              },
              "write_instruction_address": 48368,
              "write_instruction_address_hex": "H'BCF0",
              "instruction": "MOV:G.B R0, @H'F854",
              "evidence_addresses": [
                48368
              ],
              "evidence_addresses_hex": [
                "H'BCF0"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            }
          ],
          "semantic_notes": [
            "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.",
            "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.",
            "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape."
          ],
          "evidence_addresses": [
            48343,
            48360,
            48374,
            48368
          ],
          "evidence_addresses_hex": [
            "H'BCD7",
            "H'BCE8",
            "H'BCF6",
            "H'BCF0"
          ],
          "confidence": "candidate-medium",
          "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
        },
        "byte_schema": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "immediate",
            "source_expression": "0x04",
            "source": {
              "kind": "immediate",
              "value": 4,
              "value_hex": "H'04",
              "byte_index": 0
            },
            "write_instruction_address": 48343,
            "write_instruction_address_hex": "H'BCD7",
            "instruction": "MOV:G.B #H'04, @H'F850",
            "evidence_addresses": [
              48343
            ],
            "evidence_addresses_hex": [
              "H'BCD7"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[2]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 2,
                "rx_offsets": [
                  2
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48356,
                "evidence_address_hex": "H'BCE4",
                "instruction": "MOV:G.B @H'F862, R0"
              }
            },
            "write_instruction_address": 48360,
            "write_instruction_address_hex": "H'BCE8",
            "instruction": "MOV:G.B R0, @H'F851",
            "evidence_addresses": [
              48360
            ],
            "evidence_addresses_hex": [
              "H'BCE8"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "stale_or_unchanged",
            "source_expression": "stale/unchanged",
            "source": {
              "kind": "unknown"
            },
            "evidence_addresses": [],
            "evidence_addresses_hex": [],
            "confidence": "candidate-low",
            "caveat": "BCD7 does not freshly write F852 before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "table",
            "source_expression": "primary_value_table_candidate",
            "source": {
              "name_candidate": "primary_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 57344,
              "logical_base_address_hex": "H'E000",
              "negative_offset": 8192,
              "negative_offset_hex": "H'2000",
              "index_register": "R4",
              "operand": "@(-H'2000,R4)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 48364,
              "evidence_address_hex": "H'BCEC",
              "instruction": "MOV:G.W @(-H'2000,R4), R0",
              "transforms": [
                "swap_bytes"
              ],
              "byte_index": 0
            },
            "write_instruction_address": 48374,
            "write_instruction_address_hex": "H'BCF6",
            "instruction": "MOV:G.B R0, @H'F853",
            "evidence_addresses": [
              48374
            ],
            "evidence_addresses_hex": [
              "H'BCF6"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "table",
            "source_expression": "primary_value_table_candidate",
            "source": {
              "name_candidate": "primary_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 57344,
              "logical_base_address_hex": "H'E000",
              "negative_offset": 8192,
              "negative_offset_hex": "H'2000",
              "index_register": "R4",
              "operand": "@(-H'2000,R4)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 48364,
              "evidence_address_hex": "H'BCEC",
              "instruction": "MOV:G.W @(-H'2000,R4), R0",
              "byte_index": 0
            },
            "write_instruction_address": 48368,
            "write_instruction_address_hex": "H'BCF0",
            "instruction": "MOV:G.B R0, @H'F854",
            "evidence_addresses": [
              48368
            ],
            "evidence_addresses_hex": [
              "H'BCF0"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [
          "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.",
          "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.",
          "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape."
        ]
      },
      {
        "id": "response_at_BE22",
        "kind": "response_staging_candidate",
        "call_address": 48674,
        "call_address_hex": "H'BE22",
        "send_builder": "loc_BA26",
        "send_builder_address": 47654,
        "send_builder_address_hex": "H'BA26",
        "window_start": 48645,
        "window_start_hex": "H'BE05",
        "writes": [
          {
            "instruction_address": 48649,
            "instruction_address_hex": "H'BE09",
            "addresses": [
              63568,
              63569
            ],
            "addresses_hex": [
              "H'F850",
              "H'F851"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "tx_frame_word",
              "tx_offset": 0,
              "tx_offsets": [
                0,
                1
              ],
              "tx_address": 63576,
              "tx_address_hex": "H'F858",
              "evidence_address": 48645,
              "evidence_address_hex": "H'BE05",
              "instruction": "MOV:G.W @H'F858, R0"
            },
            "instruction": "MOV:G.W R0, @H'F850"
          },
          {
            "instruction_address": 48657,
            "instruction_address_hex": "H'BE11",
            "addresses": [
              63570,
              63571
            ],
            "addresses_hex": [
              "H'F852",
              "H'F853"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "tx_frame_word",
              "tx_offset": 2,
              "tx_offsets": [
                2,
                3
              ],
              "tx_address": 63578,
              "tx_address_hex": "H'F85A",
              "evidence_address": 48653,
              "evidence_address_hex": "H'BE0D",
              "instruction": "MOV:G.W @H'F85A, R0"
            },
            "instruction": "MOV:G.W R0, @H'F852"
          },
          {
            "instruction_address": 48665,
            "instruction_address_hex": "H'BE19",
            "addresses": [
              63572
            ],
            "addresses_hex": [
              "H'F854"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "tx_frame_word",
              "tx_offset": 4,
              "tx_offsets": [
                4,
                5
              ],
              "tx_address": 63580,
              "tx_address_hex": "H'F85C",
              "evidence_address": 48661,
              "evidence_address_hex": "H'BE15",
              "instruction": "MOV:G.W @H'F85C, R0"
            },
            "instruction": "MOV:G.W R0, @H'F854"
          }
        ],
        "rx_reads": [],
        "evidence_addresses": [
          48649,
          48657,
          48665,
          48674
        ],
        "evidence_addresses_hex": [
          "H'BE09",
          "H'BE11",
          "H'BE19",
          "H'BE22"
        ],
        "confidence": "medium",
        "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
        "schema": {
          "kind": "response_schema_candidate",
          "response_id": "response_at_BE22",
          "call_address": 48674,
          "call_address_hex": "H'BE22",
          "buffer_start": 63568,
          "buffer_start_hex": "H'F850",
          "buffer_end": 63572,
          "buffer_end_hex": "H'F854",
          "bytes": [
            {
              "offset": 0,
              "byte": "byte0",
              "tx_byte": "TX[0]",
              "tx_staging_byte": "TX[0]",
              "address": 63568,
              "address_hex": "H'F850",
              "source_kind": "tx_frame_byte",
              "source_expression": "tx[0]",
              "source": {
                "kind": "tx_frame_byte",
                "tx_offset": 0,
                "tx_address": 63576,
                "tx_address_hex": "H'F858",
                "derived_from": {
                  "kind": "tx_frame_word",
                  "tx_offset": 0,
                  "tx_offsets": [
                    0,
                    1
                  ],
                  "tx_address": 63576,
                  "tx_address_hex": "H'F858",
                  "evidence_address": 48645,
                  "evidence_address_hex": "H'BE05",
                  "instruction": "MOV:G.W @H'F858, R0"
                }
              },
              "write_instruction_address": 48649,
              "write_instruction_address_hex": "H'BE09",
              "instruction": "MOV:G.W R0, @H'F850",
              "evidence_addresses": [
                48649
              ],
              "evidence_addresses_hex": [
                "H'BE09"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 1,
              "byte": "byte1",
              "tx_byte": "TX[1]",
              "tx_staging_byte": "TX[1]",
              "address": 63569,
              "address_hex": "H'F851",
              "source_kind": "tx_frame_byte",
              "source_expression": "tx[1]",
              "source": {
                "kind": "tx_frame_byte",
                "tx_offset": 1,
                "tx_address": 63577,
                "tx_address_hex": "H'F859",
                "derived_from": {
                  "kind": "tx_frame_word",
                  "tx_offset": 0,
                  "tx_offsets": [
                    0,
                    1
                  ],
                  "tx_address": 63576,
                  "tx_address_hex": "H'F858",
                  "evidence_address": 48645,
                  "evidence_address_hex": "H'BE05",
                  "instruction": "MOV:G.W @H'F858, R0"
                }
              },
              "write_instruction_address": 48649,
              "write_instruction_address_hex": "H'BE09",
              "instruction": "MOV:G.W R0, @H'F850",
              "evidence_addresses": [
                48649
              ],
              "evidence_addresses_hex": [
                "H'BE09"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 2,
              "byte": "byte2",
              "tx_byte": "TX[2]",
              "tx_staging_byte": "TX[2]",
              "address": 63570,
              "address_hex": "H'F852",
              "source_kind": "tx_frame_byte",
              "source_expression": "tx[2]",
              "source": {
                "kind": "tx_frame_byte",
                "tx_offset": 2,
                "tx_address": 63578,
                "tx_address_hex": "H'F85A",
                "derived_from": {
                  "kind": "tx_frame_word",
                  "tx_offset": 2,
                  "tx_offsets": [
                    2,
                    3
                  ],
                  "tx_address": 63578,
                  "tx_address_hex": "H'F85A",
                  "evidence_address": 48653,
                  "evidence_address_hex": "H'BE0D",
                  "instruction": "MOV:G.W @H'F85A, R0"
                }
              },
              "write_instruction_address": 48657,
              "write_instruction_address_hex": "H'BE11",
              "instruction": "MOV:G.W R0, @H'F852",
              "evidence_addresses": [
                48657
              ],
              "evidence_addresses_hex": [
                "H'BE11"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 3,
              "byte": "byte3",
              "tx_byte": "TX[3]",
              "tx_staging_byte": "TX[3]",
              "address": 63571,
              "address_hex": "H'F853",
              "source_kind": "tx_frame_byte",
              "source_expression": "tx[3]",
              "source": {
                "kind": "tx_frame_byte",
                "tx_offset": 3,
                "tx_address": 63579,
                "tx_address_hex": "H'F85B",
                "derived_from": {
                  "kind": "tx_frame_word",
                  "tx_offset": 2,
                  "tx_offsets": [
                    2,
                    3
                  ],
                  "tx_address": 63578,
                  "tx_address_hex": "H'F85A",
                  "evidence_address": 48653,
                  "evidence_address_hex": "H'BE0D",
                  "instruction": "MOV:G.W @H'F85A, R0"
                }
              },
              "write_instruction_address": 48657,
              "write_instruction_address_hex": "H'BE11",
              "instruction": "MOV:G.W R0, @H'F852",
              "evidence_addresses": [
                48657
              ],
              "evidence_addresses_hex": [
                "H'BE11"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 4,
              "byte": "byte4",
              "tx_byte": "TX[4]",
              "tx_staging_byte": "TX[4]",
              "address": 63572,
              "address_hex": "H'F854",
              "source_kind": "tx_frame_byte",
              "source_expression": "tx[4]",
              "source": {
                "kind": "tx_frame_byte",
                "tx_offset": 4,
                "tx_address": 63580,
                "tx_address_hex": "H'F85C",
                "derived_from": {
                  "kind": "tx_frame_word",
                  "tx_offset": 4,
                  "tx_offsets": [
                    4,
                    5
                  ],
                  "tx_address": 63580,
                  "tx_address_hex": "H'F85C",
                  "evidence_address": 48661,
                  "evidence_address_hex": "H'BE15",
                  "instruction": "MOV:G.W @H'F85C, R0"
                }
              },
              "write_instruction_address": 48665,
              "write_instruction_address_hex": "H'BE19",
              "instruction": "MOV:G.W R0, @H'F854",
              "evidence_addresses": [
                48665
              ],
              "evidence_addresses_hex": [
                "H'BE19"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            }
          ],
          "semantic_notes": [],
          "evidence_addresses": [
            48649,
            48657,
            48665
          ],
          "evidence_addresses_hex": [
            "H'BE09",
            "H'BE11",
            "H'BE19"
          ],
          "confidence": "candidate-medium",
          "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
        },
        "byte_schema": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[0]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 0,
              "tx_address": 63576,
              "tx_address_hex": "H'F858",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 0,
                "tx_offsets": [
                  0,
                  1
                ],
                "tx_address": 63576,
                "tx_address_hex": "H'F858",
                "evidence_address": 48645,
                "evidence_address_hex": "H'BE05",
                "instruction": "MOV:G.W @H'F858, R0"
              }
            },
            "write_instruction_address": 48649,
            "write_instruction_address_hex": "H'BE09",
            "instruction": "MOV:G.W R0, @H'F850",
            "evidence_addresses": [
              48649
            ],
            "evidence_addresses_hex": [
              "H'BE09"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[1]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 1,
              "tx_address": 63577,
              "tx_address_hex": "H'F859",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 0,
                "tx_offsets": [
                  0,
                  1
                ],
                "tx_address": 63576,
                "tx_address_hex": "H'F858",
                "evidence_address": 48645,
                "evidence_address_hex": "H'BE05",
                "instruction": "MOV:G.W @H'F858, R0"
              }
            },
            "write_instruction_address": 48649,
            "write_instruction_address_hex": "H'BE09",
            "instruction": "MOV:G.W R0, @H'F850",
            "evidence_addresses": [
              48649
            ],
            "evidence_addresses_hex": [
              "H'BE09"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[2]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 2,
              "tx_address": 63578,
              "tx_address_hex": "H'F85A",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 2,
                "tx_offsets": [
                  2,
                  3
                ],
                "tx_address": 63578,
                "tx_address_hex": "H'F85A",
                "evidence_address": 48653,
                "evidence_address_hex": "H'BE0D",
                "instruction": "MOV:G.W @H'F85A, R0"
              }
            },
            "write_instruction_address": 48657,
            "write_instruction_address_hex": "H'BE11",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48657
            ],
            "evidence_addresses_hex": [
              "H'BE11"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[3]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 3,
              "tx_address": 63579,
              "tx_address_hex": "H'F85B",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 2,
                "tx_offsets": [
                  2,
                  3
                ],
                "tx_address": 63578,
                "tx_address_hex": "H'F85A",
                "evidence_address": 48653,
                "evidence_address_hex": "H'BE0D",
                "instruction": "MOV:G.W @H'F85A, R0"
              }
            },
            "write_instruction_address": 48657,
            "write_instruction_address_hex": "H'BE11",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48657
            ],
            "evidence_addresses_hex": [
              "H'BE11"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[4]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 4,
              "tx_address": 63580,
              "tx_address_hex": "H'F85C",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 4,
                "tx_offsets": [
                  4,
                  5
                ],
                "tx_address": 63580,
                "tx_address_hex": "H'F85C",
                "evidence_address": 48661,
                "evidence_address_hex": "H'BE15",
                "instruction": "MOV:G.W @H'F85C, R0"
              }
            },
            "write_instruction_address": 48665,
            "write_instruction_address_hex": "H'BE19",
            "instruction": "MOV:G.W R0, @H'F854",
            "evidence_addresses": [
              48665
            ],
            "evidence_addresses_hex": [
              "H'BE19"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": []
      },
      {
        "id": "response_at_BE6A",
        "kind": "response_staging_candidate",
        "call_address": 48746,
        "call_address_hex": "H'BE6A",
        "send_builder": "loc_BA26",
        "send_builder_address": 47654,
        "send_builder_address_hex": "H'BA26",
        "window_start": 48717,
        "window_start_hex": "H'BE4D",
        "writes": [
          {
            "instruction_address": 48717,
            "instruction_address_hex": "H'BE4D",
            "addresses": [
              63568
            ],
            "addresses_hex": [
              "H'F850"
            ],
            "source_operand": "#H'07",
            "source": {
              "kind": "immediate",
              "value": 7,
              "value_hex": "H'07"
            },
            "instruction": "MOV:G.B #H'07, @H'F850"
          },
          {
            "instruction_address": 48726,
            "instruction_address_hex": "H'BE56",
            "addresses": [
              63569
            ],
            "addresses_hex": [
              "H'F851"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 1,
              "rx_offsets": [
                1
              ],
              "rx_address": 63585,
              "rx_address_hex": "H'F861",
              "evidence_address": 48722,
              "evidence_address_hex": "H'BE52",
              "instruction": "MOV:G.B @H'F861, R0"
            },
            "instruction": "MOV:G.B R0, @H'F851"
          },
          {
            "instruction_address": 48734,
            "instruction_address_hex": "H'BE5E",
            "addresses": [
              63570,
              63571
            ],
            "addresses_hex": [
              "H'F852",
              "H'F853"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "rx_frame_word",
              "rx_offset": 2,
              "rx_offsets": [
                2,
                3
              ],
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "evidence_address": 48730,
              "evidence_address_hex": "H'BE5A",
              "instruction": "MOV:G.W @H'F862, R0"
            },
            "instruction": "MOV:G.W R0, @H'F852"
          },
          {
            "instruction_address": 48742,
            "instruction_address_hex": "H'BE66",
            "addresses": [
              63572
            ],
            "addresses_hex": [
              "H'F854"
            ],
            "source_operand": "R0",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 4,
              "rx_offsets": [
                4
              ],
              "rx_address": 63588,
              "rx_address_hex": "H'F864",
              "evidence_address": 48738,
              "evidence_address_hex": "H'BE62",
              "instruction": "MOV:G.B @H'F864, R0"
            },
            "instruction": "MOV:G.B R0, @H'F854"
          }
        ],
        "rx_reads": [
          {
            "instruction_address": 48722,
            "instruction_address_hex": "H'BE52",
            "rx_offset": 1,
            "rx_address": 63585,
            "rx_address_hex": "H'F861",
            "instruction": "MOV:G.B @H'F861, R0"
          },
          {
            "instruction_address": 48730,
            "instruction_address_hex": "H'BE5A",
            "rx_offset": 2,
            "rx_address": 63586,
            "rx_address_hex": "H'F862",
            "instruction": "MOV:G.W @H'F862, R0"
          },
          {
            "instruction_address": 48738,
            "instruction_address_hex": "H'BE62",
            "rx_offset": 4,
            "rx_address": 63588,
            "rx_address_hex": "H'F864",
            "instruction": "MOV:G.B @H'F864, R0"
          }
        ],
        "evidence_addresses": [
          48717,
          48726,
          48734,
          48742,
          48722,
          48730,
          48738,
          48746
        ],
        "evidence_addresses_hex": [
          "H'BE4D",
          "H'BE56",
          "H'BE5E",
          "H'BE66",
          "H'BE52",
          "H'BE5A",
          "H'BE62",
          "H'BE6A"
        ],
        "confidence": "medium",
        "caveat": "Response candidate means F850-F854 are written shortly before loc_BA26. The analyzer does not prove every byte is meaningful for every path.",
        "schema": {
          "kind": "response_schema_candidate",
          "response_id": "response_at_BE6A",
          "call_address": 48746,
          "call_address_hex": "H'BE6A",
          "buffer_start": 63568,
          "buffer_start_hex": "H'F850",
          "buffer_end": 63572,
          "buffer_end_hex": "H'F854",
          "bytes": [
            {
              "offset": 0,
              "byte": "byte0",
              "tx_byte": "TX[0]",
              "tx_staging_byte": "TX[0]",
              "address": 63568,
              "address_hex": "H'F850",
              "source_kind": "immediate",
              "source_expression": "0x07",
              "source": {
                "kind": "immediate",
                "value": 7,
                "value_hex": "H'07",
                "byte_index": 0
              },
              "write_instruction_address": 48717,
              "write_instruction_address_hex": "H'BE4D",
              "instruction": "MOV:G.B #H'07, @H'F850",
              "evidence_addresses": [
                48717
              ],
              "evidence_addresses_hex": [
                "H'BE4D"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 1,
              "byte": "byte1",
              "tx_byte": "TX[1]",
              "tx_staging_byte": "TX[1]",
              "address": 63569,
              "address_hex": "H'F851",
              "source_kind": "rx_frame_byte",
              "source_expression": "rx[1]",
              "source": {
                "kind": "rx_frame_byte",
                "rx_offset": 1,
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "derived_from": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 1,
                  "rx_offsets": [
                    1
                  ],
                  "rx_address": 63585,
                  "rx_address_hex": "H'F861",
                  "evidence_address": 48722,
                  "evidence_address_hex": "H'BE52",
                  "instruction": "MOV:G.B @H'F861, R0"
                }
              },
              "write_instruction_address": 48726,
              "write_instruction_address_hex": "H'BE56",
              "instruction": "MOV:G.B R0, @H'F851",
              "evidence_addresses": [
                48726
              ],
              "evidence_addresses_hex": [
                "H'BE56"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 2,
              "byte": "byte2",
              "tx_byte": "TX[2]",
              "tx_staging_byte": "TX[2]",
              "address": 63570,
              "address_hex": "H'F852",
              "source_kind": "rx_frame_byte",
              "source_expression": "rx[2]",
              "source": {
                "kind": "rx_frame_byte",
                "rx_offset": 2,
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "derived_from": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48730,
                  "evidence_address_hex": "H'BE5A",
                  "instruction": "MOV:G.W @H'F862, R0"
                }
              },
              "write_instruction_address": 48734,
              "write_instruction_address_hex": "H'BE5E",
              "instruction": "MOV:G.W R0, @H'F852",
              "evidence_addresses": [
                48734
              ],
              "evidence_addresses_hex": [
                "H'BE5E"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 3,
              "byte": "byte3",
              "tx_byte": "TX[3]",
              "tx_staging_byte": "TX[3]",
              "address": 63571,
              "address_hex": "H'F853",
              "source_kind": "rx_frame_byte",
              "source_expression": "rx[3]",
              "source": {
                "kind": "rx_frame_byte",
                "rx_offset": 3,
                "rx_address": 63587,
                "rx_address_hex": "H'F863",
                "derived_from": {
                  "kind": "rx_frame_word",
                  "rx_offset": 2,
                  "rx_offsets": [
                    2,
                    3
                  ],
                  "rx_address": 63586,
                  "rx_address_hex": "H'F862",
                  "evidence_address": 48730,
                  "evidence_address_hex": "H'BE5A",
                  "instruction": "MOV:G.W @H'F862, R0"
                }
              },
              "write_instruction_address": 48734,
              "write_instruction_address_hex": "H'BE5E",
              "instruction": "MOV:G.W R0, @H'F852",
              "evidence_addresses": [
                48734
              ],
              "evidence_addresses_hex": [
                "H'BE5E"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            },
            {
              "offset": 4,
              "byte": "byte4",
              "tx_byte": "TX[4]",
              "tx_staging_byte": "TX[4]",
              "address": 63572,
              "address_hex": "H'F854",
              "source_kind": "rx_frame_byte",
              "source_expression": "rx[4]",
              "source": {
                "kind": "rx_frame_byte",
                "rx_offset": 4,
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "derived_from": {
                  "kind": "rx_frame_byte",
                  "rx_offset": 4,
                  "rx_offsets": [
                    4
                  ],
                  "rx_address": 63588,
                  "rx_address_hex": "H'F864",
                  "evidence_address": 48738,
                  "evidence_address_hex": "H'BE62",
                  "instruction": "MOV:G.B @H'F864, R0"
                }
              },
              "write_instruction_address": 48742,
              "write_instruction_address_hex": "H'BE66",
              "instruction": "MOV:G.B R0, @H'F854",
              "evidence_addresses": [
                48742
              ],
              "evidence_addresses_hex": [
                "H'BE66"
              ],
              "confidence": "candidate-medium",
              "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
            }
          ],
          "semantic_notes": [
            "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.",
            "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value."
          ],
          "evidence_addresses": [
            48717,
            48726,
            48734,
            48742
          ],
          "evidence_addresses_hex": [
            "H'BE4D",
            "H'BE56",
            "H'BE5E",
            "H'BE66"
          ],
          "confidence": "candidate-medium",
          "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
        },
        "byte_schema": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "immediate",
            "source_expression": "0x07",
            "source": {
              "kind": "immediate",
              "value": 7,
              "value_hex": "H'07",
              "byte_index": 0
            },
            "write_instruction_address": 48717,
            "write_instruction_address_hex": "H'BE4D",
            "instruction": "MOV:G.B #H'07, @H'F850",
            "evidence_addresses": [
              48717
            ],
            "evidence_addresses_hex": [
              "H'BE4D"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[1]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 1,
              "rx_address": 63585,
              "rx_address_hex": "H'F861",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 1,
                "rx_offsets": [
                  1
                ],
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "evidence_address": 48722,
                "evidence_address_hex": "H'BE52",
                "instruction": "MOV:G.B @H'F861, R0"
              }
            },
            "write_instruction_address": 48726,
            "write_instruction_address_hex": "H'BE56",
            "instruction": "MOV:G.B R0, @H'F851",
            "evidence_addresses": [
              48726
            ],
            "evidence_addresses_hex": [
              "H'BE56"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[2]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48730,
                "evidence_address_hex": "H'BE5A",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48734,
            "write_instruction_address_hex": "H'BE5E",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48734
            ],
            "evidence_addresses_hex": [
              "H'BE5E"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[3]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 3,
              "rx_address": 63587,
              "rx_address_hex": "H'F863",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48730,
                "evidence_address_hex": "H'BE5A",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48734,
            "write_instruction_address_hex": "H'BE5E",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48734
            ],
            "evidence_addresses_hex": [
              "H'BE5E"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[4]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 4,
              "rx_address": 63588,
              "rx_address_hex": "H'F864",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 4,
                "rx_offsets": [
                  4
                ],
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "evidence_address": 48738,
                "evidence_address_hex": "H'BE62",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            },
            "write_instruction_address": 48742,
            "write_instruction_address_hex": "H'BE66",
            "instruction": "MOV:G.B R0, @H'F854",
            "evidence_addresses": [
              48742
            ],
            "evidence_addresses_hex": [
              "H'BE66"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [
          "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.",
          "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value."
        ]
      }
    ],
    "response_schemas": [
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BB43",
        "call_address": 47939,
        "call_address_hex": "H'BB43",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "computed",
            "source_expression": "computed",
            "source": {
              "kind": "register_or_computed",
              "operand": "R1",
              "source_category": "computed",
              "operation": "AND",
              "evidence_address": 47897,
              "evidence_address_hex": "H'BB19",
              "instruction": "AND.B #H'07, R1",
              "byte_index": 0
            },
            "write_instruction_address": 47900,
            "write_instruction_address_hex": "H'BB1C",
            "instruction": "MOV:G.B R1, @H'F850",
            "evidence_addresses": [
              47900
            ],
            "evidence_addresses_hex": [
              "H'BB1C"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "computed",
            "source_expression": "computed",
            "source": {
              "kind": "register_or_computed",
              "operand": "R5",
              "source_category": "computed",
              "operation": "OR",
              "evidence_address": 47913,
              "evidence_address_hex": "H'BB29",
              "instruction": "OR.B R2, R5",
              "byte_index": 0
            },
            "write_instruction_address": 47915,
            "write_instruction_address_hex": "H'BB2B",
            "instruction": "MOV:G.B R5, @H'F851",
            "evidence_addresses": [
              47915
            ],
            "evidence_addresses_hex": [
              "H'BB2B"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "computed",
            "source_expression": "computed",
            "source": {
              "kind": "register_or_computed",
              "operand": "@(-H'0790,R0)",
              "source_category": "computed",
              "evidence_address": 47880,
              "evidence_address_hex": "H'BB08",
              "instruction": "MOV:G.W @(-H'0790,R0), R0",
              "byte_index": 0
            },
            "write_instruction_address": 47904,
            "write_instruction_address_hex": "H'BB20",
            "instruction": "MOV:G.B R5, @H'F852",
            "evidence_addresses": [
              47904
            ],
            "evidence_addresses_hex": [
              "H'BB20"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "table",
            "source_expression": "current_value_table_candidate",
            "source": {
              "name_candidate": "current_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 59392,
              "logical_base_address_hex": "H'E800",
              "negative_offset": 6144,
              "negative_offset_hex": "H'1800",
              "index_register": "R0",
              "operand": "@(-H'1800,R0)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 47925,
              "evidence_address_hex": "H'BB35",
              "instruction": "MOV:G.W @(-H'1800,R0), R4",
              "transforms": [
                "swap_bytes"
              ],
              "byte_index": 0
            },
            "write_instruction_address": 47935,
            "write_instruction_address_hex": "H'BB3F",
            "instruction": "MOV:G.B R4, @H'F853",
            "evidence_addresses": [
              47935
            ],
            "evidence_addresses_hex": [
              "H'BB3F"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "table",
            "source_expression": "current_value_table_candidate",
            "source": {
              "name_candidate": "current_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 59392,
              "logical_base_address_hex": "H'E800",
              "negative_offset": 6144,
              "negative_offset_hex": "H'1800",
              "index_register": "R0",
              "operand": "@(-H'1800,R0)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 47925,
              "evidence_address_hex": "H'BB35",
              "instruction": "MOV:G.W @(-H'1800,R0), R4",
              "byte_index": 0
            },
            "write_instruction_address": 47929,
            "write_instruction_address_hex": "H'BB39",
            "instruction": "MOV:G.B R4, @H'F854",
            "evidence_addresses": [
              47929
            ],
            "evidence_addresses_hex": [
              "H'BB39"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [],
        "evidence_addresses": [
          47900,
          47915,
          47904,
          47935,
          47929
        ],
        "evidence_addresses_hex": [
          "H'BB1C",
          "H'BB2B",
          "H'BB20",
          "H'BB3F",
          "H'BB39"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      },
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BCCD",
        "call_address": 48333,
        "call_address_hex": "H'BCCD",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "immediate",
            "source_expression": "0x04",
            "source": {
              "kind": "immediate",
              "value": 4,
              "value_hex": "H'04",
              "byte_index": 0
            },
            "write_instruction_address": 48304,
            "write_instruction_address_hex": "H'BCB0",
            "instruction": "MOV:G.B #H'04, @H'F850",
            "evidence_addresses": [
              48304
            ],
            "evidence_addresses_hex": [
              "H'BCB0"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[1]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 1,
              "rx_address": 63585,
              "rx_address_hex": "H'F861",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 1,
                "rx_offsets": [
                  1
                ],
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "evidence_address": 48309,
                "evidence_address_hex": "H'BCB5",
                "instruction": "MOV:G.B @H'F861, R0"
              }
            },
            "write_instruction_address": 48313,
            "write_instruction_address_hex": "H'BCB9",
            "instruction": "MOV:G.B R0, @H'F851",
            "evidence_addresses": [
              48313
            ],
            "evidence_addresses_hex": [
              "H'BCB9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[2]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48317,
                "evidence_address_hex": "H'BCBD",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48321,
            "write_instruction_address_hex": "H'BCC1",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48321
            ],
            "evidence_addresses_hex": [
              "H'BCC1"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[3]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 3,
              "rx_address": 63587,
              "rx_address_hex": "H'F863",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48317,
                "evidence_address_hex": "H'BCBD",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48321,
            "write_instruction_address_hex": "H'BCC1",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48321
            ],
            "evidence_addresses_hex": [
              "H'BCC1"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[4]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 4,
              "rx_address": 63588,
              "rx_address_hex": "H'F864",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 4,
                "rx_offsets": [
                  4
                ],
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "evidence_address": 48325,
                "evidence_address_hex": "H'BCC5",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            },
            "write_instruction_address": 48329,
            "write_instruction_address_hex": "H'BCC9",
            "instruction": "MOV:G.B R0, @H'F854",
            "evidence_addresses": [
              48329
            ],
            "evidence_addresses_hex": [
              "H'BCC9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [],
        "evidence_addresses": [
          48304,
          48313,
          48321,
          48329
        ],
        "evidence_addresses_hex": [
          "H'BCB0",
          "H'BCB9",
          "H'BCC1",
          "H'BCC9"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      },
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BCFA",
        "call_address": 48378,
        "call_address_hex": "H'BCFA",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "immediate",
            "source_expression": "0x04",
            "source": {
              "kind": "immediate",
              "value": 4,
              "value_hex": "H'04",
              "byte_index": 0
            },
            "write_instruction_address": 48343,
            "write_instruction_address_hex": "H'BCD7",
            "instruction": "MOV:G.B #H'04, @H'F850",
            "evidence_addresses": [
              48343
            ],
            "evidence_addresses_hex": [
              "H'BCD7"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[2]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 2,
                "rx_offsets": [
                  2
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48356,
                "evidence_address_hex": "H'BCE4",
                "instruction": "MOV:G.B @H'F862, R0"
              }
            },
            "write_instruction_address": 48360,
            "write_instruction_address_hex": "H'BCE8",
            "instruction": "MOV:G.B R0, @H'F851",
            "evidence_addresses": [
              48360
            ],
            "evidence_addresses_hex": [
              "H'BCE8"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "stale_or_unchanged",
            "source_expression": "stale/unchanged",
            "source": {
              "kind": "unknown"
            },
            "evidence_addresses": [],
            "evidence_addresses_hex": [],
            "confidence": "candidate-low",
            "caveat": "BCD7 does not freshly write F852 before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "table",
            "source_expression": "primary_value_table_candidate",
            "source": {
              "name_candidate": "primary_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 57344,
              "logical_base_address_hex": "H'E000",
              "negative_offset": 8192,
              "negative_offset_hex": "H'2000",
              "index_register": "R4",
              "operand": "@(-H'2000,R4)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 48364,
              "evidence_address_hex": "H'BCEC",
              "instruction": "MOV:G.W @(-H'2000,R4), R0",
              "transforms": [
                "swap_bytes"
              ],
              "byte_index": 0
            },
            "write_instruction_address": 48374,
            "write_instruction_address_hex": "H'BCF6",
            "instruction": "MOV:G.B R0, @H'F853",
            "evidence_addresses": [
              48374
            ],
            "evidence_addresses_hex": [
              "H'BCF6"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "table",
            "source_expression": "primary_value_table_candidate",
            "source": {
              "name_candidate": "primary_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 57344,
              "logical_base_address_hex": "H'E000",
              "negative_offset": 8192,
              "negative_offset_hex": "H'2000",
              "index_register": "R4",
              "operand": "@(-H'2000,R4)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 48364,
              "evidence_address_hex": "H'BCEC",
              "instruction": "MOV:G.W @(-H'2000,R4), R0",
              "byte_index": 0
            },
            "write_instruction_address": 48368,
            "write_instruction_address_hex": "H'BCF0",
            "instruction": "MOV:G.B R0, @H'F854",
            "evidence_addresses": [
              48368
            ],
            "evidence_addresses_hex": [
              "H'BCF0"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [
          "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.",
          "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.",
          "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape."
        ],
        "evidence_addresses": [
          48343,
          48360,
          48374,
          48368
        ],
        "evidence_addresses_hex": [
          "H'BCD7",
          "H'BCE8",
          "H'BCF6",
          "H'BCF0"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      },
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BE22",
        "call_address": 48674,
        "call_address_hex": "H'BE22",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[0]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 0,
              "tx_address": 63576,
              "tx_address_hex": "H'F858",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 0,
                "tx_offsets": [
                  0,
                  1
                ],
                "tx_address": 63576,
                "tx_address_hex": "H'F858",
                "evidence_address": 48645,
                "evidence_address_hex": "H'BE05",
                "instruction": "MOV:G.W @H'F858, R0"
              }
            },
            "write_instruction_address": 48649,
            "write_instruction_address_hex": "H'BE09",
            "instruction": "MOV:G.W R0, @H'F850",
            "evidence_addresses": [
              48649
            ],
            "evidence_addresses_hex": [
              "H'BE09"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[1]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 1,
              "tx_address": 63577,
              "tx_address_hex": "H'F859",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 0,
                "tx_offsets": [
                  0,
                  1
                ],
                "tx_address": 63576,
                "tx_address_hex": "H'F858",
                "evidence_address": 48645,
                "evidence_address_hex": "H'BE05",
                "instruction": "MOV:G.W @H'F858, R0"
              }
            },
            "write_instruction_address": 48649,
            "write_instruction_address_hex": "H'BE09",
            "instruction": "MOV:G.W R0, @H'F850",
            "evidence_addresses": [
              48649
            ],
            "evidence_addresses_hex": [
              "H'BE09"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[2]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 2,
              "tx_address": 63578,
              "tx_address_hex": "H'F85A",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 2,
                "tx_offsets": [
                  2,
                  3
                ],
                "tx_address": 63578,
                "tx_address_hex": "H'F85A",
                "evidence_address": 48653,
                "evidence_address_hex": "H'BE0D",
                "instruction": "MOV:G.W @H'F85A, R0"
              }
            },
            "write_instruction_address": 48657,
            "write_instruction_address_hex": "H'BE11",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48657
            ],
            "evidence_addresses_hex": [
              "H'BE11"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[3]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 3,
              "tx_address": 63579,
              "tx_address_hex": "H'F85B",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 2,
                "tx_offsets": [
                  2,
                  3
                ],
                "tx_address": 63578,
                "tx_address_hex": "H'F85A",
                "evidence_address": 48653,
                "evidence_address_hex": "H'BE0D",
                "instruction": "MOV:G.W @H'F85A, R0"
              }
            },
            "write_instruction_address": 48657,
            "write_instruction_address_hex": "H'BE11",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48657
            ],
            "evidence_addresses_hex": [
              "H'BE11"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[4]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 4,
              "tx_address": 63580,
              "tx_address_hex": "H'F85C",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 4,
                "tx_offsets": [
                  4,
                  5
                ],
                "tx_address": 63580,
                "tx_address_hex": "H'F85C",
                "evidence_address": 48661,
                "evidence_address_hex": "H'BE15",
                "instruction": "MOV:G.W @H'F85C, R0"
              }
            },
            "write_instruction_address": 48665,
            "write_instruction_address_hex": "H'BE19",
            "instruction": "MOV:G.W R0, @H'F854",
            "evidence_addresses": [
              48665
            ],
            "evidence_addresses_hex": [
              "H'BE19"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [],
        "evidence_addresses": [
          48649,
          48657,
          48665
        ],
        "evidence_addresses_hex": [
          "H'BE09",
          "H'BE11",
          "H'BE19"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      },
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BE6A",
        "call_address": 48746,
        "call_address_hex": "H'BE6A",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "immediate",
            "source_expression": "0x07",
            "source": {
              "kind": "immediate",
              "value": 7,
              "value_hex": "H'07",
              "byte_index": 0
            },
            "write_instruction_address": 48717,
            "write_instruction_address_hex": "H'BE4D",
            "instruction": "MOV:G.B #H'07, @H'F850",
            "evidence_addresses": [
              48717
            ],
            "evidence_addresses_hex": [
              "H'BE4D"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[1]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 1,
              "rx_address": 63585,
              "rx_address_hex": "H'F861",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 1,
                "rx_offsets": [
                  1
                ],
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "evidence_address": 48722,
                "evidence_address_hex": "H'BE52",
                "instruction": "MOV:G.B @H'F861, R0"
              }
            },
            "write_instruction_address": 48726,
            "write_instruction_address_hex": "H'BE56",
            "instruction": "MOV:G.B R0, @H'F851",
            "evidence_addresses": [
              48726
            ],
            "evidence_addresses_hex": [
              "H'BE56"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[2]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48730,
                "evidence_address_hex": "H'BE5A",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48734,
            "write_instruction_address_hex": "H'BE5E",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48734
            ],
            "evidence_addresses_hex": [
              "H'BE5E"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[3]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 3,
              "rx_address": 63587,
              "rx_address_hex": "H'F863",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48730,
                "evidence_address_hex": "H'BE5A",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48734,
            "write_instruction_address_hex": "H'BE5E",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48734
            ],
            "evidence_addresses_hex": [
              "H'BE5E"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[4]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 4,
              "rx_address": 63588,
              "rx_address_hex": "H'F864",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 4,
                "rx_offsets": [
                  4
                ],
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "evidence_address": 48738,
                "evidence_address_hex": "H'BE62",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            },
            "write_instruction_address": 48742,
            "write_instruction_address_hex": "H'BE66",
            "instruction": "MOV:G.B R0, @H'F854",
            "evidence_addresses": [
              48742
            ],
            "evidence_addresses_hex": [
              "H'BE66"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [
          "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.",
          "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value."
        ],
        "evidence_addresses": [
          48717,
          48726,
          48734,
          48742
        ],
        "evidence_addresses_hex": [
          "H'BE4D",
          "H'BE56",
          "H'BE5E",
          "H'BE66"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      }
    ],
    "response_schema": [
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BB43",
        "call_address": 47939,
        "call_address_hex": "H'BB43",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "computed",
            "source_expression": "computed",
            "source": {
              "kind": "register_or_computed",
              "operand": "R1",
              "source_category": "computed",
              "operation": "AND",
              "evidence_address": 47897,
              "evidence_address_hex": "H'BB19",
              "instruction": "AND.B #H'07, R1",
              "byte_index": 0
            },
            "write_instruction_address": 47900,
            "write_instruction_address_hex": "H'BB1C",
            "instruction": "MOV:G.B R1, @H'F850",
            "evidence_addresses": [
              47900
            ],
            "evidence_addresses_hex": [
              "H'BB1C"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "computed",
            "source_expression": "computed",
            "source": {
              "kind": "register_or_computed",
              "operand": "R5",
              "source_category": "computed",
              "operation": "OR",
              "evidence_address": 47913,
              "evidence_address_hex": "H'BB29",
              "instruction": "OR.B R2, R5",
              "byte_index": 0
            },
            "write_instruction_address": 47915,
            "write_instruction_address_hex": "H'BB2B",
            "instruction": "MOV:G.B R5, @H'F851",
            "evidence_addresses": [
              47915
            ],
            "evidence_addresses_hex": [
              "H'BB2B"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "computed",
            "source_expression": "computed",
            "source": {
              "kind": "register_or_computed",
              "operand": "@(-H'0790,R0)",
              "source_category": "computed",
              "evidence_address": 47880,
              "evidence_address_hex": "H'BB08",
              "instruction": "MOV:G.W @(-H'0790,R0), R0",
              "byte_index": 0
            },
            "write_instruction_address": 47904,
            "write_instruction_address_hex": "H'BB20",
            "instruction": "MOV:G.B R5, @H'F852",
            "evidence_addresses": [
              47904
            ],
            "evidence_addresses_hex": [
              "H'BB20"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "table",
            "source_expression": "current_value_table_candidate",
            "source": {
              "name_candidate": "current_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 59392,
              "logical_base_address_hex": "H'E800",
              "negative_offset": 6144,
              "negative_offset_hex": "H'1800",
              "index_register": "R0",
              "operand": "@(-H'1800,R0)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 47925,
              "evidence_address_hex": "H'BB35",
              "instruction": "MOV:G.W @(-H'1800,R0), R4",
              "transforms": [
                "swap_bytes"
              ],
              "byte_index": 0
            },
            "write_instruction_address": 47935,
            "write_instruction_address_hex": "H'BB3F",
            "instruction": "MOV:G.B R4, @H'F853",
            "evidence_addresses": [
              47935
            ],
            "evidence_addresses_hex": [
              "H'BB3F"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "table",
            "source_expression": "current_value_table_candidate",
            "source": {
              "name_candidate": "current_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 59392,
              "logical_base_address_hex": "H'E800",
              "negative_offset": 6144,
              "negative_offset_hex": "H'1800",
              "index_register": "R0",
              "operand": "@(-H'1800,R0)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 47925,
              "evidence_address_hex": "H'BB35",
              "instruction": "MOV:G.W @(-H'1800,R0), R4",
              "byte_index": 0
            },
            "write_instruction_address": 47929,
            "write_instruction_address_hex": "H'BB39",
            "instruction": "MOV:G.B R4, @H'F854",
            "evidence_addresses": [
              47929
            ],
            "evidence_addresses_hex": [
              "H'BB39"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [],
        "evidence_addresses": [
          47900,
          47915,
          47904,
          47935,
          47929
        ],
        "evidence_addresses_hex": [
          "H'BB1C",
          "H'BB2B",
          "H'BB20",
          "H'BB3F",
          "H'BB39"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      },
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BCCD",
        "call_address": 48333,
        "call_address_hex": "H'BCCD",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "immediate",
            "source_expression": "0x04",
            "source": {
              "kind": "immediate",
              "value": 4,
              "value_hex": "H'04",
              "byte_index": 0
            },
            "write_instruction_address": 48304,
            "write_instruction_address_hex": "H'BCB0",
            "instruction": "MOV:G.B #H'04, @H'F850",
            "evidence_addresses": [
              48304
            ],
            "evidence_addresses_hex": [
              "H'BCB0"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[1]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 1,
              "rx_address": 63585,
              "rx_address_hex": "H'F861",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 1,
                "rx_offsets": [
                  1
                ],
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "evidence_address": 48309,
                "evidence_address_hex": "H'BCB5",
                "instruction": "MOV:G.B @H'F861, R0"
              }
            },
            "write_instruction_address": 48313,
            "write_instruction_address_hex": "H'BCB9",
            "instruction": "MOV:G.B R0, @H'F851",
            "evidence_addresses": [
              48313
            ],
            "evidence_addresses_hex": [
              "H'BCB9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[2]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48317,
                "evidence_address_hex": "H'BCBD",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48321,
            "write_instruction_address_hex": "H'BCC1",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48321
            ],
            "evidence_addresses_hex": [
              "H'BCC1"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[3]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 3,
              "rx_address": 63587,
              "rx_address_hex": "H'F863",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48317,
                "evidence_address_hex": "H'BCBD",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48321,
            "write_instruction_address_hex": "H'BCC1",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48321
            ],
            "evidence_addresses_hex": [
              "H'BCC1"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[4]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 4,
              "rx_address": 63588,
              "rx_address_hex": "H'F864",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 4,
                "rx_offsets": [
                  4
                ],
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "evidence_address": 48325,
                "evidence_address_hex": "H'BCC5",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            },
            "write_instruction_address": 48329,
            "write_instruction_address_hex": "H'BCC9",
            "instruction": "MOV:G.B R0, @H'F854",
            "evidence_addresses": [
              48329
            ],
            "evidence_addresses_hex": [
              "H'BCC9"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [],
        "evidence_addresses": [
          48304,
          48313,
          48321,
          48329
        ],
        "evidence_addresses_hex": [
          "H'BCB0",
          "H'BCB9",
          "H'BCC1",
          "H'BCC9"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      },
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BCFA",
        "call_address": 48378,
        "call_address_hex": "H'BCFA",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "immediate",
            "source_expression": "0x04",
            "source": {
              "kind": "immediate",
              "value": 4,
              "value_hex": "H'04",
              "byte_index": 0
            },
            "write_instruction_address": 48343,
            "write_instruction_address_hex": "H'BCD7",
            "instruction": "MOV:G.B #H'04, @H'F850",
            "evidence_addresses": [
              48343
            ],
            "evidence_addresses_hex": [
              "H'BCD7"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[2]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 2,
                "rx_offsets": [
                  2
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48356,
                "evidence_address_hex": "H'BCE4",
                "instruction": "MOV:G.B @H'F862, R0"
              }
            },
            "write_instruction_address": 48360,
            "write_instruction_address_hex": "H'BCE8",
            "instruction": "MOV:G.B R0, @H'F851",
            "evidence_addresses": [
              48360
            ],
            "evidence_addresses_hex": [
              "H'BCE8"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "stale_or_unchanged",
            "source_expression": "stale/unchanged",
            "source": {
              "kind": "unknown"
            },
            "evidence_addresses": [],
            "evidence_addresses_hex": [],
            "confidence": "candidate-low",
            "caveat": "BCD7 does not freshly write F852 before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "table",
            "source_expression": "primary_value_table_candidate",
            "source": {
              "name_candidate": "primary_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 57344,
              "logical_base_address_hex": "H'E000",
              "negative_offset": 8192,
              "negative_offset_hex": "H'2000",
              "index_register": "R4",
              "operand": "@(-H'2000,R4)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 48364,
              "evidence_address_hex": "H'BCEC",
              "instruction": "MOV:G.W @(-H'2000,R4), R0",
              "transforms": [
                "swap_bytes"
              ],
              "byte_index": 0
            },
            "write_instruction_address": 48374,
            "write_instruction_address_hex": "H'BCF6",
            "instruction": "MOV:G.B R0, @H'F853",
            "evidence_addresses": [
              48374
            ],
            "evidence_addresses_hex": [
              "H'BCF6"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "table",
            "source_expression": "primary_value_table_candidate",
            "source": {
              "name_candidate": "primary_value_table_candidate",
              "element_candidate": "word_value",
              "logical_base_address": 57344,
              "logical_base_address_hex": "H'E000",
              "negative_offset": 8192,
              "negative_offset_hex": "H'2000",
              "index_register": "R4",
              "operand": "@(-H'2000,R4)",
              "kind": "table",
              "access_width": 2,
              "evidence_address": 48364,
              "evidence_address_hex": "H'BCEC",
              "instruction": "MOV:G.W @(-H'2000,R4), R0",
              "byte_index": 0
            },
            "write_instruction_address": 48368,
            "write_instruction_address_hex": "H'BCF0",
            "instruction": "MOV:G.B R0, @H'F854",
            "evidence_addresses": [
              48368
            ],
            "evidence_addresses_hex": [
              "H'BCF0"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [
          "Command 1 BCD7 staging is odd: F850=0x04; F851 is written from F861 then overwritten by F862.",
          "The primary table word is read from E000 + 2*selector; F854/F853 receive low/high value bytes.",
          "F852 may be stale or unchanged in this handler; avoid a fixed 04 00 QQ hi lo response shape."
        ],
        "evidence_addresses": [
          48343,
          48360,
          48374,
          48368
        ],
        "evidence_addresses_hex": [
          "H'BCD7",
          "H'BCE8",
          "H'BCF6",
          "H'BCF0"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      },
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BE22",
        "call_address": 48674,
        "call_address_hex": "H'BE22",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[0]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 0,
              "tx_address": 63576,
              "tx_address_hex": "H'F858",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 0,
                "tx_offsets": [
                  0,
                  1
                ],
                "tx_address": 63576,
                "tx_address_hex": "H'F858",
                "evidence_address": 48645,
                "evidence_address_hex": "H'BE05",
                "instruction": "MOV:G.W @H'F858, R0"
              }
            },
            "write_instruction_address": 48649,
            "write_instruction_address_hex": "H'BE09",
            "instruction": "MOV:G.W R0, @H'F850",
            "evidence_addresses": [
              48649
            ],
            "evidence_addresses_hex": [
              "H'BE09"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[1]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 1,
              "tx_address": 63577,
              "tx_address_hex": "H'F859",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 0,
                "tx_offsets": [
                  0,
                  1
                ],
                "tx_address": 63576,
                "tx_address_hex": "H'F858",
                "evidence_address": 48645,
                "evidence_address_hex": "H'BE05",
                "instruction": "MOV:G.W @H'F858, R0"
              }
            },
            "write_instruction_address": 48649,
            "write_instruction_address_hex": "H'BE09",
            "instruction": "MOV:G.W R0, @H'F850",
            "evidence_addresses": [
              48649
            ],
            "evidence_addresses_hex": [
              "H'BE09"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[2]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 2,
              "tx_address": 63578,
              "tx_address_hex": "H'F85A",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 2,
                "tx_offsets": [
                  2,
                  3
                ],
                "tx_address": 63578,
                "tx_address_hex": "H'F85A",
                "evidence_address": 48653,
                "evidence_address_hex": "H'BE0D",
                "instruction": "MOV:G.W @H'F85A, R0"
              }
            },
            "write_instruction_address": 48657,
            "write_instruction_address_hex": "H'BE11",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48657
            ],
            "evidence_addresses_hex": [
              "H'BE11"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[3]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 3,
              "tx_address": 63579,
              "tx_address_hex": "H'F85B",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 2,
                "tx_offsets": [
                  2,
                  3
                ],
                "tx_address": 63578,
                "tx_address_hex": "H'F85A",
                "evidence_address": 48653,
                "evidence_address_hex": "H'BE0D",
                "instruction": "MOV:G.W @H'F85A, R0"
              }
            },
            "write_instruction_address": 48657,
            "write_instruction_address_hex": "H'BE11",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48657
            ],
            "evidence_addresses_hex": [
              "H'BE11"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "tx_frame_byte",
            "source_expression": "tx[4]",
            "source": {
              "kind": "tx_frame_byte",
              "tx_offset": 4,
              "tx_address": 63580,
              "tx_address_hex": "H'F85C",
              "derived_from": {
                "kind": "tx_frame_word",
                "tx_offset": 4,
                "tx_offsets": [
                  4,
                  5
                ],
                "tx_address": 63580,
                "tx_address_hex": "H'F85C",
                "evidence_address": 48661,
                "evidence_address_hex": "H'BE15",
                "instruction": "MOV:G.W @H'F85C, R0"
              }
            },
            "write_instruction_address": 48665,
            "write_instruction_address_hex": "H'BE19",
            "instruction": "MOV:G.W R0, @H'F854",
            "evidence_addresses": [
              48665
            ],
            "evidence_addresses_hex": [
              "H'BE19"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [],
        "evidence_addresses": [
          48649,
          48657,
          48665
        ],
        "evidence_addresses_hex": [
          "H'BE09",
          "H'BE11",
          "H'BE19"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      },
      {
        "kind": "response_schema_candidate",
        "response_id": "response_at_BE6A",
        "call_address": 48746,
        "call_address_hex": "H'BE6A",
        "buffer_start": 63568,
        "buffer_start_hex": "H'F850",
        "buffer_end": 63572,
        "buffer_end_hex": "H'F854",
        "bytes": [
          {
            "offset": 0,
            "byte": "byte0",
            "tx_byte": "TX[0]",
            "tx_staging_byte": "TX[0]",
            "address": 63568,
            "address_hex": "H'F850",
            "source_kind": "immediate",
            "source_expression": "0x07",
            "source": {
              "kind": "immediate",
              "value": 7,
              "value_hex": "H'07",
              "byte_index": 0
            },
            "write_instruction_address": 48717,
            "write_instruction_address_hex": "H'BE4D",
            "instruction": "MOV:G.B #H'07, @H'F850",
            "evidence_addresses": [
              48717
            ],
            "evidence_addresses_hex": [
              "H'BE4D"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 1,
            "byte": "byte1",
            "tx_byte": "TX[1]",
            "tx_staging_byte": "TX[1]",
            "address": 63569,
            "address_hex": "H'F851",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[1]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 1,
              "rx_address": 63585,
              "rx_address_hex": "H'F861",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 1,
                "rx_offsets": [
                  1
                ],
                "rx_address": 63585,
                "rx_address_hex": "H'F861",
                "evidence_address": 48722,
                "evidence_address_hex": "H'BE52",
                "instruction": "MOV:G.B @H'F861, R0"
              }
            },
            "write_instruction_address": 48726,
            "write_instruction_address_hex": "H'BE56",
            "instruction": "MOV:G.B R0, @H'F851",
            "evidence_addresses": [
              48726
            ],
            "evidence_addresses_hex": [
              "H'BE56"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 2,
            "byte": "byte2",
            "tx_byte": "TX[2]",
            "tx_staging_byte": "TX[2]",
            "address": 63570,
            "address_hex": "H'F852",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[2]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 2,
              "rx_address": 63586,
              "rx_address_hex": "H'F862",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48730,
                "evidence_address_hex": "H'BE5A",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48734,
            "write_instruction_address_hex": "H'BE5E",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48734
            ],
            "evidence_addresses_hex": [
              "H'BE5E"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 3,
            "byte": "byte3",
            "tx_byte": "TX[3]",
            "tx_staging_byte": "TX[3]",
            "address": 63571,
            "address_hex": "H'F853",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[3]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 3,
              "rx_address": 63587,
              "rx_address_hex": "H'F863",
              "derived_from": {
                "kind": "rx_frame_word",
                "rx_offset": 2,
                "rx_offsets": [
                  2,
                  3
                ],
                "rx_address": 63586,
                "rx_address_hex": "H'F862",
                "evidence_address": 48730,
                "evidence_address_hex": "H'BE5A",
                "instruction": "MOV:G.W @H'F862, R0"
              }
            },
            "write_instruction_address": 48734,
            "write_instruction_address_hex": "H'BE5E",
            "instruction": "MOV:G.W R0, @H'F852",
            "evidence_addresses": [
              48734
            ],
            "evidence_addresses_hex": [
              "H'BE5E"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          },
          {
            "offset": 4,
            "byte": "byte4",
            "tx_byte": "TX[4]",
            "tx_staging_byte": "TX[4]",
            "address": 63572,
            "address_hex": "H'F854",
            "source_kind": "rx_frame_byte",
            "source_expression": "rx[4]",
            "source": {
              "kind": "rx_frame_byte",
              "rx_offset": 4,
              "rx_address": 63588,
              "rx_address_hex": "H'F864",
              "derived_from": {
                "kind": "rx_frame_byte",
                "rx_offset": 4,
                "rx_offsets": [
                  4
                ],
                "rx_address": 63588,
                "rx_address_hex": "H'F864",
                "evidence_address": 48738,
                "evidence_address_hex": "H'BE62",
                "instruction": "MOV:G.B @H'F864, R0"
              }
            },
            "write_instruction_address": 48742,
            "write_instruction_address_hex": "H'BE66",
            "instruction": "MOV:G.B R0, @H'F854",
            "evidence_addresses": [
              48742
            ],
            "evidence_addresses_hex": [
              "H'BE66"
            ],
            "confidence": "candidate-medium",
            "caveat": "Per-byte source is inferred from the final observed write to this staging byte before loc_BA26."
          }
        ],
        "semantic_notes": [
          "loc_BE4D retry/error echo stages F850=0x07 and copies F861-F864 into F851-F854 before loc_BA26.",
          "Observed 07 80 40 20 90 2D echoes RX payload bytes 80 40 20 90; it is not a table-derived value."
        ],
        "evidence_addresses": [
          48717,
          48726,
          48734,
          48742
        ],
        "evidence_addresses_hex": [
          "H'BE4D",
          "H'BE56",
          "H'BE5E",
          "H'BE66"
        ],
        "confidence": "candidate-medium",
        "caveat": "Response schema is a candidate extracted from writes to F850-F854 in the local window before loc_BA26; control-flow alternatives may share a send call."
      }
    ],
    "send_builder": {
      "kind": "tx_send_builder_candidate",
      "label": "loc_BA26",
      "address": 47654,
      "address_hex": "H'BA26",
      "staging_buffer_start": 63568,
      "staging_buffer_start_hex": "H'F850",
      "staging_buffer_end": 63572,
      "staging_buffer_end_hex": "H'F854",
      "tx_frame_start": 63576,
      "tx_frame_start_hex": "H'F858",
      "tx_frame_end": 63581,
      "tx_frame_end_hex": "H'F85D",
      "checksum_address": 63581,
      "checksum_address_hex": "H'F85D",
      "checksum_seed": 90,
      "checksum_seed_hex": "H'005A",
      "staging_to_frame_copies": [],
      "response_call_addresses": [
        47939,
        48333,
        48378,
        48674,
        48746
      ],
      "response_call_addresses_hex": [
        "H'BB43",
        "H'BCCD",
        "H'BCFA",
        "H'BE22",
        "H'BE6A"
      ],
      "serial_reconstruction_candidate_id": "sci1_tx_frame_f858_len6_candidate",
      "evidence_addresses": [
        47674,
        47682,
        47690,
        47696,
        47700,
        47704,
        47708,
        47712,
        47716,
        47726,
        47939,
        48333,
        48378,
        48674,
        48746
      ],
      "evidence_addresses_hex": [
        "H'BA3A",
        "H'BA42",
        "H'BA4A",
        "H'BA50",
        "H'BA54",
        "H'BA58",
        "H'BA5C",
        "H'BA60",
        "H'BA64",
        "H'BA6E",
        "H'BB43",
        "H'BCCD",
        "H'BCFA",
        "H'BE22",
        "H'BE6A"
      ],
      "confidence": "low",
      "caveat": "loc_BA26 is treated as a send builder because it copies F850-F854 into the evidence-supported TX frame and then starts SCI1 transmission."
    },
    "logical_table_map_candidates": [
      {
        "kind": "logical_table_map_candidate",
        "name_candidate": "primary_value_table_candidate",
        "element_candidate": "word_value",
        "logical_base_address": 57344,
        "logical_base_address_hex": "H'E000",
        "negative_offset": 8192,
        "negative_offset_hex": "H'2000",
        "observed_index_registers": [
          "R0",
          "R3",
          "R4"
        ],
        "observed_accesses": [
          "read",
          "write"
        ],
        "observed_widths": [
          2
        ],
        "accesses": [
          {
            "instruction_address": 6627,
            "instruction_address_hex": "H'19E3",
            "operand": "@(-H'2000,R3)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'2000,R3), R0"
          },
          {
            "instruction_address": 6659,
            "instruction_address_hex": "H'1A03",
            "operand": "@(-H'2000,R3)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "CMP:G.W @(-H'2000,R3), R1"
          },
          {
            "instruction_address": 6717,
            "instruction_address_hex": "H'1A3D",
            "operand": "@(-H'2000,R3)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'2000,R3), R0"
          },
          {
            "instruction_address": 6763,
            "instruction_address_hex": "H'1A6B",
            "operand": "@(-H'2000,R3)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "CMP:G.W @(-H'2000,R3), R0"
          },
          {
            "instruction_address": 16268,
            "instruction_address_hex": "H'3F8C",
            "operand": "@(-H'2000,R0)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'2000,R0)"
          },
          {
            "instruction_address": 16503,
            "instruction_address_hex": "H'4077",
            "operand": "@(-H'2000,R0)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'2000,R0)"
          },
          {
            "instruction_address": 48245,
            "instruction_address_hex": "H'BC75",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'2000,R4)"
          },
          {
            "instruction_address": 48277,
            "instruction_address_hex": "H'BC95",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'2000,R4)"
          },
          {
            "instruction_address": 48364,
            "instruction_address_hex": "H'BCEC",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'2000,R4), R0"
          },
          {
            "instruction_address": 48410,
            "instruction_address_hex": "H'BD1A",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'2000,R4)"
          },
          {
            "instruction_address": 48437,
            "instruction_address_hex": "H'BD35",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'2000,R4)"
          }
        ],
        "evidence_addresses": [
          6627,
          6659,
          6717,
          6763,
          16268,
          16503,
          48245,
          48277,
          48364,
          48410,
          48437
        ],
        "evidence_addresses_hex": [
          "H'19E3",
          "H'1A03",
          "H'1A3D",
          "H'1A6B",
          "H'3F8C",
          "H'4077",
          "H'BC75",
          "H'BC95",
          "H'BCEC",
          "H'BD1A",
          "H'BD35"
        ],
        "confidence": "candidate-medium",
        "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
      },
      {
        "kind": "logical_table_map_candidate",
        "name_candidate": "secondary_value_table_candidate",
        "element_candidate": "word_value",
        "logical_base_address": 58368,
        "logical_base_address_hex": "H'E400",
        "negative_offset": 7168,
        "negative_offset_hex": "H'1C00",
        "observed_index_registers": [
          "R0",
          "R3",
          "R4"
        ],
        "observed_accesses": [
          "read",
          "write"
        ],
        "observed_widths": [
          2
        ],
        "accesses": [
          {
            "instruction_address": 6570,
            "instruction_address_hex": "H'19AA",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'1C00,R3), R0"
          },
          {
            "instruction_address": 6731,
            "instruction_address_hex": "H'1A4B",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'1C00,R3), R1"
          },
          {
            "instruction_address": 6747,
            "instruction_address_hex": "H'1A5B",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'1C00,R3), R1"
          },
          {
            "instruction_address": 6785,
            "instruction_address_hex": "H'1A81",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "AND.W @(-H'1C00,R3), R1"
          },
          {
            "instruction_address": 6836,
            "instruction_address_hex": "H'1AB4",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "BTST.W R0, @(-H'1C00,R3)"
          },
          {
            "instruction_address": 6849,
            "instruction_address_hex": "H'1AC1",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "BTST.W R0, @(-H'1C00,R3)"
          },
          {
            "instruction_address": 16507,
            "instruction_address_hex": "H'407B",
            "operand": "@(-H'1C00,R0)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'1C00,R0)"
          },
          {
            "instruction_address": 48613,
            "instruction_address_hex": "H'BDE5",
            "operand": "@(-H'1C00,R4)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1C00,R4)"
          }
        ],
        "evidence_addresses": [
          6570,
          6731,
          6747,
          6785,
          6836,
          6849,
          16507,
          48613
        ],
        "evidence_addresses_hex": [
          "H'19AA",
          "H'1A4B",
          "H'1A5B",
          "H'1A81",
          "H'1AB4",
          "H'1AC1",
          "H'407B",
          "H'BDE5"
        ],
        "confidence": "candidate-medium",
        "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
      },
      {
        "kind": "logical_table_map_candidate",
        "name_candidate": "current_value_table_candidate",
        "element_candidate": "word_value",
        "logical_base_address": 59392,
        "logical_base_address_hex": "H'E800",
        "negative_offset": 6144,
        "negative_offset_hex": "H'1800",
        "observed_index_registers": [
          "R0",
          "R3",
          "R4"
        ],
        "observed_accesses": [
          "read",
          "write"
        ],
        "observed_widths": [
          2
        ],
        "accesses": [
          {
            "instruction_address": 6665,
            "instruction_address_hex": "H'1A09",
            "operand": "@(-H'1800,R3)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R3",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R1, @(-H'1800,R3)"
          },
          {
            "instruction_address": 6769,
            "instruction_address_hex": "H'1A71",
            "operand": "@(-H'1800,R3)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R3",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1800,R3)"
          },
          {
            "instruction_address": 16272,
            "instruction_address_hex": "H'3F90",
            "operand": "@(-H'1800,R0)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'1800,R0)"
          },
          {
            "instruction_address": 16511,
            "instruction_address_hex": "H'407F",
            "operand": "@(-H'1800,R0)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'1800,R0)"
          },
          {
            "instruction_address": 47925,
            "instruction_address_hex": "H'BB35",
            "operand": "@(-H'1800,R0)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R0",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'1800,R0), R4"
          },
          {
            "instruction_address": 48249,
            "instruction_address_hex": "H'BC79",
            "operand": "@(-H'1800,R4)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1800,R4)"
          },
          {
            "instruction_address": 48281,
            "instruction_address_hex": "H'BC99",
            "operand": "@(-H'1800,R4)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1800,R4)"
          },
          {
            "instruction_address": 48414,
            "instruction_address_hex": "H'BD1E",
            "operand": "@(-H'1800,R4)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1800,R4)"
          }
        ],
        "evidence_addresses": [
          6665,
          6769,
          16272,
          16511,
          47925,
          48249,
          48281,
          48414
        ],
        "evidence_addresses_hex": [
          "H'1A09",
          "H'1A71",
          "H'3F90",
          "H'407F",
          "H'BB35",
          "H'BC79",
          "H'BC99",
          "H'BD1E"
        ],
        "confidence": "candidate-medium",
        "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
      },
      {
        "kind": "logical_table_map_candidate",
        "name_candidate": "flag_table_candidate",
        "element_candidate": "bit_flags",
        "logical_base_address": 60416,
        "logical_base_address_hex": "H'EC00",
        "negative_offset": 5120,
        "negative_offset_hex": "H'1400",
        "observed_index_registers": [
          "R0",
          "R5"
        ],
        "observed_accesses": [
          "write"
        ],
        "observed_widths": [
          1,
          2
        ],
        "accesses": [
          {
            "instruction_address": 16520,
            "instruction_address_hex": "H'4088",
            "operand": "@(-H'1400,R0)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'1400,R0)"
          },
          {
            "instruction_address": 48258,
            "instruction_address_hex": "H'BC82",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #7, @(-H'1400,R5)"
          },
          {
            "instruction_address": 48285,
            "instruction_address_hex": "H'BC9D",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #7, @(-H'1400,R5)"
          },
          {
            "instruction_address": 48418,
            "instruction_address_hex": "H'BD22",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #7, @(-H'1400,R5)"
          },
          {
            "instruction_address": 48441,
            "instruction_address_hex": "H'BD39",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #7, @(-H'1400,R5)"
          },
          {
            "instruction_address": 48617,
            "instruction_address_hex": "H'BDE9",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #6, @(-H'1400,R5)"
          }
        ],
        "evidence_addresses": [
          16520,
          48258,
          48285,
          48418,
          48441,
          48617
        ],
        "evidence_addresses_hex": [
          "H'4088",
          "H'BC82",
          "H'BC9D",
          "H'BD22",
          "H'BD39",
          "H'BDE9"
        ],
        "confidence": "candidate-medium",
        "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
      }
    ],
    "table_map_candidates": [
      {
        "kind": "logical_table_map_candidate",
        "name_candidate": "primary_value_table_candidate",
        "element_candidate": "word_value",
        "logical_base_address": 57344,
        "logical_base_address_hex": "H'E000",
        "negative_offset": 8192,
        "negative_offset_hex": "H'2000",
        "observed_index_registers": [
          "R0",
          "R3",
          "R4"
        ],
        "observed_accesses": [
          "read",
          "write"
        ],
        "observed_widths": [
          2
        ],
        "accesses": [
          {
            "instruction_address": 6627,
            "instruction_address_hex": "H'19E3",
            "operand": "@(-H'2000,R3)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'2000,R3), R0"
          },
          {
            "instruction_address": 6659,
            "instruction_address_hex": "H'1A03",
            "operand": "@(-H'2000,R3)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "CMP:G.W @(-H'2000,R3), R1"
          },
          {
            "instruction_address": 6717,
            "instruction_address_hex": "H'1A3D",
            "operand": "@(-H'2000,R3)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'2000,R3), R0"
          },
          {
            "instruction_address": 6763,
            "instruction_address_hex": "H'1A6B",
            "operand": "@(-H'2000,R3)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "CMP:G.W @(-H'2000,R3), R0"
          },
          {
            "instruction_address": 16268,
            "instruction_address_hex": "H'3F8C",
            "operand": "@(-H'2000,R0)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'2000,R0)"
          },
          {
            "instruction_address": 16503,
            "instruction_address_hex": "H'4077",
            "operand": "@(-H'2000,R0)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'2000,R0)"
          },
          {
            "instruction_address": 48245,
            "instruction_address_hex": "H'BC75",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'2000,R4)"
          },
          {
            "instruction_address": 48277,
            "instruction_address_hex": "H'BC95",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'2000,R4)"
          },
          {
            "instruction_address": 48364,
            "instruction_address_hex": "H'BCEC",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'2000,R4), R0"
          },
          {
            "instruction_address": 48410,
            "instruction_address_hex": "H'BD1A",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'2000,R4)"
          },
          {
            "instruction_address": 48437,
            "instruction_address_hex": "H'BD35",
            "operand": "@(-H'2000,R4)",
            "negative_offset": 8192,
            "negative_offset_hex": "H'2000",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'2000,R4)"
          }
        ],
        "evidence_addresses": [
          6627,
          6659,
          6717,
          6763,
          16268,
          16503,
          48245,
          48277,
          48364,
          48410,
          48437
        ],
        "evidence_addresses_hex": [
          "H'19E3",
          "H'1A03",
          "H'1A3D",
          "H'1A6B",
          "H'3F8C",
          "H'4077",
          "H'BC75",
          "H'BC95",
          "H'BCEC",
          "H'BD1A",
          "H'BD35"
        ],
        "confidence": "candidate-medium",
        "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
      },
      {
        "kind": "logical_table_map_candidate",
        "name_candidate": "secondary_value_table_candidate",
        "element_candidate": "word_value",
        "logical_base_address": 58368,
        "logical_base_address_hex": "H'E400",
        "negative_offset": 7168,
        "negative_offset_hex": "H'1C00",
        "observed_index_registers": [
          "R0",
          "R3",
          "R4"
        ],
        "observed_accesses": [
          "read",
          "write"
        ],
        "observed_widths": [
          2
        ],
        "accesses": [
          {
            "instruction_address": 6570,
            "instruction_address_hex": "H'19AA",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'1C00,R3), R0"
          },
          {
            "instruction_address": 6731,
            "instruction_address_hex": "H'1A4B",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'1C00,R3), R1"
          },
          {
            "instruction_address": 6747,
            "instruction_address_hex": "H'1A5B",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'1C00,R3), R1"
          },
          {
            "instruction_address": 6785,
            "instruction_address_hex": "H'1A81",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "AND.W @(-H'1C00,R3), R1"
          },
          {
            "instruction_address": 6836,
            "instruction_address_hex": "H'1AB4",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "BTST.W R0, @(-H'1C00,R3)"
          },
          {
            "instruction_address": 6849,
            "instruction_address_hex": "H'1AC1",
            "operand": "@(-H'1C00,R3)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R3",
            "access": "read",
            "width": 2,
            "instruction": "BTST.W R0, @(-H'1C00,R3)"
          },
          {
            "instruction_address": 16507,
            "instruction_address_hex": "H'407B",
            "operand": "@(-H'1C00,R0)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'1C00,R0)"
          },
          {
            "instruction_address": 48613,
            "instruction_address_hex": "H'BDE5",
            "operand": "@(-H'1C00,R4)",
            "negative_offset": 7168,
            "negative_offset_hex": "H'1C00",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1C00,R4)"
          }
        ],
        "evidence_addresses": [
          6570,
          6731,
          6747,
          6785,
          6836,
          6849,
          16507,
          48613
        ],
        "evidence_addresses_hex": [
          "H'19AA",
          "H'1A4B",
          "H'1A5B",
          "H'1A81",
          "H'1AB4",
          "H'1AC1",
          "H'407B",
          "H'BDE5"
        ],
        "confidence": "candidate-medium",
        "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
      },
      {
        "kind": "logical_table_map_candidate",
        "name_candidate": "current_value_table_candidate",
        "element_candidate": "word_value",
        "logical_base_address": 59392,
        "logical_base_address_hex": "H'E800",
        "negative_offset": 6144,
        "negative_offset_hex": "H'1800",
        "observed_index_registers": [
          "R0",
          "R3",
          "R4"
        ],
        "observed_accesses": [
          "read",
          "write"
        ],
        "observed_widths": [
          2
        ],
        "accesses": [
          {
            "instruction_address": 6665,
            "instruction_address_hex": "H'1A09",
            "operand": "@(-H'1800,R3)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R3",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R1, @(-H'1800,R3)"
          },
          {
            "instruction_address": 6769,
            "instruction_address_hex": "H'1A71",
            "operand": "@(-H'1800,R3)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R3",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1800,R3)"
          },
          {
            "instruction_address": 16272,
            "instruction_address_hex": "H'3F90",
            "operand": "@(-H'1800,R0)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'1800,R0)"
          },
          {
            "instruction_address": 16511,
            "instruction_address_hex": "H'407F",
            "operand": "@(-H'1800,R0)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'1800,R0)"
          },
          {
            "instruction_address": 47925,
            "instruction_address_hex": "H'BB35",
            "operand": "@(-H'1800,R0)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R0",
            "access": "read",
            "width": 2,
            "instruction": "MOV:G.W @(-H'1800,R0), R4"
          },
          {
            "instruction_address": 48249,
            "instruction_address_hex": "H'BC79",
            "operand": "@(-H'1800,R4)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1800,R4)"
          },
          {
            "instruction_address": 48281,
            "instruction_address_hex": "H'BC99",
            "operand": "@(-H'1800,R4)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1800,R4)"
          },
          {
            "instruction_address": 48414,
            "instruction_address_hex": "H'BD1E",
            "operand": "@(-H'1800,R4)",
            "negative_offset": 6144,
            "negative_offset_hex": "H'1800",
            "index_register": "R4",
            "access": "write",
            "width": 2,
            "instruction": "MOV:G.W R0, @(-H'1800,R4)"
          }
        ],
        "evidence_addresses": [
          6665,
          6769,
          16272,
          16511,
          47925,
          48249,
          48281,
          48414
        ],
        "evidence_addresses_hex": [
          "H'1A09",
          "H'1A71",
          "H'3F90",
          "H'407F",
          "H'BB35",
          "H'BC79",
          "H'BC99",
          "H'BD1E"
        ],
        "confidence": "candidate-medium",
        "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
      },
      {
        "kind": "logical_table_map_candidate",
        "name_candidate": "flag_table_candidate",
        "element_candidate": "bit_flags",
        "logical_base_address": 60416,
        "logical_base_address_hex": "H'EC00",
        "negative_offset": 5120,
        "negative_offset_hex": "H'1400",
        "observed_index_registers": [
          "R0",
          "R5"
        ],
        "observed_accesses": [
          "write"
        ],
        "observed_widths": [
          1,
          2
        ],
        "accesses": [
          {
            "instruction_address": 16520,
            "instruction_address_hex": "H'4088",
            "operand": "@(-H'1400,R0)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R0",
            "access": "write",
            "width": 2,
            "instruction": "CLR.W @(-H'1400,R0)"
          },
          {
            "instruction_address": 48258,
            "instruction_address_hex": "H'BC82",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #7, @(-H'1400,R5)"
          },
          {
            "instruction_address": 48285,
            "instruction_address_hex": "H'BC9D",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #7, @(-H'1400,R5)"
          },
          {
            "instruction_address": 48418,
            "instruction_address_hex": "H'BD22",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #7, @(-H'1400,R5)"
          },
          {
            "instruction_address": 48441,
            "instruction_address_hex": "H'BD39",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #7, @(-H'1400,R5)"
          },
          {
            "instruction_address": 48617,
            "instruction_address_hex": "H'BDE9",
            "operand": "@(-H'1400,R5)",
            "negative_offset": 5120,
            "negative_offset_hex": "H'1400",
            "index_register": "R5",
            "access": "write",
            "width": 1,
            "instruction": "BSET.B #6, @(-H'1400,R5)"
          }
        ],
        "evidence_addresses": [
          16520,
          48258,
          48285,
          48418,
          48441,
          48617
        ],
        "evidence_addresses_hex": [
          "H'4088",
          "H'BC82",
          "H'BC9D",
          "H'BD22",
          "H'BD39",
          "H'BDE9"
        ],
        "confidence": "candidate-medium",
        "caveat": "Logical table base is inferred from negative indexed operands only; the table name is a conservative candidate."
      }
    ],
    "state_variable_candidates": [
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "serial_session_flags_candidate",
        "address": 64162,
        "address_hex": "H'FAA2",
        "access_count": 18,
        "read_count": 5,
        "write_count": 13,
        "bit_candidates": [
          3,
          7
        ],
        "immediate_values": [
          3,
          7
        ],
        "immediate_values_hex": [
          "H'0003",
          "H'0007"
        ],
        "accesses": [
          {
            "instruction_address": 47748,
            "instruction_address_hex": "H'BA84",
            "access": "read",
            "mnemonic": "BTST.B",
            "instruction": "BTST.B #3, @H'FAA2",
            "bit": 3,
            "immediate": 3,
            "immediate_hex": "H'03"
          },
          {
            "instruction_address": 47766,
            "instruction_address_hex": "H'BA96",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #3, @H'FAA2",
            "bit": 3,
            "immediate": 3,
            "immediate_hex": "H'03"
          },
          {
            "instruction_address": 47872,
            "instruction_address_hex": "H'BB00",
            "access": "write",
            "mnemonic": "BSET.B",
            "instruction": "BSET.B #3, @H'FAA2",
            "bit": 3,
            "immediate": 3,
            "immediate_hex": "H'03"
          },
          {
            "instruction_address": 48143,
            "instruction_address_hex": "H'BC0F",
            "access": "read",
            "mnemonic": "TST.B",
            "instruction": "TST.B @H'FAA2"
          },
          {
            "instruction_address": 48149,
            "instruction_address_hex": "H'BC15",
            "access": "write",
            "mnemonic": "BSET.B",
            "instruction": "BSET.B #7, @H'FAA2",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48179,
            "instruction_address_hex": "H'BC33",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA2"
          },
          {
            "instruction_address": 48220,
            "instruction_address_hex": "H'BC5C",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #3, @H'FAA2",
            "bit": 3,
            "immediate": 3,
            "immediate_hex": "H'03"
          },
          {
            "instruction_address": 48336,
            "instruction_address_hex": "H'BCD0",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #7, @H'FAA2",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48381,
            "instruction_address_hex": "H'BCFD",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #7, @H'FAA2",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48388,
            "instruction_address_hex": "H'BD04",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #7, @H'FAA2",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48487,
            "instruction_address_hex": "H'BD67",
            "access": "read",
            "mnemonic": "BTST.B",
            "instruction": "BTST.B #3, @H'FAA2",
            "bit": 3,
            "immediate": 3,
            "immediate_hex": "H'03"
          },
          {
            "instruction_address": 48505,
            "instruction_address_hex": "H'BD79",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA2"
          },
          {
            "instruction_address": 48578,
            "instruction_address_hex": "H'BDC2",
            "access": "read",
            "mnemonic": "BTST.B",
            "instruction": "BTST.B #3, @H'FAA2",
            "bit": 3,
            "immediate": 3,
            "immediate_hex": "H'03"
          },
          {
            "instruction_address": 48596,
            "instruction_address_hex": "H'BDD4",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA2"
          },
          {
            "instruction_address": 48621,
            "instruction_address_hex": "H'BDED",
            "access": "read",
            "mnemonic": "BTST.B",
            "instruction": "BTST.B #3, @H'FAA2",
            "bit": 3,
            "immediate": 3,
            "immediate_hex": "H'03"
          },
          {
            "instruction_address": 48639,
            "instruction_address_hex": "H'BDFF",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA2"
          },
          {
            "instruction_address": 48711,
            "instruction_address_hex": "H'BE47",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA2"
          },
          {
            "instruction_address": 48815,
            "instruction_address_hex": "H'BEAF",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA2"
          }
        ],
        "evidence_addresses": [
          47748,
          47766,
          47872,
          48143,
          48149,
          48179,
          48220,
          48336,
          48381,
          48388,
          48487,
          48505,
          48578,
          48596,
          48621,
          48639,
          48711,
          48815
        ],
        "evidence_addresses_hex": [
          "H'BA84",
          "H'BA96",
          "H'BB00",
          "H'BC0F",
          "H'BC15",
          "H'BC33",
          "H'BC5C",
          "H'BCD0",
          "H'BCFD",
          "H'BD04",
          "H'BD67",
          "H'BD79",
          "H'BDC2",
          "H'BDD4",
          "H'BDED",
          "H'BDFF",
          "H'BE47",
          "H'BEAF"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "serial_pending_mask_candidate",
        "address": 64163,
        "address_hex": "H'FAA3",
        "access_count": 10,
        "read_count": 1,
        "write_count": 9,
        "bit_candidates": [
          7
        ],
        "immediate_values": [
          128,
          7
        ],
        "immediate_values_hex": [
          "H'0080",
          "H'0007"
        ],
        "accesses": [
          {
            "instruction_address": 47770,
            "instruction_address_hex": "H'BA9A",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA3"
          },
          {
            "instruction_address": 47953,
            "instruction_address_hex": "H'BB51",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'80, @H'FAA3",
            "immediate": 128,
            "immediate_hex": "H'80"
          },
          {
            "instruction_address": 48227,
            "instruction_address_hex": "H'BC63",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA3"
          },
          {
            "instruction_address": 48501,
            "instruction_address_hex": "H'BD75",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA3"
          },
          {
            "instruction_address": 48592,
            "instruction_address_hex": "H'BDD0",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA3"
          },
          {
            "instruction_address": 48635,
            "instruction_address_hex": "H'BDFB",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA3"
          },
          {
            "instruction_address": 48707,
            "instruction_address_hex": "H'BE43",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA3"
          },
          {
            "instruction_address": 48805,
            "instruction_address_hex": "H'BEA5",
            "access": "write",
            "mnemonic": "AND.B",
            "instruction": "AND.B @H'FAA3, R0"
          },
          {
            "instruction_address": 48809,
            "instruction_address_hex": "H'BEA9",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B R0, @H'FAA3"
          },
          {
            "instruction_address": 48843,
            "instruction_address_hex": "H'BECB",
            "access": "read",
            "mnemonic": "BTST.B",
            "instruction": "BTST.B #7, @H'FAA3",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          }
        ],
        "evidence_addresses": [
          47770,
          47953,
          48227,
          48501,
          48592,
          48635,
          48707,
          48805,
          48809,
          48843
        ],
        "evidence_addresses_hex": [
          "H'BA9A",
          "H'BB51",
          "H'BC63",
          "H'BD75",
          "H'BDD0",
          "H'BDFB",
          "H'BE43",
          "H'BEA5",
          "H'BEA9",
          "H'BECB"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "serial_rx_error_or_retry_gate_candidate",
        "address": 64164,
        "address_hex": "H'FAA4",
        "access_count": 4,
        "read_count": 1,
        "write_count": 3,
        "bit_candidates": [
          7
        ],
        "immediate_values": [
          7
        ],
        "immediate_values_hex": [
          "H'0007"
        ],
        "accesses": [
          {
            "instruction_address": 47959,
            "instruction_address_hex": "H'BB57",
            "access": "write",
            "mnemonic": "BSET.B",
            "instruction": "BSET.B #7, @H'FAA4",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48004,
            "instruction_address_hex": "H'BB84",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA4"
          },
          {
            "instruction_address": 48079,
            "instruction_address_hex": "H'BBCF",
            "access": "read",
            "mnemonic": "BTST.B",
            "instruction": "BTST.B #7, @H'FAA4",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48681,
            "instruction_address_hex": "H'BE29",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #7, @H'FAA4",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          }
        ],
        "evidence_addresses": [
          47959,
          48004,
          48079,
          48681
        ],
        "evidence_addresses_hex": [
          "H'BB57",
          "H'BB84",
          "H'BBCF",
          "H'BE29"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "serial_retry_enable_or_mode_flags_candidate",
        "address": 64165,
        "address_hex": "H'FAA5",
        "access_count": 4,
        "read_count": 4,
        "write_count": 0,
        "bit_candidates": [
          7
        ],
        "immediate_values": [
          7
        ],
        "immediate_values_hex": [
          "H'0007"
        ],
        "accesses": [
          {
            "instruction_address": 16460,
            "instruction_address_hex": "H'404C",
            "access": "read",
            "mnemonic": "BTST.B",
            "instruction": "BTST.B #7, @H'FAA5",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 47754,
            "instruction_address_hex": "H'BA8A",
            "access": "read",
            "mnemonic": "BTST.B",
            "instruction": "BTST.B #7, @H'FAA5",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48685,
            "instruction_address_hex": "H'BE2D",
            "access": "read",
            "mnemonic": "BTST.B",
            "instruction": "BTST.B #7, @H'FAA5",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48798,
            "instruction_address_hex": "H'BE9E",
            "access": "read",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B @H'FAA5, R0"
          }
        ],
        "evidence_addresses": [
          16460,
          47754,
          48685,
          48798
        ],
        "evidence_addresses_hex": [
          "H'404C",
          "H'BA8A",
          "H'BE2D",
          "H'BE9E"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "serial_retry_counter_candidate",
        "address": 64166,
        "address_hex": "H'FAA6",
        "access_count": 3,
        "read_count": 1,
        "write_count": 2,
        "bit_candidates": [],
        "immediate_values": [
          1,
          2
        ],
        "immediate_values_hex": [
          "H'0001",
          "H'0002"
        ],
        "accesses": [
          {
            "instruction_address": 48115,
            "instruction_address_hex": "H'BBF3",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'FAA6"
          },
          {
            "instruction_address": 48691,
            "instruction_address_hex": "H'BE33",
            "access": "write",
            "mnemonic": "ADD:Q.B",
            "instruction": "ADD:Q.B #1, @H'FAA6",
            "immediate": 1,
            "immediate_hex": "H'01"
          },
          {
            "instruction_address": 48695,
            "instruction_address_hex": "H'BE37",
            "access": "read",
            "mnemonic": "CMP:G.B",
            "instruction": "CMP:G.B #H'02, @H'FAA6",
            "immediate": 2,
            "immediate_hex": "H'02"
          }
        ],
        "evidence_addresses": [
          48115,
          48691,
          48695
        ],
        "evidence_addresses_hex": [
          "H'BBF3",
          "H'BE33",
          "H'BE37"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "event_queue_read_cursor_candidate",
        "address": 63924,
        "address_hex": "H'F9B4",
        "access_count": 3,
        "read_count": 1,
        "write_count": 2,
        "bit_candidates": [
          5
        ],
        "immediate_values": [
          1,
          5
        ],
        "immediate_values_hex": [
          "H'0001",
          "H'0005"
        ],
        "accesses": [
          {
            "instruction_address": 48760,
            "instruction_address_hex": "H'BE78",
            "access": "read",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B @H'F9B4, R1"
          },
          {
            "instruction_address": 48789,
            "instruction_address_hex": "H'BE95",
            "access": "write",
            "mnemonic": "ADD:Q.B",
            "instruction": "ADD:Q.B #1, @H'F9B4",
            "immediate": 1,
            "immediate_hex": "H'01"
          },
          {
            "instruction_address": 48793,
            "instruction_address_hex": "H'BE99",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #5, @H'F9B4",
            "bit": 5,
            "immediate": 5,
            "immediate_hex": "H'05"
          }
        ],
        "evidence_addresses": [
          48760,
          48789,
          48793
        ],
        "evidence_addresses_hex": [
          "H'BE78",
          "H'BE95",
          "H'BE99"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "event_queue_write_or_pending_cursor_candidate",
        "address": 63925,
        "address_hex": "H'F9B5",
        "access_count": 8,
        "read_count": 2,
        "write_count": 6,
        "bit_candidates": [
          7
        ],
        "immediate_values": [
          1,
          7
        ],
        "immediate_values_hex": [
          "H'0001",
          "H'0007"
        ],
        "accesses": [
          {
            "instruction_address": 16479,
            "instruction_address_hex": "H'405F",
            "access": "read",
            "mnemonic": "CMP:G.B",
            "instruction": "CMP:G.B @H'F9B5, R2"
          },
          {
            "instruction_address": 47858,
            "instruction_address_hex": "H'BAF2",
            "access": "read",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B @H'F9B5, R1"
          },
          {
            "instruction_address": 48493,
            "instruction_address_hex": "H'BD6D",
            "access": "write",
            "mnemonic": "ADD:Q.B",
            "instruction": "ADD:Q.B #1, @H'F9B5",
            "immediate": 1,
            "immediate_hex": "H'01"
          },
          {
            "instruction_address": 48497,
            "instruction_address_hex": "H'BD71",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #7, @H'F9B5",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48584,
            "instruction_address_hex": "H'BDC8",
            "access": "write",
            "mnemonic": "ADD:Q.B",
            "instruction": "ADD:Q.B #1, @H'F9B5",
            "immediate": 1,
            "immediate_hex": "H'01"
          },
          {
            "instruction_address": 48588,
            "instruction_address_hex": "H'BDCC",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #7, @H'F9B5",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48627,
            "instruction_address_hex": "H'BDF3",
            "access": "write",
            "mnemonic": "ADD:Q.B",
            "instruction": "ADD:Q.B #1, @H'F9B5",
            "immediate": 1,
            "immediate_hex": "H'01"
          },
          {
            "instruction_address": 48631,
            "instruction_address_hex": "H'BDF7",
            "access": "write",
            "mnemonic": "BCLR.B",
            "instruction": "BCLR.B #7, @H'F9B5",
            "bit": 7,
            "immediate": 7,
            "immediate_hex": "H'07"
          }
        ],
        "evidence_addresses": [
          16479,
          47858,
          48493,
          48497,
          48584,
          48588,
          48627,
          48631
        ],
        "evidence_addresses_hex": [
          "H'405F",
          "H'BAF2",
          "H'BD6D",
          "H'BD71",
          "H'BDC8",
          "H'BDCC",
          "H'BDF3",
          "H'BDF7"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "event_queue_base_or_current_slot_candidate",
        "address": 63929,
        "address_hex": "H'F9B9",
        "access_count": 1,
        "read_count": 1,
        "write_count": 0,
        "bit_candidates": [],
        "immediate_values": [],
        "immediate_values_hex": [],
        "accesses": [
          {
            "instruction_address": 48752,
            "instruction_address_hex": "H'BE70",
            "access": "read",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B @H'F9B9, R3"
          }
        ],
        "evidence_addresses": [
          48752
        ],
        "evidence_addresses_hex": [
          "H'BE70"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "serial_tx_busy_timer_candidate",
        "address": 63936,
        "address_hex": "H'F9C0",
        "access_count": 10,
        "read_count": 2,
        "write_count": 8,
        "bit_candidates": [],
        "immediate_values": [
          100,
          31,
          9,
          240,
          65535
        ],
        "immediate_values_hex": [
          "H'0064",
          "H'001F",
          "H'0009",
          "H'00F0",
          "H'FFFF"
        ],
        "accesses": [
          {
            "instruction_address": 47654,
            "instruction_address_hex": "H'BA26",
            "access": "read",
            "mnemonic": "TST.B",
            "instruction": "TST.B @H'F9C0"
          },
          {
            "instruction_address": 47660,
            "instruction_address_hex": "H'BA2C",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'64, @H'F9C0",
            "immediate": 100,
            "immediate_hex": "H'64"
          },
          {
            "instruction_address": 47778,
            "instruction_address_hex": "H'BAA2",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'1F, @H'F9C0",
            "immediate": 31,
            "immediate_hex": "H'1F"
          },
          {
            "instruction_address": 47834,
            "instruction_address_hex": "H'BADA",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'09, @H'F9C0",
            "immediate": 9,
            "immediate_hex": "H'09"
          },
          {
            "instruction_address": 47841,
            "instruction_address_hex": "H'BAE1",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'09, @H'F9C0",
            "immediate": 9,
            "immediate_hex": "H'09"
          },
          {
            "instruction_address": 47848,
            "instruction_address_hex": "H'BAE8",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'F0, @H'F9C0",
            "immediate": 240,
            "immediate_hex": "H'F0"
          },
          {
            "instruction_address": 48669,
            "instruction_address_hex": "H'BE1D",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'1F, @H'F9C0",
            "immediate": 31,
            "immediate_hex": "H'1F"
          },
          {
            "instruction_address": 48702,
            "instruction_address_hex": "H'BE3E",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'1F, @H'F9C0",
            "immediate": 31,
            "immediate_hex": "H'1F"
          },
          {
            "instruction_address": 48878,
            "instruction_address_hex": "H'BEEE",
            "access": "read",
            "mnemonic": "TST.B",
            "instruction": "TST.B @H'F9C0"
          },
          {
            "instruction_address": 48884,
            "instruction_address_hex": "H'BEF4",
            "access": "write",
            "mnemonic": "ADD:Q.B",
            "instruction": "ADD:Q.B #-1, @H'F9C0",
            "immediate": 65535,
            "immediate_hex": "H'FFFF"
          }
        ],
        "evidence_addresses": [
          47654,
          47660,
          47778,
          47834,
          47841,
          47848,
          48669,
          48702,
          48878,
          48884
        ],
        "evidence_addresses_hex": [
          "H'BA26",
          "H'BA2C",
          "H'BAA2",
          "H'BADA",
          "H'BAE1",
          "H'BAE8",
          "H'BE1D",
          "H'BE3E",
          "H'BEEE",
          "H'BEF4"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "idle_heartbeat_gate_countdown_candidate",
        "address": 63940,
        "address_hex": "H'F9C4",
        "access_count": 5,
        "read_count": 2,
        "write_count": 3,
        "bit_candidates": [],
        "immediate_values": [
          20,
          7,
          65535
        ],
        "immediate_values_hex": [
          "H'0014",
          "H'0007",
          "H'FFFF"
        ],
        "accesses": [
          {
            "instruction_address": 16454,
            "instruction_address_hex": "H'4046",
            "access": "read",
            "mnemonic": "TST.B",
            "instruction": "TST.B @H'F9C4"
          },
          {
            "instruction_address": 16608,
            "instruction_address_hex": "H'40E0",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'14, @H'F9C4",
            "immediate": 20,
            "immediate_hex": "H'14"
          },
          {
            "instruction_address": 47665,
            "instruction_address_hex": "H'BA31",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'07, @H'F9C4",
            "immediate": 7,
            "immediate_hex": "H'07"
          },
          {
            "instruction_address": 48935,
            "instruction_address_hex": "H'BF27",
            "access": "read",
            "mnemonic": "TST.B",
            "instruction": "TST.B @H'F9C4"
          },
          {
            "instruction_address": 48941,
            "instruction_address_hex": "H'BF2D",
            "access": "write",
            "mnemonic": "ADD:Q.B",
            "instruction": "ADD:Q.B #-1, @H'F9C4",
            "immediate": 65535,
            "immediate_hex": "H'FFFF"
          }
        ],
        "evidence_addresses": [
          16454,
          16608,
          47665,
          48935,
          48941
        ],
        "evidence_addresses_hex": [
          "H'4046",
          "H'40E0",
          "H'BA31",
          "H'BF27",
          "H'BF2D"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "rx_session_timeout_candidate",
        "address": 63941,
        "address_hex": "H'F9C5",
        "access_count": 4,
        "read_count": 1,
        "write_count": 3,
        "bit_candidates": [],
        "immediate_values": [
          20,
          65535
        ],
        "immediate_values_hex": [
          "H'0014",
          "H'FFFF"
        ],
        "accesses": [
          {
            "instruction_address": 48030,
            "instruction_address_hex": "H'BB9E",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'14, @H'F9C5",
            "immediate": 20,
            "immediate_hex": "H'14"
          },
          {
            "instruction_address": 48868,
            "instruction_address_hex": "H'BEE4",
            "access": "write",
            "mnemonic": "CLR.B",
            "instruction": "CLR.B @H'F9C5"
          },
          {
            "instruction_address": 48945,
            "instruction_address_hex": "H'BF31",
            "access": "read",
            "mnemonic": "TST.B",
            "instruction": "TST.B @H'F9C5"
          },
          {
            "instruction_address": 48951,
            "instruction_address_hex": "H'BF37",
            "access": "write",
            "mnemonic": "ADD:Q.B",
            "instruction": "ADD:Q.B #-1, @H'F9C5",
            "immediate": 65535,
            "immediate_hex": "H'FFFF"
          }
        ],
        "evidence_addresses": [
          48030,
          48868,
          48945,
          48951
        ],
        "evidence_addresses_hex": [
          "H'BB9E",
          "H'BEE4",
          "H'BF31",
          "H'BF37"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "autonomous_report_period_timer_candidate",
        "address": 63942,
        "address_hex": "H'F9C6",
        "access_count": 5,
        "read_count": 2,
        "write_count": 3,
        "bit_candidates": [],
        "immediate_values": [
          500,
          65535
        ],
        "immediate_values_hex": [
          "H'01F4",
          "H'FFFF"
        ],
        "accesses": [
          {
            "instruction_address": 47942,
            "instruction_address_hex": "H'BB46",
            "access": "write",
            "mnemonic": "MOV:G.W",
            "instruction": "MOV:G.W #H'01F4, @H'F9C6",
            "immediate": 500,
            "immediate_hex": "H'01F4"
          },
          {
            "instruction_address": 48821,
            "instruction_address_hex": "H'BEB5",
            "access": "read",
            "mnemonic": "TST.W",
            "instruction": "TST.W @H'F9C6"
          },
          {
            "instruction_address": 48837,
            "instruction_address_hex": "H'BEC5",
            "access": "write",
            "mnemonic": "MOV:G.W",
            "instruction": "MOV:G.W #H'01F4, @H'F9C6",
            "immediate": 500,
            "immediate_hex": "H'01F4"
          },
          {
            "instruction_address": 48898,
            "instruction_address_hex": "H'BF02",
            "access": "read",
            "mnemonic": "TST.W",
            "instruction": "TST.W @H'F9C6"
          },
          {
            "instruction_address": 48904,
            "instruction_address_hex": "H'BF08",
            "access": "write",
            "mnemonic": "ADD:Q.W",
            "instruction": "ADD:Q.W #-1, @H'F9C6",
            "immediate": 65535,
            "immediate_hex": "H'FFFF"
          }
        ],
        "evidence_addresses": [
          47942,
          48821,
          48837,
          48898,
          48904
        ],
        "evidence_addresses_hex": [
          "H'BB46",
          "H'BEB5",
          "H'BEC5",
          "H'BF02",
          "H'BF08"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      },
      {
        "kind": "serial_state_variable_candidate",
        "name_candidate": "autonomous_report_resend_countdown_candidate",
        "address": 63944,
        "address_hex": "H'F9C8",
        "access_count": 3,
        "read_count": 1,
        "write_count": 2,
        "bit_candidates": [],
        "immediate_values": [
          20,
          65535
        ],
        "immediate_values_hex": [
          "H'0014",
          "H'FFFF"
        ],
        "accesses": [
          {
            "instruction_address": 47948,
            "instruction_address_hex": "H'BB4C",
            "access": "write",
            "mnemonic": "MOV:G.B",
            "instruction": "MOV:G.B #H'14, @H'F9C8",
            "immediate": 20,
            "immediate_hex": "H'14"
          },
          {
            "instruction_address": 48827,
            "instruction_address_hex": "H'BEBB",
            "access": "read",
            "mnemonic": "TST.B",
            "instruction": "TST.B @H'F9C8"
          },
          {
            "instruction_address": 48833,
            "instruction_address_hex": "H'BEC1",
            "access": "write",
            "mnemonic": "ADD:Q.B",
            "instruction": "ADD:Q.B #-1, @H'F9C8",
            "immediate": 65535,
            "immediate_hex": "H'FFFF"
          }
        ],
        "evidence_addresses": [
          47948,
          48827,
          48833
        ],
        "evidence_addresses_hex": [
          "H'BB4C",
          "H'BEBB",
          "H'BEC1"
        ],
        "confidence": "candidate-medium",
        "caveat": "Role is inferred from references in serial handler, gate, and timer regions and remains a state-variable candidate."
      }
    ],
    "retry_error_model": {
      "kind": "serial_retry_error_model_candidate",
      "checksum_failure_path": {
        "condition_candidate": "0x5A-seeded XOR over RX[0..4] differs from RX[5]",
        "error_target": "loc_BE29",
        "error_target_address": 48681,
        "error_target_address_hex": "H'BE29",
        "checksum_error_response_candidates": [
          "response_at_BE6A"
        ],
        "branch_evidence_addresses": [
          48112
        ],
        "branch_evidence_addresses_hex": [
          "H'BBF0"
        ],
        "evidence_addresses": [
          48088,
          48092,
          48096,
          48100,
          48104,
          48108,
          48112,
          48717,
          48726,
          48734,
          48742,
          48722,
          48730,
          48738,
          48746
        ],
        "evidence_addresses_hex": [
          "H'BBD8",
          "H'BBDC",
          "H'BBE0",
          "H'BBE4",
          "H'BBE8",
          "H'BBEC",
          "H'BBF0",
          "H'BE4D",
          "H'BE56",
          "H'BE5E",
          "H'BE66",
          "H'BE52",
          "H'BE5A",
          "H'BE62",
          "H'BE6A"
        ],
        "confidence": "candidate-high"
      },
      "retry_path": {
        "entry_label": "loc_BE29",
        "entry_address": 48681,
        "entry_address_hex": "H'BE29",
        "counter_address": 64166,
        "counter_address_hex": "H'FAA6",
        "threshold_candidate": 2,
        "response_candidates": [
          "response_at_BE6A"
        ],
        "summary": "Candidate retry path clears/consults serial flags, increments FAA6, compares it with 2, and when still below the apparent limit enters loc_BE4D to stage a command 0x07 retry/error echo of RX payload bytes F861-F864.",
        "echo_response_candidate": {
          "entry_label": "loc_BE4D",
          "entry_address": 48717,
          "entry_address_hex": "H'BE4D",
          "staging_candidate": "F850=0x07; F851-F854=F861-F864",
          "observed_frame_caveat": "07 80 40 20 90 2D echoes RX payload 80 40 20 90 and is not a table value."
        },
        "evidence_addresses": [
          48681,
          48685,
          48691,
          48695,
          48707,
          48711,
          48717,
          48726,
          48734,
          48742,
          48722,
          48730,
          48738,
          48746
        ],
        "evidence_addresses_hex": [
          "H'BE29",
          "H'BE2D",
          "H'BE33",
          "H'BE37",
          "H'BE43",
          "H'BE47",
          "H'BE4D",
          "H'BE56",
          "H'BE5E",
          "H'BE66",
          "H'BE52",
          "H'BE5A",
          "H'BE62",
          "H'BE6A"
        ],
        "confidence": "candidate-medium"
      },
      "command_0x07_path": {
        "entry_label": "loc_BE05",
        "entry_address": 48645,
        "entry_address_hex": "H'BE05",
        "response_candidates": [
          "response_at_BE22"
        ],
        "summary": "Candidate retransmit/explicit command 0x07 path either copies previous TX frame bytes back to F850-F854 or stages an observed 0x07 response before loc_BA26.",
        "evidence_addresses": [
          48645,
          48653,
          48661,
          48649,
          48657,
          48665,
          48674
        ],
        "evidence_addresses_hex": [
          "H'BE05",
          "H'BE0D",
          "H'BE15",
          "H'BE09",
          "H'BE11",
          "H'BE19",
          "H'BE22"
        ],
        "confidence": "candidate-medium"
      },
      "evidence_addresses": [
        48088,
        48092,
        48096,
        48100,
        48104,
        48108,
        48112,
        48717,
        48726,
        48734,
        48742,
        48722,
        48730,
        48738,
        48746,
        48681,
        48685,
        48691,
        48695,
        48707,
        48711,
        48645,
        48653,
        48661,
        48649,
        48657,
        48665,
        48674
      ],
      "evidence_addresses_hex": [
        "H'BBD8",
        "H'BBDC",
        "H'BBE0",
        "H'BBE4",
        "H'BBE8",
        "H'BBEC",
        "H'BBF0",
        "H'BE4D",
        "H'BE56",
        "H'BE5E",
        "H'BE66",
        "H'BE52",
        "H'BE5A",
        "H'BE62",
        "H'BE6A",
        "H'BE29",
        "H'BE2D",
        "H'BE33",
        "H'BE37",
        "H'BE43",
        "H'BE47",
        "H'BE05",
        "H'BE0D",
        "H'BE15",
        "H'BE09",
        "H'BE11",
        "H'BE19",
        "H'BE22"
      ],
      "confidence": "candidate-medium",
      "caveat": "The retry/error model is inferred from checksum branch targets, retry-counter state, and response staging; exact host-visible semantics remain candidate phrasing."
    },
    "gate_queue_model": {
      "kind": "serial_gate_queue_state_machine_candidate",
      "summary": "Conservative model for autonomous report gating, queue cursor comparison, periodic resend, and RX/session side effects.",
      "predicates": [
        {
          "name": "main_loop_may_enter_report_builder",
          "entry_label": "loc_3FD3",
          "target_label": "loc_BAF2",
          "condition_candidate": "FAA2 == 0 && F9C0 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0))",
          "summary": "Main-loop report gate; session must be idle, TX busy timer clear, and RX gate open.",
          "state_addresses_hex": [
            "H'FAA2",
            "H'FAA5",
            "H'F9C3",
            "H'F9C0"
          ],
          "evidence_addresses": [
            16339,
            16343,
            16345,
            16349,
            16351,
            16355,
            16357,
            16361,
            16363
          ]
        },
        {
          "name": "idle_heartbeat_report_may_enqueue",
          "entry_label": "loc_4046",
          "target_label": "loc_4067",
          "condition_candidate": "F9C4 == 0 && ((FAA5.bit7 == 0) || (F9C3 == 0)) && F9B0 == F9B5",
          "summary": "Idle/default report gate; when the FRT2 countdown clears and the queue is empty, loc_4046 can enqueue H'0000 for the later loc_BAF2 -> loc_BA26 send path.",
          "state_addresses_hex": [
            "H'F9C4",
            "H'FAA5",
            "H'F9C3",
            "H'F9B0",
            "H'F9B5"
          ],
          "enqueued_report_candidate_hex": "H'0000",
          "write_semantics_candidate": "loc_4067 is MOV:G.W #H'00, @(-H'0790,R2): the byte immediate is zero-extended by the word destination, so the queue slot becomes H'0000.",
          "runtime_trace_confirmation": {
            "source": "h8536_emulator_probe target-frame run",
            "report_id_hex": "H'0000",
            "queue_write_address_hex": "H'4067",
            "queue_write_semantics": "H'FFFF -> H'0000, not H'00FF",
            "dequeue_path": [
              "loc_4046",
              "loc_BAF2",
              "loc_BB08",
              "loc_BB1C",
              "loc_BB20",
              "loc_BB2B",
              "loc_BA26"
            ],
            "emitted_frame_hex": "00 00 00 00 80 DA",
            "checksum_seed_hex": "H'5A",
            "checksum_hex": "H'DA"
          },
          "evidence_addresses": [
            16454,
            16458,
            16460,
            16464,
            16466,
            16470,
            16472,
            16473,
            16477,
            16479,
            16483,
            16485,
            16487,
            16492,
            16496
          ]
        },
        {
          "name": "queue_has_pending_report",
          "entry_label": "loc_BAF2",
          "condition_candidate": "F9B5 != F9B0",
          "summary": "Queue/pending cursor gate; non-empty state stages through BB43 before loc_BA26.",
          "state_addresses_hex": [
            "H'F9B5",
            "H'F9B0"
          ],
          "staging_path": [
            "loc_BAF2",
            "loc_BB43",
            "loc_BA26"
          ],
          "evidence_addresses": [
            47858,
            47862,
            47864,
            47868,
            47870,
            47872,
            47876,
            47878,
            47880,
            47884,
            47886,
            47889,
            47891,
            47893,
            47895,
            47897,
            47900,
            47904,
            47908,
            47910,
            47913,
            47915,
            47919,
            47923,
            47925,
            47929,
            47933,
            47935,
            47939
          ]
        },
        {
          "name": "periodic_resend_may_fire",
          "entry_label": "loc_BE9E",
          "target_label": "loc_BED5",
          "condition_candidate": "(FAA5 & FAA3 & 0x80) != 0 && F9C6 == 0 && F9C8 != 0 after countdown",
          "summary": "Resend gate masks pending state with FAA5, checks F9C6/F9C8, then calls BA26 at BED5.",
          "state_addresses_hex": [
            "H'FAA5",
            "H'FAA3",
            "H'F9C6",
            "H'F9C8"
          ],
          "evidence_addresses": [
            48798,
            48802,
            48805,
            48809,
            48813,
            48815,
            48819,
            48821,
            48825,
            48827,
            48831,
            48833,
            48837,
            48843,
            48847,
            48849,
            48853
          ]
        }
      ],
      "session_effects": [
        {
          "name": "rx_completion_sets_session_timer",
          "summary": "RX completion sets F9C5 (observed reload H'14) after the sixth byte is captured.",
          "state_addresses_hex": [
            "H'F9C5"
          ],
          "evidence_addresses": [
            48030
          ]
        },
        {
          "name": "session_timeout_clears_gate_and_queue",
          "entry_label": "loc_3FEF",
          "summary": "When F9C5 is clear, loc_3FEF clears F9B5/F9B0 and clears FAA5.bit7; when nonzero, it sets FAA5.bit7.",
          "state_addresses_hex": [
            "H'F9C5",
            "H'F9B5",
            "H'F9B0",
            "H'FAA5"
          ],
          "evidence_addresses": [
            16367,
            16371,
            16373,
            16377,
            16381,
            16385,
            16387,
            16389,
            16391
          ]
        },
        {
          "name": "idle_heartbeat_gate_initial_delay_loaded",
          "summary": "Startup/init loads F9C4 with H'14 before the first idle/default report can be queued.",
          "state_addresses_hex": [
            "H'F9C4"
          ],
          "reload_value_hex": "H'14",
          "evidence_addresses": [
            16608
          ]
        },
        {
          "name": "idle_heartbeat_gate_post_send_delay_loaded",
          "summary": "loc_BA26 reloads F9C4 with H'07 after each send, matching the observed heartbeat spacing.",
          "state_addresses_hex": [
            "H'F9C4"
          ],
          "reload_value_hex": "H'07",
          "evidence_addresses": [
            47665
          ]
        },
        {
          "name": "host_ack_can_advance_queue",
          "summary": "Command 0x05 is a continuation-only ACK/session clear path: it clears FAA3/FAA2 and advances F9B5 only when queued-report FAA2.bit3 was set. Selector 0x0040 has no response; if FAA2 == 0 the command falls through instead of doing ACK work.",
          "command_values_hex": [
            "H'05"
          ],
          "state_addresses_hex": [
            "H'FAA2",
            "H'FAA3",
            "H'F9B5"
          ],
          "evidence_addresses": [
            48136,
            48140,
            48202,
            48204
          ]
        }
      ],
      "caveat": "Many panel controls may require host/session traffic before reporting. Observed autonomous call/camera-power indexes are runtime/capture overlays, not ROM constants.",
      "confidence": "candidate-medium",
      "evidence_addresses": [
        16339,
        16343,
        16345,
        16349,
        16351,
        16355,
        16357,
        16361,
        16363,
        16367,
        16371,
        16373,
        16377,
        16381,
        16385,
        16387,
        16389,
        16391,
        16454,
        16458,
        16460,
        16464,
        16466,
        16470,
        16472,
        16473,
        16477,
        16479,
        16483,
        16485,
        16487,
        16492,
        16496,
        47858,
        47862,
        47864,
        47868,
        47870,
        47872,
        47876,
        47878,
        47880,
        47884,
        47886,
        47889,
        47891,
        47893,
        47895,
        47897,
        47900,
        47904,
        47908,
        47910,
        47913,
        47915,
        47919,
        47923,
        47925,
        47929,
        47933,
        47935,
        47939,
        48798,
        48802,
        48805,
        48809,
        48813,
        48815,
        48819,
        48821,
        48825,
        48827,
        48831,
        48833,
        48837,
        48843,
        48847,
        48849,
        48853
      ],
      "evidence_addresses_hex": [
        "H'3FD3",
        "H'3FD7",
        "H'3FD9",
        "H'3FDD",
        "H'3FDF",
        "H'3FE3",
        "H'3FE5",
        "H'3FE9",
        "H'3FEB",
        "H'3FEF",
        "H'3FF3",
        "H'3FF5",
        "H'3FF9",
        "H'3FFD",
        "H'4001",
        "H'4003",
        "H'4005",
        "H'4007",
        "H'4046",
        "H'404A",
        "H'404C",
        "H'4050",
        "H'4052",
        "H'4056",
        "H'4058",
        "H'4059",
        "H'405D",
        "H'405F",
        "H'4063",
        "H'4065",
        "H'4067",
        "H'406C",
        "H'4070",
        "H'BAF2",
        "H'BAF6",
        "H'BAF8",
        "H'BAFC",
        "H'BAFE",
        "H'BB00",
        "H'BB04",
        "H'BB06",
        "H'BB08",
        "H'BB0C",
        "H'BB0E",
        "H'BB11",
        "H'BB13",
        "H'BB15",
        "H'BB17",
        "H'BB19",
        "H'BB1C",
        "H'BB20",
        "H'BB24",
        "H'BB26",
        "H'BB29",
        "H'BB2B",
        "H'BB2F",
        "H'BB33",
        "H'BB35",
        "H'BB39",
        "H'BB3D",
        "H'BB3F",
        "H'BB43",
        "H'BE9E",
        "H'BEA2",
        "H'BEA5",
        "H'BEA9",
        "H'BEAD",
        "H'BEAF",
        "H'BEB3",
        "H'BEB5",
        "H'BEB9",
        "H'BEBB",
        "H'BEBF",
        "H'BEC1",
        "H'BEC5",
        "H'BECB",
        "H'BECF",
        "H'BED1",
        "H'BED5"
      ]
    },
    "tx_report_model": {
      "kind": "bb43_to_ba26_tx_report_model_candidate",
      "direction": "device_to_host_autonomous_report_candidate",
      "entry_label": "loc_BB43",
      "entry_address": 47939,
      "entry_address_hex": "H'BB43",
      "send_builder": "loc_BA26",
      "send_builder_address": 47654,
      "send_builder_address_hex": "H'BA26",
      "response_candidates": [
        "response_at_BB43"
      ],
      "summary": "TX report bytes 0..2 are computed encoded logical index/report id bytes, bytes 3..4 come from current_value_table_candidate, and byte5 is the 0x5A XOR checksum.",
      "byte_roles": [
        {
          "offset": 0,
          "field_candidate": "encoded_logical_index_or_report_id_byte0",
          "source_candidate": "computed from candidate logical index/report id"
        },
        {
          "offset": 1,
          "field_candidate": "encoded_logical_index_or_report_id_byte1",
          "source_candidate": "computed from candidate logical index/report id"
        },
        {
          "offset": 2,
          "field_candidate": "encoded_logical_index_or_report_id_byte2",
          "source_candidate": "computed from candidate logical index/report id"
        },
        {
          "offset": 3,
          "field_candidate": "current_value_hi",
          "source_candidate": "current_value_table_candidate high byte",
          "table_candidate": "current_value_table_candidate"
        },
        {
          "offset": 4,
          "field_candidate": "current_value_lo",
          "source_candidate": "current_value_table_candidate low byte",
          "table_candidate": "current_value_table_candidate"
        },
        {
          "offset": 5,
          "field_candidate": "checksum",
          "source_candidate": "0x5A XOR TX[0..4]"
        }
      ],
      "value_source_candidate": "current_value_table_candidate",
      "checksum_formula": "checksum = 0x5A ^ byte0 ^ byte1 ^ byte2 ^ byte3 ^ byte4",
      "observed_capture_overlay_candidates": [
        {
          "logical_index": 0,
          "name_candidate": "heartbeat_or_idle_report_candidate",
          "observed_frames_hex": [
            "00 00 00 00 80 DA"
          ],
          "observed_period_ms_candidate": 700
        },
        {
          "logical_index": 21,
          "name_candidate": "call_button_report_candidate",
          "observed_frames_hex": [
            "00 00 15 80 00 CF",
            "00 00 15 00 00 4F"
          ]
        },
        {
          "logical_index": 7,
          "name_candidate": "camera_power_report_candidate",
          "observed_frames_hex": [
            "00 00 07 80 00 DD"
          ]
        }
      ],
      "runtime_confirmed_paths": [
        {
          "name": "idle_heartbeat_report_runtime_confirmation",
          "report_id_hex": "H'0000",
          "queue_write_address_hex": "H'4067",
          "queue_write_semantics": "MOV:G.W #H'00 writes H'0000 to the queue slot",
          "staging_path": [
            "loc_4046",
            "loc_BAF2",
            "loc_BB08",
            "loc_BB1C",
            "loc_BB20",
            "loc_BB2B",
            "loc_BA26"
          ],
          "emitted_frame_hex": "00 00 00 00 80 DA",
          "checksum_hex": "H'DA"
        }
      ],
      "consistency_checks": [
        {
          "name": "idle_heartbeat_report_id_width",
          "status": "pass",
          "summary": "Decompiler mnemonic MOV:G.W and emulator execution now agree that the H'00 immediate at loc_4067 is zero-extended to report H'0000."
        }
      ],
      "observed_autonomous_output_caveat": "Real captures supplied so far show only heartbeat/idle, call, and camera-power autonomous TX frames. Other panel controls may require a host/device request or state transition before the firmware reports them.",
      "confidence": "candidate-medium",
      "caveat": "This is a TX/report model for the BB43 -> BA26 path, separate from RX command dispatch. Observed report names are a capture overlay candidate only, not hard-coded source truth.",
      "evidence_addresses": [
        47900,
        47904,
        47915,
        47929,
        47935,
        47939
      ],
      "evidence_addresses_hex": [
        "H'BB1C",
        "H'BB20",
        "H'BB2B",
        "H'BB39",
        "H'BB3F",
        "H'BB43"
      ]
    },
    "periodic_resend_model": {
      "kind": "autonomous_periodic_resend_model_candidate",
      "period_timer": {
        "address": 63942,
        "address_hex": "H'F9C6",
        "reload_value_candidate": 500,
        "reload_value_hex": "H'01F4",
        "summary": "Candidate periodic report/heartbeat timer reload.",
        "evidence_addresses": [
          47942,
          48837
        ],
        "evidence_addresses_hex": [
          "H'BB46",
          "H'BEC5"
        ]
      },
      "resend_countdown": {
        "address": 63944,
        "address_hex": "H'F9C8",
        "reload_value_candidate": 20,
        "reload_value_hex": "H'14",
        "summary": "Candidate periodic resend countdown/retry spacing value.",
        "evidence_addresses": [
          47948
        ],
        "evidence_addresses_hex": [
          "H'BB4C"
        ]
      },
      "pending_mask": {
        "address": 64163,
        "address_hex": "H'FAA3",
        "mask_candidate": 128,
        "mask_hex": "H'80",
        "summary": "Candidate bit/mask that marks an autonomous report pending.",
        "evidence_addresses": [
          47953,
          48843
        ],
        "evidence_addresses_hex": [
          "H'BB51",
          "H'BECB"
        ]
      },
      "resend_path": {
        "entry_label": "loc_BED5",
        "entry_address": 48853,
        "entry_address_hex": "H'BED5",
        "summary": "Candidate periodic resend path feeding the TX staging/send-builder flow.",
        "evidence_addresses": [
          48853
        ],
        "evidence_addresses_hex": [
          "H'BED5"
        ]
      },
      "evidence_addresses": [
        47942,
        48837,
        47948,
        47953,
        48843,
        48853
      ],
      "evidence_addresses_hex": [
        "H'BB46",
        "H'BEC5",
        "H'BB4C",
        "H'BB51",
        "H'BECB",
        "H'BED5"
      ],
      "confidence": "candidate-medium",
      "caveat": "Timer and resend roles are inferred from constants/state references around F9C6, F9C8, FAA3, and loc_BED5; exact scheduling units remain candidate phrasing."
    },
    "timer_interrupt_model": {
      "kind": "timer_interrupt_model_candidate",
      "source": "FRT1 OCIA / FRT2 OCIA",
      "summary": "FRT compare-match handlers decrement serial gate, timeout, and cadence counters.",
      "sources": [
        {
          "source": "FRT1 OCIA",
          "vector_address_hex": "H'0062",
          "handler_address": 48874,
          "handler_address_hex": "H'BEEA",
          "summary": "Candidate periodic tick ISR for serial busy, interbyte, and resend counters.",
          "counters": [
            {
              "address": 63936,
              "address_hex": "H'F9C0",
              "name_candidate": "tx_report_gate_counter_candidate",
              "role": "candidate gate counter used before entering the report builder.",
              "evidence_address": 48884,
              "evidence_address_hex": "H'BEF4"
            },
            {
              "address": 63937,
              "address_hex": "H'F9C1",
              "name_candidate": "rx_interbyte_timeout_candidate",
              "role": "candidate RX interbyte timeout counter.",
              "evidence_address": 48894,
              "evidence_address_hex": "H'BEFE"
            },
            {
              "address": 63942,
              "address_hex": "H'F9C6",
              "name_candidate": "periodic_resend_cadence_counter_candidate",
              "role": "candidate periodic resend/heartbeat cadence counter.",
              "evidence_address": 48904,
              "evidence_address_hex": "H'BF08"
            }
          ],
          "evidence_addresses": [
            48874,
            48878,
            48882,
            48884,
            48888,
            48892,
            48894,
            48898,
            48902,
            48904
          ],
          "evidence_addresses_hex": [
            "H'BEEA",
            "H'BEEE",
            "H'BEF2",
            "H'BEF4",
            "H'BEF8",
            "H'BEFC",
            "H'BEFE",
            "H'BF02",
            "H'BF06",
            "H'BF08"
          ]
        },
        {
          "source": "FRT2 OCIA",
          "vector_address_hex": "H'006A",
          "handler_address": 48931,
          "handler_address_hex": "H'BF23",
          "summary": "Candidate periodic tick ISR for idle heartbeat/report and RX session counters.",
          "clock_select": "CKS1=1 CKS0=0 => phi/32",
          "ocra_value_hex": "H'7A12",
          "manual_reference": "Manual/0900766b802125d0.md:12038 FRT CKS1/CKS0 clock select",
          "counters": [
            {
              "address": 63940,
              "address_hex": "H'F9C4",
              "name_candidate": "idle_heartbeat_gate_countdown_candidate",
              "role": "candidate idle/default report enqueue countdown.",
              "evidence_address": 48941,
              "evidence_address_hex": "H'BF2D"
            },
            {
              "address": 63941,
              "address_hex": "H'F9C5",
              "name_candidate": "rx_session_timeout_candidate",
              "role": "candidate RX/session maintenance timeout counter.",
              "evidence_address": 48951,
              "evidence_address_hex": "H'BF37"
            }
          ],
          "evidence_addresses": [
            48931,
            48935,
            48939,
            48941,
            48945,
            48949,
            48951
          ],
          "evidence_addresses_hex": [
            "H'BF23",
            "H'BF27",
            "H'BF2B",
            "H'BF2D",
            "H'BF31",
            "H'BF35",
            "H'BF37"
          ]
        }
      ],
      "counters": [
        {
          "address": 63936,
          "address_hex": "H'F9C0",
          "name_candidate": "tx_report_gate_counter_candidate",
          "role": "candidate gate counter used before entering the report builder.",
          "evidence_address": 48884,
          "evidence_address_hex": "H'BEF4"
        },
        {
          "address": 63937,
          "address_hex": "H'F9C1",
          "name_candidate": "rx_interbyte_timeout_candidate",
          "role": "candidate RX interbyte timeout counter.",
          "evidence_address": 48894,
          "evidence_address_hex": "H'BEFE"
        },
        {
          "address": 63942,
          "address_hex": "H'F9C6",
          "name_candidate": "periodic_resend_cadence_counter_candidate",
          "role": "candidate periodic resend/heartbeat cadence counter.",
          "evidence_address": 48904,
          "evidence_address_hex": "H'BF08"
        },
        {
          "address": 63940,
          "address_hex": "H'F9C4",
          "name_candidate": "idle_heartbeat_gate_countdown_candidate",
          "role": "candidate idle/default report enqueue countdown.",
          "evidence_address": 48941,
          "evidence_address_hex": "H'BF2D"
        },
        {
          "address": 63941,
          "address_hex": "H'F9C5",
          "name_candidate": "rx_session_timeout_candidate",
          "role": "candidate RX/session maintenance timeout counter.",
          "evidence_address": 48951,
          "evidence_address_hex": "H'BF37"
        }
      ],
      "evidence_addresses": [
        48874,
        48878,
        48882,
        48884,
        48888,
        48892,
        48894,
        48898,
        48902,
        48904,
        48931,
        48935,
        48939,
        48941,
        48945,
        48949,
        48951
      ],
      "evidence_addresses_hex": [
        "H'BEEA",
        "H'BEEE",
        "H'BEF2",
        "H'BEF4",
        "H'BEF8",
        "H'BEFC",
        "H'BEFE",
        "H'BF02",
        "H'BF06",
        "H'BF08",
        "H'BF23",
        "H'BF27",
        "H'BF2B",
        "H'BF2D",
        "H'BF31",
        "H'BF35",
        "H'BF37"
      ],
      "confidence": "candidate-medium"
    },
    "confidence": "medium-high",
    "confidence_score": 0.9,
    "caveat": "Semantic names are candidates only. The analyzer reports byte roles, command values, dispatch targets, and response staging patterns observed in code; it does not prove source-level intent or protocol documentation."
  }
}