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Aiden
@@ -118,6 +118,99 @@ Useful implication:
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- `CN1` is now the strongest candidate for the board-side harness/IO connector
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that should be traced against the external 10-pin cable assembly
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### `CN1` Continuity Mapping
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Based on your continuity tracing and the board silkscreen numbering:
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| `CN1` pin | Observed function | Internal wire color | External 10-pin |
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| --- | --- | --- | --- |
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| `1` | `VBS (X) IN` | white | pin `2` |
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| `2` | `VBS (G) IN` | blue | pin `3` |
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| `3` | data ground | grey | pin `5` |
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| `4` | data `RCP -> CCU` | yellow | pin `4` |
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| `5` | data `CCU -> RCP` | orange | pin `7` |
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| `6` | data ground | brown | pin `6` |
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| `7` | ground | black | pin `9` |
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| `8` | `DC+` | red | pin `10` |
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Important observations:
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- `CN1` pin `7` is the main ground path and maps to external pin `9`
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- `CN1` pin `8` is DC power and maps to external pin `10`
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- the serial pair is now clearly confirmed at the board level:
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- `CN1` pin `4` / external pin `4` = `RCP -> CCU`
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- `CN1` pin `5` / external pin `7` = `CCU -> RCP`
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- there are **two additional non-serial signal inputs** on external pins `2`
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and `3`
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- there are **two separate data-ground/return lines** on external pins `5` and
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`6`
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Very important electrical note from tracing:
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- the two data-ground lines (`CN1` pins `3` and `6`) were observed as **not
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connected to common ground**
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That strongly suggests the connector is not just:
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- power
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- one TX line
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- one RX line
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Instead, it likely carries a mixed signal set with at least:
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- analog/video-related inputs
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- serial/control
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- separate signal returns
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- power/common ground
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Refined grounding observation:
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- the separate data grounds appear to connect to common ground **through small
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ceramic capacitors** near the connector
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- the relevant parts are labeled:
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- `C55`
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- `C56`
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This changes the interpretation from "totally isolated grounds" to something
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more like:
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- DC-isolated or not directly hard-tied
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- but AC-coupled / noise-referenced to common ground
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That is a very plausible arrangement for:
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- signal-return noise control
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- EMI filtering
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- keeping the data pair referenced without fully hard-bonding the return paths
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### Manual Cross-Check: External Connector Signals
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The manual fragment for the external connector aligns very strongly with the
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continuity map we traced:
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| External pin | Manual signal | Notes |
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| --- | --- | --- |
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| `1` | `(SPARE)` | matches the fact that it has not appeared on `CN1` |
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| `2` | `VBS (X) IN` | manual notes `1.0 Vp-p, sync negative` |
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| `3` | `VBS (G) IN` | confirms a second VBS input line |
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| `4` | `S. DATA (RCP -> CCU)` | matches traced serial-out line |
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| `5` | `S. DATA GND` | matches traced separate data ground |
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| `6` | `S. DATA GND` | matches traced separate data ground |
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| `7` | `S. DATA (CCU -> RCP)` | matches traced serial-in line |
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This is a strong confirmation that the harness tracing is fundamentally right.
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Big implication:
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- `VBS (X) IN` and `VBS (G) IN` are not mystery wires anymore
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- they are documented inputs and are likely meaningful to normal panel
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operation
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- the wake/session problem may therefore depend on more than serial traffic,
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although board-level routing now suggests that may vary by revision/options
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The manual wording also strengthens the idea that these are likely
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video/reference-style inputs rather than general-purpose logic lines.
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### H8 / DIP Area
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- the H8 marking is now clearly readable in-package as:
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@@ -163,6 +256,117 @@ Working interpretation:
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- nearby resistor-network and option-footprint areas also fit the picture of a
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configurable CPU/control board with variant population options
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### Serial Interface Confirmation
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Tracing from the connector into the board:
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- external pin `4` / `CN1` pin `4` goes to a `MAX202` device at package pad
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`14`
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- external pin `7` / `CN1` pin `5` goes to the same `MAX202` device at package
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pad `13`
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- no other `CN1` pins were observed going to that `MAX202`
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Observed marking on the interface chip:
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- `MAX202`
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- `CSE 0107`
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Interpretation:
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- this is a very strong confirmation that the PT2 serial path is carried as a
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real RS-232-style interface through a dedicated line transceiver
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- it also strongly implies the other connector lines (`1`, `2`, `3`, `6`) are
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**not** just extra serial handshake pins to the same interface chip
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- the wake/session problem may therefore involve:
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- analog/video sense inputs
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- separate return/reference behavior
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- or higher-level protocol/state expectations beyond the RS-232 channel alone
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Refined serial-ground read:
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- because the two `S. DATA GND` lines are capacitor-coupled to common ground,
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the serial interface likely expects a somewhat cleaner/dedicated return
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structure than a naive "everything tied straight together" hookup
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- this does **not** by itself explain the missing wake/session behavior
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- but it does support the idea that Sony treated the remote link as a proper
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interface with controlled grounding rather than as a casual single-ground
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wiring bundle
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### Important Open Electrical Discrepancy
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The manual fragment for external pin `7` appears to describe:
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- `Zi >= 10 kohm`
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- high/open state around `4.5 +/- 0.5 V`
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- low state around `0 +/- 0.5 V`
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That does **not** read like a classic bipolar RS-232-level description.
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But the board tracing currently shows external pin `7` going into the `MAX202`
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at pad `13` (`R1IN` on a standard MAX202 pinout), while external pin `4` goes
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to pad `14` (`T1OUT`).
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So there is now a real discrepancy to resolve:
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1. the manual signal description for pin `7` looks logic/open style
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2. the board tracing looks like an RS-232 transceiver path
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Possible explanations to keep open for now:
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- the manual fragment may describe behavior at a different system boundary or
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for a slightly different revision/context
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- the Sony interface may be electrically unusual despite using a `MAX202`
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- there may be surrounding circuitry affecting how the line behaves at the
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connector
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For now, the safest conclusion is:
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- the signal names are strongly confirmed
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- the exact electrical behavior still needs reconciliation
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### Board Construction / Routing Note
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- The board appears to be a **2-layer PCB**
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- Components are populated on only **one side**
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- With transmitted light, traces appear visible on the opposite side, with no
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obvious evidence of hidden inner layers
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This matters because it makes visual trace-following more trustworthy and makes
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the connector routing conclusions stronger.
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### VBS Routing Observation
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New tracing observation:
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- `VBS (X) IN` and `VBS (G) IN` do **not** appear to run into the CPU/serial
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section directly
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- instead, they route to the side of the board toward an **empty connector
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position labeled `CN5`**
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- the only other obvious trace associated with that area appears to be ground
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Working interpretation:
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- the VBS lines may be routed primarily to an **unpopulated optional connector
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or daughterboard position**
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- this could mean:
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- the TX7 PCB was designed for a variant that used the VBS signals more
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directly
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- this particular board revision does not currently use them in the populated
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build
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- or the signals are simply passed through / made available without deep
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local processing
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Why this matters:
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- this weakens the earlier "VBS is definitely the missing wake input" theory
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- it does **not** eliminate it completely
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- but it does suggest the most immediate wake/session logic is still more likely
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to live in:
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- the serial path
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- the DIP/boot configuration
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- optional/unpopulated variant circuitry
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- or retained configuration in NVRAM/firmware
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## Additional Silkscreen / Board Markings
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Observed so far:
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@@ -571,3 +775,36 @@ Only if something changes meaningfully, then test:
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useful result.
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- If one setting produces a dramatically different boot state, stop and record
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it before going wider.
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## DIP Switch First-Pass Results
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The first single-bit sweep produced a useful answer:
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- the DIP switches are **not** inert
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- but they do **not** seem to act like a blunt "service mode on/off" in the
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simplest sense
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What changed visibly:
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- user reported that the first tested DIP setting briefly showed a **small
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cursor on the LCD**
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- the other single-bit settings looked the same visually
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What changed serially:
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- `S3-1` shifted the `A0 -> 90` startup family from:
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- `07 80 64 40 30 C9`
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to:
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- `07 80 E4 40 30 49`
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- `S2-3` suppressed the `A0 -> 90` branch entirely in the first pass
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- `S2-1` left `A0 -> 90` alive but appears to have flattened `A0 -> AF`
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Best current hardware interpretation:
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- the DIP banks very likely participate in **startup personality / mode
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selection**
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- they may not directly control "active vs inactive panel"
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- but they clearly can steer which startup-family surface the firmware exposes
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This is consistent with the earlier suspicion that `S2` + `S3` form a boot-time
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configuration byte rather than casual front-panel options.
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